JPH01291437A - Method of mounting semiconductor chip - Google Patents
Method of mounting semiconductor chipInfo
- Publication number
- JPH01291437A JPH01291437A JP63120469A JP12046988A JPH01291437A JP H01291437 A JPH01291437 A JP H01291437A JP 63120469 A JP63120469 A JP 63120469A JP 12046988 A JP12046988 A JP 12046988A JP H01291437 A JPH01291437 A JP H01291437A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- board
- wiring pattern
- bumps
- connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 239000000758 substrate Substances 0.000 claims description 11
- 239000000615 nonconductor Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 abstract description 6
- 229910052751 metal Inorganic materials 0.000 abstract description 6
- 230000006355 external stress Effects 0.000 description 4
- 230000002950 deficient Effects 0.000 description 3
- 239000010931 gold Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000005357 flat glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、回路基板にフェースアップで実装する半導体
チップの実装方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for mounting a semiconductor chip face-up on a circuit board.
（従来の技術）
従来のフェースアップによる半導体チップの実装方法に
ついて、第３図に・よりフィルムキャリヤ方式による方
法を、また、第４図でワイヤボンディングによる方法を
説明する。フェースアップによる実装は、半導体チップ
が回路基板と直接液しているので、フェースダウンに比
べて放熱の面で右利である。(Prior Art) Regarding the conventional face-up semiconductor chip mounting method, a method using a film carrier method will be explained with reference to FIG. 3, and a method using wire bonding will be explained with reference to FIG. Face-up mounting is advantageous in terms of heat dissipation compared to face-down mounting because the semiconductor chip is in direct contact with the circuit board.
第３図において、フィルムキャリヤ方式で実装するには
、まず、半導体チップ１の複数の電極端子２の上に接続
金属によってバンプ３を形成し、キャリヤフィルム（図
示せず）の複数のリード４と上記のバンプ３とを接合し
、キャリヤフィルムに半導体チップ１を装着する１次に
、キャリヤフィルムに装着された半導体チップ１を回路
基板５の上にフェースアップの形で接着して、回路基板
５の表面に形成された配線パターン６と上記のり−ド４
を接続した後、キャリヤフィルムから切り離すと、図に
示したフェースアップ実装が得られる。In FIG. 3, for mounting using the film carrier method, bumps 3 are first formed on a plurality of electrode terminals 2 of a semiconductor chip 1 using connecting metal, and then bumps 3 are formed on a plurality of leads 4 of a carrier film (not shown). First, the semiconductor chip 1 mounted on the carrier film is bonded to the bumps 3 described above and the semiconductor chip 1 is mounted on the carrier film. Next, the semiconductor chip 1 mounted on the carrier film is adhered face-up onto the circuit board 5. The wiring pattern 6 formed on the surface of the board 4
After connecting and separating from the carrier film, the face-up mounting shown in the figure is obtained.
第４図において、まず、半導体チップ１をフェースアッ
プの形で回路基板５の上に接着した後、半導体チップ１
の電極端子２と回路基板５の配線パターン６とをワイヤ
７で接続する。In FIG. 4, first, the semiconductor chip 1 is bonded face-up onto the circuit board 5, and then the semiconductor chip 1 is bonded onto the circuit board 5.
The electrode terminal 2 and the wiring pattern 6 of the circuit board 5 are connected by a wire 7.
（発明が解決しようとする課題）
しかしながら、上記の構成では、フィルムキャリヤ方式
はウェハ状態の半導体チップ１にバンプ３を形成する繁
雑なプロセスを必要とするため、半導体チップ１の歩留
りを下げたり、不良の半導体チップ１に高価な金（Ａｕ
）のような接続金属でバンプを形成するという無駄があ
るという問題があった。また１両方式が共にリード４や
ワイヤ７が半導体チップ１のパターン面の上部に出てい
るので、外からの応力等の影響に弱いという間開もあっ
た。(Problems to be Solved by the Invention) However, with the above configuration, the film carrier method requires a complicated process of forming bumps 3 on the semiconductor chip 1 in a wafer state, which may reduce the yield of the semiconductor chip 1. Expensive gold (Au) is added to the defective semiconductor chip 1.
) There was a problem in that it was wasteful to form bumps with connection metals such as. In addition, since the leads 4 and wires 7 of both types are exposed above the pattern surface of the semiconductor chip 1, there is also a gap that makes them susceptible to external stress.
本発明は上記の問題を解決するもので、高価な接続金属
を有効に使用し、半導体チップの歩留りを低下させるこ
ともなく、さらに、外部からの応力の影響を受けない半
導体チップの実装方法を提供するものである。The present invention solves the above problems, and provides a method for mounting semiconductor chips that effectively uses expensive connection metals, does not reduce the yield of semiconductor chips, and is not affected by external stress. This is what we provide.
（課題を解決するための手段）
上記の課題を解決するため、本発明は透光性の電気絶縁
体か、あるいは半導体チップに近い熱膨張係数を有する
電気的絶縁体からなる接続用基板に、各辺近傍に直角に
形成した複数の配線パターンの内側端部にバンプを設け
、これらのバンプに半導体チップの電極端子を接続する
。さらに、上記の複数の配線パターンの外側端部と回路
基板上の複数の配線パターンを、異方性導電ゴムを用い
て接続するものである。これにより、半導体チップは回
路基板上にフェースアップで実装される。(Means for Solving the Problems) In order to solve the above problems, the present invention provides a connection substrate made of a light-transmitting electrical insulator or an electrical insulator having a coefficient of thermal expansion close to that of a semiconductor chip. Bumps are provided at the inner ends of a plurality of wiring patterns formed at right angles near each side, and electrode terminals of the semiconductor chip are connected to these bumps. Furthermore, the outer ends of the plurality of wiring patterns described above and the plurality of wiring patterns on the circuit board are connected using anisotropic conductive rubber. Thereby, the semiconductor chip is mounted face up on the circuit board.
（作 用）
上記の構成によれば、接続用基板にバンプを形成するの
で、作業が容易であるばかりでなく、半導体チップの歩
留りに影響を与えない。また、不良の半導体チップに形
成することもないので、高価な接続金属の無駄使用がな
い。さらに、接続用基板が半導体チップおよび接続部を
保護するので、外部からの応力の影響を受けない。(Function) According to the above configuration, since the bumps are formed on the connection substrate, the work is not only easy but also does not affect the yield of semiconductor chips. Further, since it is not formed on a defective semiconductor chip, there is no waste of expensive connection metal. Furthermore, since the connection substrate protects the semiconductor chip and the connection portion, it is not affected by external stress.
（実施例）
本発明の一実施例を第１図および第２図により説明する
。第１図は接続用基板の側面図で、電気的絶縁体からな
る接続用基板８の表面には、その周縁に各辺に直角に複
数の接続用配線パターン９が形成され、さらにその内側
端部にそれぞれバンプ１０が形成されている。(Example) An example of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a side view of the connection board. On the surface of the connection board 8 made of an electrical insulator, a plurality of connection wiring patterns 9 are formed on the periphery at right angles to each side, and furthermore, on the inner edge thereof. A bump 10 is formed on each portion.
なお、接続用基板８に絶縁体で透光性をもつ。Note that the connection substrate 8 is an insulator and has translucency.
例えば平行平板ガラスを用いれば、半導体チップ１の電
極端子２の位置が確認できる。また、熱膨張係数が半導
体チップ１の材料のＳｉに近い、例えば低温焼成セラミ
ックスのような絶縁体を用いれば、熱膨張の違いによっ
て発生するバンプ１０の熱応力を小さくすることができ
る。For example, if parallel flat glass is used, the positions of the electrode terminals 2 of the semiconductor chip 1 can be confirmed. Further, by using an insulator such as low-temperature fired ceramics, which has a coefficient of thermal expansion close to that of Si, which is the material of the semiconductor chip 1, thermal stress in the bumps 10 caused by the difference in thermal expansion can be reduced.
第２図は、上記の接続用基板８を用いて半導体チップ１
を回路基板５上にフェースアップで実装した状態を示す
側面図で、まず、半導体チップ１の電極端子２と接続用
基板８上に形成したバンプｌＯを加熱圧着により共晶接
合させ、半導体チップ１を接続用基板８に装着する。次
に、回路基板５の配線パターン６と上記の接続用配線パ
ターン９の外側端部との間に、一方向にのみ導通する異
方性導電ゴム１１を挿入した後、半導体チップ１を回路
基板５に接着し、接続用基板８の接続用配線パターン９
および回路基、板５の配線パターン６をそれぞれ異方性
導電ゴム１１に接触させ、電気的に導通するようにする
。異方性導電ゴム１１の厚さは、接続用基板８の接続用
配線パターン９と回路基板５の配線パターン６が電気的
導通をもち、しかもバンプ１０に過大の応力が掛からな
い程度とする。FIG. 2 shows a semiconductor chip 1 using the above connection board 8.
is a side view showing a state in which the semiconductor chip 1 is mounted face-up on a circuit board 5. First, the electrode terminals 2 of the semiconductor chip 1 and the bumps IO formed on the connection substrate 8 are eutectic bonded by thermocompression bonding, and the semiconductor chip 1 is mounted face-up on the circuit board 5. is attached to the connection board 8. Next, an anisotropic conductive rubber 11 that conducts in only one direction is inserted between the wiring pattern 6 of the circuit board 5 and the outer end of the connection wiring pattern 9, and then the semiconductor chip 1 is inserted into the circuit board. 5, and the connection wiring pattern 9 of the connection board 8
Then, the circuit board and the wiring pattern 6 of the board 5 are respectively brought into contact with the anisotropic conductive rubber 11 so as to be electrically conductive. The thickness of the anisotropic conductive rubber 11 is such that the connection wiring pattern 9 of the connection board 8 and the wiring pattern 6 of the circuit board 5 have electrical continuity, and that excessive stress is not applied to the bumps 10.
（発明の効果）
以上説明したように、本発明によれば、ウェハ状態の半
導体チップにバンプを形成する工程がないので、不良品
にバンプを形成する接続金属の無駄使いもなく、また、
半導体チップの歩留りを低下することもない。また、接
続用基板が半導体チップ自体および半導体チップと回路
基板との接続部を覆って保護するので、外からの応力の
影響を受けない、信頼性の高い実装方法となる。(Effects of the Invention) As explained above, according to the present invention, there is no step of forming bumps on a semiconductor chip in a wafer state, so there is no wastage of connection metal to form bumps on defective products, and
There is no reduction in the yield of semiconductor chips. Further, since the connection substrate covers and protects the semiconductor chip itself and the connection portion between the semiconductor chip and the circuit board, the mounting method is highly reliable and is not affected by external stress.
さらに、透光性の接続用基板を用いれば、半導体チップ
の装着時および接続用基板を介した実装時に、目視で位
置決め状態がａ察できるので、装着および実装が容易と
なる。また、半導体チップの基板と近い熱膨張係数の接
続用基板を用いれば、バンプに発生する熱応力を小さく
することができるので、信頼性の高い実装が可能となる
。Furthermore, if a light-transmitting connection board is used, the positioning state can be visually observed when mounting the semiconductor chip and mounting via the connection board, making mounting and mounting easier. Furthermore, by using a connection substrate with a coefficient of thermal expansion close to that of the semiconductor chip substrate, the thermal stress generated in the bumps can be reduced, allowing highly reliable mounting.
第１図は本発明で用いる接続用基板の側面断面図、第２
図は上記の接続用基板を用いフェースアップで半導体チ
ップを実装した状態を示す側面断面図、第３図は従来の
フィルムキャリヤ方式による実装状態を示す側面断面図
、第４図は従来のワイヤボンディング方式による実装状
態を示す側面断面図である。
１・・・半導体チップ、 ２・・・電極端子、 ３゜１
０・・・バンプ、 ４・・・リード、 ５・・・回路
基板、 ６・・・配線パターン、 ７・・・ワイヤ。
８・・・接続用基板、 ９・・・接続用配線パターン、
１１・・・異方性導電ゴム。
第１図
第２図
第３図
第４図Figure 1 is a side sectional view of the connection board used in the present invention, Figure 2 is
The figure is a side sectional view showing a state in which a semiconductor chip is mounted face-up using the above connection board, Figure 3 is a side sectional view showing a state in which it is mounted using a conventional film carrier method, and Figure 4 is a side sectional view showing a state in which a semiconductor chip is mounted face-up using the above connection board. FIG. 3 is a side cross-sectional view showing a mounting state according to the method. 1... Semiconductor chip, 2... Electrode terminal, 3゜1
0...Bump, 4...Lead, 5...Circuit board, 6...Wiring pattern, 7...Wire. 8... Connection board, 9... Connection wiring pattern,
11...Anisotropic conductive rubber. Figure 1 Figure 2 Figure 3 Figure 4
Claims (3)
線パターンを形成し、さらにその内側端部にバンプを形
成し、上記のバンプと半導体チップの電極端子を接合し
て半導体チップを装着した後、上記の接続用配線パター
ンと回路基板の配線パターンとの間に異方性導電ゴムを
挿入して電気的に接続することを特徴とする半導体チッ
プの実装方法。(1) Form a plurality of connection wiring patterns perpendicularly to each side on the periphery of the connection substrate, further form bumps on the inner edges, and bond the bumps and the electrode terminals of the semiconductor chip to form the semiconductor chip. 1. A method for mounting a semiconductor chip, comprising: inserting an anisotropic conductive rubber between the connection wiring pattern and the circuit board wiring pattern to electrically connect the wiring pattern to the circuit board.
ことを特徴とする請求項（１）記載の半導体チップの実
装方法。(2) The method for mounting a semiconductor chip according to claim (1), wherein a transparent electrical insulator is used as the connection substrate.
近い電気絶縁体を使用したことを特徴とする請求項（１
）記載の半導体チップの実装方法。(3) Claim (1) characterized in that an electrical insulator having a coefficient of thermal expansion close to that of a semiconductor chip is used as the connection substrate.
) mounting method of the semiconductor chip described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63120469A JPH01291437A (en) | 1988-05-19 | 1988-05-19 | Method of mounting semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63120469A JPH01291437A (en) | 1988-05-19 | 1988-05-19 | Method of mounting semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01291437A true JPH01291437A (en) | 1989-11-24 |
Family
ID=14786944
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63120469A Pending JPH01291437A (en) | 1988-05-19 | 1988-05-19 | Method of mounting semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01291437A (en) |
-
1988
- 1988-05-19 JP JP63120469A patent/JPH01291437A/en active Pending
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