JPH0319262A - Mounting structure of semiconductor device - Google Patents

Mounting structure of semiconductor device

Info

Publication number
JPH0319262A
JPH0319262A JP1154317A JP15431789A JPH0319262A JP H0319262 A JPH0319262 A JP H0319262A JP 1154317 A JP1154317 A JP 1154317A JP 15431789 A JP15431789 A JP 15431789A JP H0319262 A JPH0319262 A JP H0319262A
Authority
JP
Japan
Prior art keywords
semiconductor device
electrode
electrodes
metallized
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1154317A
Other languages
Japanese (ja)
Inventor
Nobuo Yamamoto
修生 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1154317A priority Critical patent/JPH0319262A/en
Publication of JPH0319262A publication Critical patent/JPH0319262A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the bending and the imperfect contact of a lead and improve the yield by connecting a clad wire between an electrode on a board and a metallized electrode, after a semiconductor device is mounted on the wiring board. CONSTITUTION:A semiconductor element is mounted on the inside of a ceramic substrate 1, and metallized electrodes 2 having electric conduction to the semiconductor element are arranged on the periphery of the upper surface. Then a semiconductor device is bonded on a printed wiring board 3; wiring electrodes 4 of a copper foil patterned on the board 3 and the electrodes 2 on the substrate 1 are subjected to solder connection by using insulative clad wires. The wires 5 of solder connection part 6 on the package side and solder connection part 7 on the board 3 side are subjected to solder connection by exfoliating the coating of the connection parts 6, 7. Thereby the imperfect fixing of outer leads and the bending of leads are not necessary to be considered, and the electrodes 2, 4 are precisely connected.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の実装構造に関し、特にフラットパ
ッケージ型半導体装置の外部リードの接続構造に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a mounting structure for a semiconductor device, and particularly to a connection structure for external leads of a flat package type semiconductor device.

〔従来の技術〕[Conventional technology]

従来、この種の半導体装置の構造を第4図に示す。外部
リード9は、タイパー10によって支持される形状にエ
ッチング又はプレス加工されたものである。LSIチッ
プを搭載するセラミック基板1上面外周部に配列された
メタライズ電極2に外部リード9を銀一銅(Ag−Cu
)ろう付けすることにより、セラミックフラットパッケ
ージ型の半導体装置が構成される。ここでタイパー10
は外部リード9の変形を防止し、リードろう付け及びろ
う付け後のハンドリングを可能とするものであった。こ
のように製造されたセラミックパッケージ(フラットパ
ッケージ)は、半導体装置メーカーにおいて半導体素子
の搭載,封止,リード或形(タイバー切断,及びリード
曲げ或形),選別等の工程を経て、半導体装置として完
威される。
The structure of a conventional semiconductor device of this type is shown in FIG. The external lead 9 is etched or pressed into a shape that is supported by the tieper 10. External leads 9 are connected to metalized electrodes 2 arranged on the outer periphery of the upper surface of the ceramic substrate 1 on which the LSI chip is mounted.
) By brazing, a ceramic flat package type semiconductor device is constructed. here typer 10
This prevents deformation of the external lead 9 and enables lead brazing and handling after brazing. The ceramic package (flat package) manufactured in this way goes through processes such as mounting the semiconductor element, sealing, shaping the leads (tie bar cutting and bending or shaping the leads), and sorting at the semiconductor device manufacturer, and then becomes a semiconductor device. It will be completely destroyed.

第5図(a)および(b)に示されるように、ガラスエ
ポキシ等にプリント配線基板14に実装される際は、エ
ッチングによりパターンニングされた配線電極4列、た
とえば銅箔電極列に対し、バッケージの外部リード9を
位置合わせした後、半田リフロー等により機械的,電気
的に接続されていた。
As shown in FIGS. 5(a) and 5(b), when mounted on the printed wiring board 14 using glass epoxy or the like, four rows of wiring electrodes patterned by etching, for example, a row of copper foil electrodes, are After positioning the external leads 9 of the package, they were mechanically and electrically connected by solder reflow or the like.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

現在要求されている半導体装置は半導体素子の高集積化
に伴うパッケージの多ビン化があげられる。従ってガラ
スエボキシ等のプリント配線基板の配線実装密度の向上
に伴い、パッケージ外部リードピッチのファイン化(0
.4mmpitch以下)が必要である。
Currently, semiconductor devices are required to have multiple bins in packages due to the higher integration of semiconductor elements. Therefore, as the wiring mounting density of printed wiring boards such as glass epoxy improves, the package external lead pitch becomes finer (0.
.. 4mm pitch or less) is required.

上述した従来の半導体装置は、パッケージ外周に配列さ
れたメタライズ電極に外部リードをろう付けする時に、
メタライズ電極ピッチとメタライズ幅が小さく (ピッ
チ0. 4 mm以下)なると、セラミック焼戒時の寸
法ばらつきにより、外部リードろう付け位置がメタライ
ズ電極からはみ出すため、セラミックパッケージの製造
歩留の低下、すなわち、パッケージ単価の上昇につなが
るという欠点があるゆまた、半導体素子の搭載,ワイヤ
ーボンディング,封止,仕上げ,選別等の組立工程にお
けるパッケージのハンドリングにより、リード曲がり不
良の発生があり、歩留低下をひきおこす問題点があった
。次に、タイバー切り離しを伴うリード切断,リード曲
げ戒形等の工程においてもリード曲がり等が発生する可
能性がある。
In the conventional semiconductor device described above, when the external leads are brazed to the metallized electrodes arranged around the outer periphery of the package,
When the metallized electrode pitch and metallized width are small (pitch 0.4 mm or less), the external lead brazing position protrudes from the metallized electrode due to dimensional variations during ceramic firing, resulting in a decrease in the manufacturing yield of ceramic packages. In addition, it has the disadvantage of increasing the unit price of the package, and handling of the package during assembly processes such as semiconductor element mounting, wire bonding, sealing, finishing, and sorting can lead to lead bending defects, which causes a decrease in yield. There was a problem. Next, there is a possibility that lead bending may occur during processes such as lead cutting and lead bending that involve separating tie bars.

更に選別工程において、ファインピッチの外部リードを
持つパッケージは、LSIテスタに付属するソケット電
極と外部リードとを正確に電気的接触させるため、外部
リード間のガイドな目的とする複雑かつ高価なキャリア
を必要としていた。
Furthermore, during the sorting process, packages with fine-pitch external leads require a complicated and expensive carrier that serves as a guide between the external leads in order to make accurate electrical contact between the socket electrodes attached to the LSI tester and the external leads. I needed it.

またこのキャリアをもってしても、完全な電気的接触は
保証されるものではなかった。
Moreover, even with this carrier, perfect electrical contact was not guaranteed.

そして、従来の半導体装置をガラスエポキシ配線基板に
実装する際、銅箔電極列に対する外部リードの位置合せ
も高い精度が要求されるという欠点がある。
Furthermore, when mounting a conventional semiconductor device on a glass epoxy wiring board, there is a drawback that high precision is required for positioning the external leads with respect to the copper foil electrode array.

〔目的〕〔the purpose〕

本実施例の目的は、配線基板への実装前に施される組立
工程においては、セラミック基板のメタライズ電極には
外部リードを取り付けず、配線基板上への装着後、配線
基板上の電極とメタライズ電極間に被覆導線を接続する
ことにより、組立工程中に生じるリード曲がり、電気的
接触不良等を防止し、組立作業性、製品の歩留の向上を
可能とする半導体装置の実装構造を提供するものである
The purpose of this example is that in the assembly process performed before mounting on the wiring board, external leads are not attached to the metallized electrodes of the ceramic board, and after mounting on the wiring board, the electrodes on the wiring board and the metallized To provide a semiconductor device mounting structure that prevents lead bending, electrical contact failure, etc. that occur during the assembly process by connecting a covered conductor between electrodes, and improves assembly workability and product yield. It is something.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置の実装構造は、半導体素子を搭載し
たセラミ,ク基板の上面外周部に、配列され、この半導
体素子と電気的に導通したメタライズ電極を有する半導
体装置において、この半導体装置をプリント配線基板等
に実装する際、この半導体装置のメタライズ電極と、こ
のメタライズ電極に対応するプリント基板上の配線電極
とを絶縁被覆導線によって接続するものである。
The semiconductor device mounting structure of the present invention is a semiconductor device having metallized electrodes arranged on the outer periphery of the upper surface of a ceramic substrate on which a semiconductor element is mounted and electrically connected to the semiconductor element. When mounted on a wiring board or the like, the metallized electrode of this semiconductor device and the corresponding wiring electrode on the printed circuit board are connected using an insulated conductive wire.

このような実装構造により、プリント基板への実装前に
施される諸組立選別工程におけるリードの変形,電気的
接触の不良等を生じる原因である外部リードを取り除き
、実装後に施される半導体装置とプリント基板との電気
的接続時のリード間ショートを防ぐものである. 〔実施例〕 次に本発明の第1実施例を図面を参照して説明する。
This mounting structure eliminates external leads that cause deformation of leads and poor electrical contact during the various assembly and sorting processes performed before mounting on a printed circuit board, and improves the reliability of semiconductor devices that are mounted after mounting. This prevents short circuits between leads when electrically connecting to a printed circuit board. [Example] Next, a first example of the present invention will be described with reference to the drawings.

第l図(a)に示すようにセラミック基板1内部に半導
体素子を搭載し、この半導体素子と電気的に導通してい
るメタライズ電極2を上面外周部に配列した半導体装置
において、ガラスエボキシ等のプリント配線基板実装前
に仕上げ工程,選別,バーイン等の作業を行う。その後
、第1図(b)および(C)に示すようにプリント配線
基板3上に接着剤等により半導体装置を装着し、このプ
リント配線基板3上にパターンニングされた銅箔等の配
線電極4と、セラミック基板1上面のメタライズ電極2
とを絶縁被覆導線5を用いて電気的に半田接続する。こ
の際、パッケージ側半田接続部6及びプリント配線基板
側半田接続部7における被覆導線5は半田接続部の被覆
をはがして半田接続する。
As shown in FIG. 1(a), in a semiconductor device in which a semiconductor element is mounted inside a ceramic substrate 1 and metallized electrodes 2 that are electrically connected to the semiconductor element are arranged on the outer periphery of the upper surface, a material such as glass epoxy is used. Finishing processes, sorting, burn-in, etc. are performed before mounting the printed wiring board. Thereafter, as shown in FIGS. 1(b) and 1(C), the semiconductor device is mounted on the printed wiring board 3 with an adhesive or the like, and wiring electrodes 4 such as copper foil patterned on the printed wiring board 3. and metallized electrode 2 on the top surface of ceramic substrate 1.
and are electrically connected by soldering using an insulated conductive wire 5. At this time, the coated conductive wires 5 in the package side solder connection part 6 and the printed wiring board side solder connection part 7 are connected by soldering after peeling off the coating of the solder connection part.

このような実装構造により、半導体装置実装前の諸工程
における外部リードの取り付け不良、リード曲がり等を
考慮する必要はない。またメタライズ電極とプリント基
板上の電極とを接続する被覆導線は、例えばワイヤポン
ディング装置等を任意に改良することにより精度良く、
取り付けることができる。
With such a mounting structure, there is no need to take into account poor attachment of external leads, bending of leads, etc. in various steps before semiconductor device mounting. In addition, the coated conductive wire that connects the metallized electrode and the electrode on the printed circuit board can be made with high precision by optionally improving the wire bonding device, etc.
Can be installed.

次に、第2図を用いて、第1の実施例を多端子構造の半
導体装置に適用した場合について説明する。第2図(a
) , (b)に示すように、セラミ,ク基板1′は、
セラミック積層2段構造となっており、セラミック基板
1′上面外周部に、下段メタライズ電極2′及び上段メ
タライズ電極2″をそれぞれ配列した構造となっている
。またプリント配線基板3′には、メタライズ電極2′
および2″に対応して下段配線電極4′および上段配線
電極4”が設けられている. まず、下段メタライズ電極2′と下段配線電極4′とを
下段被覆導線5′で第1の実施例と同様に半田接続し、
その次に第2図(c) , (d)に示すように上段メ
タライズ電極2″と上段配線電極4″とを上段被覆導線
5″で半田接続する.本適用例は第1図に示す実施例に
対し、被覆導線を用いることにより、リード間ショート
等が防止できるという特徴を生かし、外部リードである
被覆導線を高さ方向に2段以上配列することにより、半
導体装置の多端子化,高機能化に対処できるという特徴
がある。
Next, a case where the first embodiment is applied to a semiconductor device having a multi-terminal structure will be described using FIG. Figure 2 (a
), As shown in (b), the ceramic substrate 1' is
It has a two-tier ceramic laminated structure, with a lower metallized electrode 2' and an upper metallized electrode 2'' arranged on the outer periphery of the upper surface of the ceramic substrate 1'.Furthermore, the printed wiring board 3' has a metallized Electrode 2'
and 2'', a lower wiring electrode 4' and an upper wiring electrode 4'' are provided. First, the lower metallized electrode 2' and the lower wiring electrode 4' are connected by soldering with the lower coated conductor 5' in the same manner as in the first embodiment.
Next, as shown in FIGS. 2(c) and 2(d), the upper metallized electrode 2'' and the upper wiring electrode 4'' are connected by soldering with the upper coated conductor 5''.This application example is based on the implementation shown in FIG. For example, by taking advantage of the feature that short circuits between leads can be prevented by using coated conductor wires, by arranging coated conductor wires, which are external leads, in two or more stages in the height direction, semiconductor devices can have multiple terminals and high It has the characteristic of being able to handle functionalization.

第3図は本発明の第2の実施例を示す斜視図である。本
実施例ではメタライズ電極2と銅箔等の配線電極4とが
1対1に対応した個別の被覆導線を用いるのではなく、
メタライズ電極2と配線電極4の配線ピッチを合わせ、
被覆導線の代りに、このピッチに合わせて形威されたフ
ラットケーブル8を用いて半田接続したことを特徴とし
ている。
FIG. 3 is a perspective view showing a second embodiment of the invention. In this embodiment, the metallized electrode 2 and the wiring electrode 4 such as copper foil do not use separate covered conductor wires in a one-to-one correspondence.
Match the wiring pitch of metallized electrode 2 and wiring electrode 4,
It is characterized in that a flat cable 8 shaped to match this pitch is used for solder connection instead of a coated conductor.

この実施例ではセラミック基板1の各辺ごとにフラット
ケーブル8を一括で半田接続でき、作業性の向上,構造
の単純化及び外部リードの接続強度向上を図ることがで
きる利点がある。
In this embodiment, the flat cables 8 can be soldered to each side of the ceramic substrate 1 all at once, which has the advantage of improving workability, simplifying the structure, and increasing the connection strength of the external leads.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、外部リードが取り付けら
れていないフラットパッケージ型の半導体装置をプリン
ト配線基板等に実装し、外部リードとして被覆導線を用
いて半導体装置のメタライズ電極とプリント配線基板の
電極とを半田接続することにより、パッケージ製造メー
カーによるセラミック基板への外部リードのろう付けを
不要とし、製品の歩留を向上させ、パッケージ単価の低
減を図ることができる。また、半導体装置メーカーによ
る組立工程中のリード曲がり等を防止し、組立作業性及
び組立歩留を向上させると共に、選別時の作業性向上及
び選別ンケット構造の単純化を図ることができる。更に
、この半導体装置のプリント配線基板等への実装時、た
とえば、外部リードの配線電極への半田接続時に外部リ
ード曲がりによるリード間ショート等の不良を防止でき
る効果がある。
As explained above, the present invention mounts a flat package type semiconductor device to which no external leads are attached on a printed wiring board, etc., and uses a coated conductive wire as the external lead to connect the metallized electrode of the semiconductor device and the electrode of the printed wiring board. By making a solder connection between the two, it becomes unnecessary for the package manufacturer to braze the external leads to the ceramic substrate, thereby improving product yield and reducing the unit price of the package. Furthermore, it is possible to prevent lead bending during the assembly process by semiconductor device manufacturers, improve assembly workability and assembly yield, improve workability during sorting, and simplify the sorting box structure. Furthermore, when mounting this semiconductor device on a printed wiring board or the like, for example, when connecting external leads to wiring electrodes by soldering, it is possible to prevent defects such as short-circuiting between the leads due to bending of the external leads.

用例を示す斜視図、第2図(b)および(d)は第2図
(a)及び(c)の要部断面図、第3図は第2の実施例
を示す斜視図、第4図は従来例を示す斜視図、第5図(
a)は従来例の実装状態を示す斜視図、第5図(b)は
第5図(a)の要部断面図である。
FIG. 2(b) and (d) are sectional views of main parts of FIGS. 2(a) and (c); FIG. 3 is a perspective view showing the second embodiment; FIG. 4 is a perspective view showing a conventional example, and FIG.
FIG. 5(b) is a sectional view of a main part of FIG. 5(a).

1,1′・・・・・・セラミック基板、2.2’2″・
・・・・・メタライズ電極、3,3’・・・・・・プリ
ント配線基板、4.4’  4″・・・・・・配線電極
、5,5′,5″・・・・・・被覆導線、6・・・・・
・パッケージ側半田接続部、7・・・・・・ガラスエボ
キシ基板側半田接続部、8・・・・・・フラットケーブ
ル、9・・・・・・外部リード、10・・・・・・タイ
バー。
1,1'...Ceramic substrate, 2.2'2''・
...Metallized electrode, 3,3'...Printed wiring board, 4.4'4"...Wiring electrode, 5,5',5"... Covered conductor, 6...
・Package side solder connection part, 7...Solder connection part on glass epoxy board side, 8...Flat cable, 9...External lead, 10...Tie bar .

Claims (1)

【特許請求の範囲】[Claims]  半導体素子を搭載したセラミック基板の上面外周部に
、該半導体素子と電気的に接続されたメタライズ電極が
配列された半導体装置を、プリント配線基板上に実装す
る構造において、前記半導体装置のメタライズ電極と該
プリント配線基板上に前記メタライズ電極に対応して形
成された配線電極とを絶縁被覆導線を用いて接続したこ
とを特徴とする半導体装置の実装構造。
In a structure in which a semiconductor device is mounted on a printed wiring board, in which metallized electrodes electrically connected to the semiconductor element are arranged on the outer periphery of the upper surface of a ceramic substrate on which a semiconductor element is mounted, the metallized electrode of the semiconductor device and the metallized electrode of the semiconductor device are arranged. A mounting structure for a semiconductor device, characterized in that a wiring electrode formed on the printed wiring board corresponding to the metallized electrode is connected using an insulated conductive wire.
JP1154317A 1989-06-15 1989-06-15 Mounting structure of semiconductor device Pending JPH0319262A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1154317A JPH0319262A (en) 1989-06-15 1989-06-15 Mounting structure of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1154317A JPH0319262A (en) 1989-06-15 1989-06-15 Mounting structure of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0319262A true JPH0319262A (en) 1991-01-28

Family

ID=15581483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1154317A Pending JPH0319262A (en) 1989-06-15 1989-06-15 Mounting structure of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0319262A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6062757A (en) * 1995-08-30 2000-05-16 L'oreal Portable packaging unit for a product such as mascara
KR100445594B1 (en) * 2002-07-31 2004-08-25 주식회사 요진코스메플라스트 Make-up brush

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6062757A (en) * 1995-08-30 2000-05-16 L'oreal Portable packaging unit for a product such as mascara
KR100445594B1 (en) * 2002-07-31 2004-08-25 주식회사 요진코스메플라스트 Make-up brush

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