JPH0793402B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0793402B2 JPH0793402B2 JP19758688A JP19758688A JPH0793402B2 JP H0793402 B2 JPH0793402 B2 JP H0793402B2 JP 19758688 A JP19758688 A JP 19758688A JP 19758688 A JP19758688 A JP 19758688A JP H0793402 B2 JPH0793402 B2 JP H0793402B2
- Authority
- JP
- Japan
- Prior art keywords
- leads
- lead
- frame
- base material
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structure Of Printed Boards (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） 本発明は半導体素子に係わり、特に多数の入出力端子と
してのリードを備えた半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a semiconductor element, and more particularly to a semiconductor device having a large number of leads as input / output terminals.
（従来の技術） 従来、半導体装置におけるパッケージ構造としては、DI
P,FP,PLCC及びセラミック・パッケージ等が一般に知ら
れている。(Prior Art) Conventionally, as a package structure in a semiconductor device, DI
P, FP, PLCC and ceramic packages are generally known.
そして、これらのパッケージの入出力端子であるリード
は、リードレス・チップ・キャリアを除いて、そのいず
れもが電気的特性を得る上からも夫々互いに独立し絶縁
された状態で並列的にパターニングされ、そのインナー
リードはパッケージの内部に、アウターリードはパッケ
ージ外部に突出させて配置されていた。The leads, which are the input / output terminals of these packages, are patterned in parallel with each other being insulated from each other in order to obtain electric characteristics except for the leadless chip carrier. The inner lead was arranged so as to project inside the package, and the outer lead was arranged so as to project outside the package.
（発明が解決しようとする問題点） このため、各アウターリードは個々に曲り得る状態にあ
って曲り易く、しかも各リード間の相対位置精度も±0.
1mm程度しか確保することができなかった。(Problems to be solved by the invention) Therefore, each outer lead is easily bendable because it is bendable individually, and the relative position accuracy between the leads is ± 0.
We could only secure about 1 mm.
また、加工上及び実装上等において、各リードが独立し
て変形しないようにするためには、リードの材質、厚
さ、リード幅及びリード間ピッチも制限を受けていた。Further, in processing and mounting, in order to prevent each lead from being independently deformed, the lead material, thickness, lead width and lead pitch are also limited.
例えば、FP（フラット・パッケージ）においては、リー
ド厚さは0.15mmで、リード幅はアウターリードで0.35m
m、インナーリード基端で0.15mm、リード間ピッチはア
ウターリードで0.65mm、インナーリード基端で0.3mm程
度が最小限であるのが現状で、このためピン数が増加す
るに伴い、パッケージのアウターリード先端部の全体外
形が大きくなり、パッケージの大きさはこれによりかな
り大きくなってきている。For example, in FP (flat package), the lead thickness is 0.15mm and the lead width is 0.35m for the outer leads.
m, the inner lead base is 0.15 mm, the lead-to-lead pitch is 0.65 mm for the outer leads, and the inner lead base is about 0.3 mm, which is the minimum.As a result, as the number of pins increases, the package The outer shape of the outer lead tip has become large, and the size of the package has become considerably large.
上記の制限は、半導体装置をプリント基板等に実装する
際の半田付け工程において、リード位置精度が±0.1mm
程度しか確保できないのが現状であったため、特にリー
ドピッチ間の間隔の縮小が一般に困難であった。The above limitation is that the lead position accuracy is ± 0.1 mm in the soldering process when mounting a semiconductor device on a printed circuit board, etc.
Since it is currently possible to secure only a certain degree, it is generally difficult to reduce the interval between the lead pitches.
また、リード材質の選定においても、このような細いリ
ード自体の機械的強度を確保するため、ニッケルを含む
鉄合金（42アロイ）等の高強度特性を有することがリー
ドに要求されていた。Further, also in the selection of the lead material, in order to secure the mechanical strength of such a thin lead itself, the lead is required to have high strength characteristics such as an iron alloy containing nickel (42 alloy).
本発明は上記に鑑み、特に多数の入出力端子を有する半
導体装置において、プリント基板への実装特性、即ちリ
ード位置精度の向上及びリードピッチの縮小を図ってパ
ッケージサイズを縮小することにより実装密度の向上を
図り、多数ピン半導体装置のパッケージ機能の向上を図
ったものを提供することを目的とする。In view of the above, the present invention provides a semiconductor device having a large number of input / output terminals, in which the mounting characteristics on the printed circuit board, that is, the lead position accuracy is improved and the lead pitch is reduced to reduce the package size to reduce the mounting density. It is an object of the present invention to improve the package function of a multi-pin semiconductor device.
（問題点を解決するための手段） 本発明は上記目的を達成するため、本発明における半導
体装置は、例えば、Al基板、銅基板または鉄合金基板等
の金属板状の基材の一面に絶縁層を積層し、この絶縁層
の表面に互いに電気的に絶縁され略中央から縁部に延び
る複数のリードをパターニングし前記基材の周縁を下方
に屈曲させて縦断面皿形に形成するとももに上記リード
のアウターリードの端部を接合されるプリント基板の表
面から離反する方向へ曲げてフレームを形成し、このフ
レームの絶縁層側の中央部に半導体素子をマウントする
とともに、該半導体素子の電極と上記各リードの中央側
基端のインナーリードとを夫々電気的に接続させたも
の、及び周縁を下方に屈曲させて縦断面皿形に形成した
基材の内周面側裏面に、互いに電気的に絶縁され略中央
部から縁部に延びる複数のリードをパターニングすると
ともに上記リードのアウターリードの端部を接合される
プリント基板の表面から離反する方向へ曲げてフレーム
を形成し、このフレームの内周面側裏面の中央部に半導
体素子をマウントするとともに、該半導体素子の電極と
上記各リードの中央側基端のインナーリードとを夫々電
気的に接続させたものである。(Means for Solving the Problems) In order to achieve the above object, the present invention provides a semiconductor device in which, for example, an insulating film is formed on one surface of a metal plate-shaped substrate such as an Al substrate, a copper substrate, or an iron alloy substrate. By stacking layers, a plurality of leads, which are electrically insulated from each other and extend from a substantially central portion to an edge portion, are patterned on the surface of the insulating layer, and the peripheral edge of the base material is bent downward to form a vertical cross-sectional dish shape. The outer lead ends of the leads are bent in a direction away from the surface of the printed circuit board to be joined to form a frame, and the semiconductor element is mounted at the center of the insulating layer side of the frame, and An electrode and an inner lead at the center side base end of each of the leads are electrically connected to each other, and on the inner peripheral surface side rear surface of the base material formed by bending the peripheral edge downward to form a dish-shaped cross section, Electrically disconnected A plurality of leads extending from the substantially central portion to the edge portion are patterned, and the end portions of the outer leads of the leads are bent in a direction away from the surface of the printed circuit board to be joined to form a frame. A semiconductor element is mounted on the central portion of the side and back surfaces, and the electrodes of the semiconductor element and the inner leads of the base ends of the respective leads are electrically connected to each other.
（作 用） 上記のように構成した本発明によれば、電気的には絶縁
されたリードを共通の基材で保持させ、これにより各リ
ードの機械的強度を増大させるとともに、リードの微細
加工を可能として、位置精度の向上を図り、更に、プリ
ント基板等への実装を行う上で、パッケージ機能の向上
を図ることができる。(Operation) According to the present invention configured as described above, electrically insulated leads are held by a common base material, thereby increasing the mechanical strength of each lead and performing fine processing of the lead. Therefore, it is possible to improve the positional accuracy, and further to improve the package function when mounting on a printed circuit board or the like.
（実施例） 図面は本発明の一実施例を示すもので、半導体素子１は
接着剤２を介して周縁を下方に屈曲させて縦断面皿形に
屈曲成形した矩形状のフレーム３の内周側裏面の中央部
に接着されている。(Embodiment) The drawings show an embodiment of the present invention, in which a semiconductor element 1 has an inner periphery of a rectangular frame 3 which is bent and shaped into a dish shape in a vertical cross section by bending the peripheral edge downward with an adhesive 2. It is adhered to the center of the back and side.
このフレーム３は、例えば厚さ1mm以下のAl基板等の金
属状の基材４の一面に数十μｍ程度のエポキシ樹脂から
なる樹脂層５を積層し、この樹脂層５の表面に互いに電
気的に絶縁され略中央部から縁部に延びる、例えば1/2
オンス（厚さ17μｍ）または１オンス（厚さ35μｍ）の
銅箔からなる複数のリード６をパターニングし、更に樹
脂層５を下側として下方に屈曲成形したものである。The frame 3 has a resin layer 5 made of an epoxy resin of several tens of μm laminated on one surface of a metallic base material 4 such as an Al substrate having a thickness of 1 mm or less, and the surface of the resin layer 5 is electrically connected to each other. Is insulated from and extends from the center to the edge, for example, 1/2
A plurality of leads 6 made of ounce (thickness 17 μm) or 1 ounce (thickness 35 μm) copper foil are patterned, and further bent downward with the resin layer 5 as the lower side.
このフレーム３の製造は、例えば一般のリードフレーム
のように、上記基材４の構成部分を連続して設けた1mm
以下のAl製板状体の一面に、数十μｍ程度のエポキシ樹
脂からなる樹脂層５を積層し、この樹脂層５を表面全体
に、1/2オンス（厚さ17μｍ）または１オンス（厚さ35
μｍ）の銅箔をラミネートし、しかる後、表裏両面から
エッチングを施して、リード６をパターニングするとと
もに、基材４の周囲をその隅部を残してエッチングす
る。そして、プレスによる絞り加工を施して屈曲させた
後、各フレーム３毎に分離することにより行うことがで
きる。This frame 3 is manufactured by, for example, a general lead frame having a 1 mm portion in which the constituent parts of the base material 4 are continuously provided.
A resin layer 5 made of an epoxy resin having a thickness of several tens of μm is laminated on one surface of the following aluminum plate-like body, and the resin layer 5 is formed on the entire surface by 1/2 ounce (thickness 17 μm) or 1 ounce (thickness). 35
(1 μm) copper foil is laminated, and thereafter, etching is performed from both front and back surfaces to pattern the leads 6, and the periphery of the base material 4 is etched leaving its corners. Then, it can be performed by subjecting each frame 3 to each other after being subjected to a drawing process by a press and bending.
上記基材４としては、本実施例では機械的成形が可能な
Al基板を使用しているが、他の金属板、例えば銅基板や
42アロイ等の鉄合金基板を使用することができ、このよ
うに、金属製の基材４を使用することにより、半導体素
子１の放熱性の向上を図るようにすることができる。The base material 4 can be mechanically molded in this embodiment.
I am using an Al substrate, but other metal plates such as a copper substrate or
An iron alloy substrate of 42 alloy or the like can be used, and by using the metal base material 4 in this way, the heat dissipation of the semiconductor element 1 can be improved.
更に、この基材４として、成形可能な、例えば金属ワイ
ヤもしくは網状金属を芯材としたエポキシ樹脂もしくは
ポリイミド樹脂等のプラスチック基材を使用しても良
く、この場合樹脂層を積層することなく、プラスチック
基材により直接リードをパターニングすることによりフ
レームを構成することができ、また予め屈曲成形させた
プラスチック基材を使用してフレームを構成するように
することもできる。Further, as the base material 4, a moldable plastic base material such as an epoxy resin or a polyimide resin having a metal wire or a mesh metal as a core material may be used, and in this case, without laminating a resin layer, The frame can be formed by directly patterning the leads with the plastic base material, or the frame can be formed by using a plastic base material that is pre-bent and molded.
また、リード６は、インナーリード6aとアウターリード
6bとからなり、上記のように銅箔をエッチングすること
により成形されるのであるが、この場合、この各リード
６の位置精度は、銅箔のエッチング精度により決まる。In addition, the lead 6 includes an inner lead 6a and an outer lead.
6b and is formed by etching the copper foil as described above. In this case, the positional accuracy of each lead 6 is determined by the etching accuracy of the copper foil.
ここでは、このリード６は、インナーリード6aの基端に
おいて、0.05mmの線幅（T1＝0.05mm）で、0.05mmの線間
スペース（T2＝0.05mm）にて、0.1mmのピッチ（P1＝0.1
mm）で、アウターリード6bの先端において、0.1mmの線
幅（t1＝0.1mm）で、0.1mmの線間スペース（t2＝0.1m
m）にて、0.2mmピッチ（P2＝0.2mm）で形成されてい
る。Here, the lead 6 has a line width of 0.05 mm (T 1 = 0.05 mm) and a space between lines of 0.05 mm (T 2 = 0.05 mm) and a pitch of 0.1 mm at the base end of the inner lead 6a. (P 1 = 0.1
mm) at the tip of the outer lead 6b with a line width of 0.1 mm (t 1 = 0.1 mm) and a space between lines of 0.1 mm (t 2 = 0.1 m
m), it is formed with a pitch of 0.2 mm (P 2 = 0.2 mm).
このようにして、各リード６を基材４で保持したフレー
ム３を形成することにより、この各リード６の機械的強
度を確保して、各リード６の位置精度の向上及びリード
ピッチの縮小化を図るようにすることができる。By thus forming the frame 3 in which each lead 6 is held by the base material 4, the mechanical strength of each lead 6 is ensured, and the positional accuracy of each lead 6 is improved and the lead pitch is reduced. Can be set.
このインナーリード6aの中央側の基端と半導体素子１の
電極とはボンディングワイヤ７でボンディングされ、更
に半導体素子１は保護用コーティング樹脂等の封止樹脂
８で樹脂封止されて半導体装置が構成されている。The central end of the inner lead 6a and the electrode of the semiconductor element 1 are bonded with a bonding wire 7, and the semiconductor element 1 is resin-sealed with a sealing resin 8 such as a protective coating resin to form a semiconductor device. Has been done.
なお、上記ワイヤボンディングに限ることなく、125μ
ｍ程度のポリイミドフィルムに35μｍ程度の銅箔をラミ
ネートして、エッチングによりパターニングを施したキ
ャリアテープを使用してボンディングを行う、いわゆる
TAB方式で半導体装置を構成することもできる。また、
この半導体装置の場合、ICカード等にも利用するように
することができる。Not limited to the above wire bonding, 125 μ
A copper foil of about 35 μm is laminated on a polyimide film of about m, and bonding is performed by using a carrier tape patterned by etching.
The semiconductor device can also be configured by the TAB method. Also,
In the case of this semiconductor device, it can be used for an IC card or the like.
更に、ポッティングによりフレーム３の凹部内に樹脂を
注入して半導体素子１をコーティングする他に、モール
ド樹脂により半導体素子１を樹脂封止して、信頼性の向
上を図るようにすることもできる。Further, in addition to injecting a resin into the concave portion of the frame 3 by potting to coat the semiconductor element 1, the semiconductor element 1 may be resin-sealed with a molding resin to improve reliability.
また、上記基材４の周縁端部4aは縦断面円状に屈曲成形
されている。この周縁4aは第１図に示すように、このア
ウターリード6aとプリント基板９とを半田付け10により
電気的に接続させるためのものであるが、第４図（ａ）
で示すようにＶ字状に成形したり、同図（ｂ）で示すよ
うに立ち上がらせて形成しても良く、この形状はプリン
ト基板９とパッケージの形状により任意に選択すること
ができる。Further, the peripheral edge portion 4a of the base material 4 is bent and formed in a circular cross section. As shown in FIG. 1, this peripheral edge 4a is for electrically connecting the outer lead 6a and the printed circuit board 9 by soldering, and FIG.
It may be formed in a V-shape as shown in FIG. 2 or may be formed so as to stand up as shown in FIG. 3B, and this shape can be arbitrarily selected depending on the shapes of the printed board 9 and the package.
本発明は上記のような構成であるので、多数の入出力端
子を有する半導体装置において、リードピッチの縮小を
図って、パッケージを大きさを減少させ、しかもリード
位置精度を向上させて、プリント基板等への実装時の接
続を容易にすることができる。Since the present invention has the above-described configuration, in a semiconductor device having a large number of input / output terminals, the lead pitch can be reduced, the package size can be reduced, and the lead position accuracy can be improved. It is possible to facilitate the connection at the time of mounting on the device.
また、製造工程を簡略化させてコストの低減を図ること
ができるばかりでなく、特にリードの変形による製造不
良を減少させることができ、更に、半導体装置全体を基
材でカバーするため、装置の信頼性を向上させることが
できる。Further, not only the manufacturing process can be simplified and cost can be reduced, but also manufacturing defects due to deformation of leads can be particularly reduced, and furthermore, since the entire semiconductor device is covered with the base material, The reliability can be improved.
しかも、リードパターンの微細加工が可能となり、半導
体素子の電極間ピッチとインナーリード間ピッチを近付
けて、この電気的接続を容易に行うことができる。Moreover, the lead pattern can be finely processed, and the pitch between the electrodes of the semiconductor element and the pitch between the inner leads can be made close to each other to facilitate the electrical connection.
更に、基材として金属板を使用することにより、半導体
素子の放熱性の向上を図るようにすることができるとい
った効果がある。Furthermore, by using a metal plate as the base material, there is an effect that the heat dissipation of the semiconductor element can be improved.
アウターリードの端部が半田付け等によって接合される
プリント基板の表面から離反する方向へ曲げられている
ので、フレームの内側と外側との両側からアウターリー
ドをプリント基板表面上の回路端子に半田付け可能であ
り、アウターリードの端部がプリント基板の表面に平行
に延びている場合等に比べて、アウターリードの端部と
プリント基板表面上の回路端子との接触部に半田を流れ
易くすることができる。この結果、小量の半田を用いる
だけで必要な強度の半田付けが可能であり、半導体素子
の微細化に伴いアウターリード間の間隔が狭小化された
場合においてもアウターリード間を短絡させることなく
半田付けすることができる。Since the ends of the outer leads are bent in a direction away from the surface of the printed circuit board to which they are joined by soldering, etc., solder the outer leads to the circuit terminals on the printed circuit board surface from both the inside and outside of the frame. It is possible to make it easier for the solder to flow to the contact part between the end of the outer lead and the circuit terminal on the printed circuit board surface, compared to the case where the end of the outer lead extends parallel to the surface of the printed circuit board. You can As a result, it is possible to solder with the required strength by using only a small amount of solder, and even when the distance between the outer leads is narrowed due to the miniaturization of the semiconductor element, the outer leads are not short-circuited. Can be soldered.
また、アウターリードの端部が半田付け等によって接合
されるプリント基板の表面から離反する方向へ曲げられ
ているので、アウターリードがプリント基板表面上の回
路端子に所望な状態で半田付けできたか否かを視認しや
すくすることができる。Also, since the ends of the outer leads are bent in a direction away from the surface of the printed circuit board to which they are joined by soldering, etc., whether the outer leads could be soldered to the circuit terminals on the printed circuit board surface in the desired state. This makes it easier to see.
また、アウターリードの端部が半田付け等の接合される
プリント基板の表面から離反する方向へ曲げられている
ので、半田付けする前にアウターリードとプリント基板
表面上の回路端子との位置合わせを行う場合において、
アウターリードの端部とプリント基板表面上の回路端子
との接触部の位置を多方向から視認することができ、所
定の位置合わせができているか否かを容易に確認するこ
とができる。Also, since the ends of the outer leads are bent in a direction away from the surface of the printed circuit board to be joined, such as by soldering, align the outer lead with the circuit terminals on the printed circuit board surface before soldering. When doing,
The position of the contact portion between the end portion of the outer lead and the circuit terminal on the surface of the printed circuit board can be visually recognized from multiple directions, and it can be easily confirmed whether or not predetermined alignment is achieved.
また、金属板状の基材の一面に積層した絶縁層の表面に
複数のリードをパターニングして共通の基材でリードを
保持するようにしたので、アウターリードの端部をプリ
ント基板の表面から離反する方向へ曲げてフレームを形
成する場合に、複数のリードの相対位置関係を正確に維
持しつつリードを曲げることができる。Further, since a plurality of leads are patterned on the surface of the insulating layer laminated on one surface of the metal plate-shaped base material so that the leads are held by the common base material, the end portions of the outer leads are separated from the surface of the printed circuit board. When the frame is formed by bending in the separating direction, the lead can be bent while maintaining the relative positional relationship of the leads accurately.
第１図乃至第３図は本発明の一実施例を示し、第１図は
プリント基板に接続した状態を示す縦断正面図、第２図
はフレームを示す表面図、第３図は同じく裏面図、第４
図（ａ）及び（ｂ）は基材の周縁とプリント基板との夫
々異なる接続状態の要部を示す断面図である。 １……半導体素子、３……フレーム、４……基材、５…
…樹脂層、６……リード、6a……同インナーリード、6b
……同アウターリード、７……ボンディングワイヤ、９
……プリント基板。1 to 3 show an embodiment of the present invention. FIG. 1 is a vertical sectional front view showing a state of being connected to a printed circuit board, FIG. 2 is a front view showing a frame, and FIG. , 4th
FIGS. 10A and 10B are cross-sectional views showing a main part in a different connection state between the peripheral edge of the base material and the printed circuit board. 1 ... Semiconductor element, 3 ... Frame, 4 ... Base material, 5 ...
… Resin layer, 6 ... Lead, 6a ... Inner lead, 6b
...... Same outer lead, 7 ...... Bonding wire, 9
……Printed board.
Claims (3)
この絶縁層の表面に互いに電気的に絶縁され略中央部か
ら縁部に延びる複数のリードをパターニングし前記基材
の周縁を下方に屈曲させて縦断面皿形に形成するととも
に上記リードのアウターリードの端部を接合されるプリ
ント基板の表面から離反する方向へ曲げてフレームを形
成し、このフレームの絶縁層側の中央部に半導体素子を
マウントするとともに、該半導体素子の電極と上記各リ
ードの中央側基端のインナーリードとを夫々電気的に接
続させたことを特徴とする半導体装置。1. An insulating layer is laminated on one surface of a metal plate-shaped substrate,
A plurality of leads, which are electrically insulated from each other and extend from the substantially central portion to the edge portion, are patterned on the surface of the insulating layer to bend the peripheral edge of the base material downward to form a dish shape in longitudinal section, and outer leads of the leads. A frame is formed by bending the end portion of the frame in a direction away from the surface of the printed circuit board to be joined, and the semiconductor element is mounted on the center portion of the frame on the insulating layer side. A semiconductor device characterized in that it is electrically connected to an inner lead at the base end on the center side.
合金基板を使用したことを特徴とする請求項１記載の半
導体装置。2. The semiconductor device according to claim 1, wherein an A1 substrate, a copper substrate or an iron alloy substrate is used as the base material.
した基材の内周面側裏面に、互いに電気的に絶縁され略
中央部から縁部に延びる複数のリードをパターニングす
るとともに上記リードのアウターリードの端部を接合さ
れるプリント基板の表面から離反する方向へ曲げてフレ
ームを形成し、このフレームの内周面側裏面の中央部に
半導体素子をマウントするとともに、該半導体素子の電
極と上記各リードの中央側基端のインナーリードとを夫
々電気的に接続させたことを特徴とする半導体装置。3. A plurality of leads, which are electrically insulated from each other and extend from a substantially central portion to an edge portion, are formed on a back surface of an inner peripheral surface side of a base material having a dish-shaped longitudinal section with its peripheral edge bent downward. The ends of the outer leads of the leads are bent in a direction away from the surface of the printed circuit board to be joined to form a frame, and a semiconductor element is mounted at the center of the inner surface of the frame on the back surface thereof. 2. The semiconductor device, wherein the electrode and the inner lead at the base end on the center side of each lead are electrically connected to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19758688A JPH0793402B2 (en) | 1987-08-08 | 1988-08-08 | Semiconductor device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19844387 | 1987-08-08 | ||
| JP62-198443 | 1987-08-08 | ||
| JP19758688A JPH0793402B2 (en) | 1987-08-08 | 1988-08-08 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01132147A JPH01132147A (en) | 1989-05-24 |
| JPH0793402B2 true JPH0793402B2 (en) | 1995-10-09 |
Family
ID=26510449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19758688A Expired - Lifetime JPH0793402B2 (en) | 1987-08-08 | 1988-08-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0793402B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0357258A (en) * | 1989-07-26 | 1991-03-12 | Nec Kansai Ltd | Resin-molded electronic component |
| KR940008342B1 (en) * | 1990-06-01 | 1994-09-12 | 가부시키가이샤 도시바 | Semiconductor device using film carrier |
| JP2848682B2 (en) * | 1990-06-01 | 1999-01-20 | 株式会社東芝 | Semiconductor device for high-speed operation and film carrier used for this semiconductor device |
| DE69329542T2 (en) | 1992-06-05 | 2001-02-08 | Mitsui Chemicals, Inc. | THREE-DIMENSIONAL CIRCUIT, ELECTRONIC COMPONENT ARRANGEMENT USING THIS CIRCUIT AND MANUFACTURING METHOD FOR THIS CIRCUIT |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4147889A (en) * | 1978-02-28 | 1979-04-03 | Amp Incorporated | Chip carrier |
| JPS58105546A (en) * | 1981-12-17 | 1983-06-23 | Sony Corp | Semiconductor packaging |
| JPS6084845A (en) * | 1983-10-14 | 1985-05-14 | Matsushita Electric Works Ltd | Sealed semiconductor device |
| JPS61241954A (en) * | 1985-04-19 | 1986-10-28 | Hitachi Micro Comput Eng Ltd | Semiconductor device |
| JPS6321860A (en) * | 1986-07-15 | 1988-01-29 | Oki Electric Ind Co Ltd | Semiconductor device |
-
1988
- 1988-08-08 JP JP19758688A patent/JPH0793402B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01132147A (en) | 1989-05-24 |
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