JPH03191577A - Insulated-gate field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce the difference in level on the surface of an insulating film by a method wherein a gate electrode is formed in the whole region and at the upper part of a gate insulating film, a region which surrounds a contact hole region at one end of the gate electrode and whose conductivity type is opposite to that of a substrate is formed and a first high-concentration region and a second high-concentration region of a first conductivity type are formed. CONSTITUTION:A gate electrode 1 is formed, via a gate oxide film 7, inside element formation regions 2 partitioned by a field oxide film 6 formed selectively on one main surface of a P-type Si substrate 12; and a source region 3S and a drain region 3D, of an N-type, are formed respectively inside the element formation regions 2 on both sides of the gate electrode 1. An N-type region 11 is formed in the element formation regions 2 surrounding a contact hole 4 of the gate electrode 1; a first P<+> type region 13 is formed between one end of the gate electrode 1 and the field oxide film 6; and a second P<+> type region 14 is formed between the N-type region 11 and the source and drain regions 3S, 3D. Thereby, the difference in level on the surface of an insulating film 9 on the top can be made small.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulated gate field effect transistor, and more particularly to the structure of a MOS (MOS) transistor used in a semiconductor integrated circuit.

[Conventional technology]

A MOS (MOS) transistor used in a conventional semiconductor integrated circuit is formed by field oxidation M on a P-type Si substrate 12, as shown in FIG.
6 delimits a selectively formed element formation region 2, and the gate electrode 1 is provided above the field oxide film 6 and the element formation region 2.

The gate electrode 1 is covered with an insulating film 8, the contact hole 4 of the gate electrode 1 is located above the field oxide M6, the gate wiring 10 and the gate electrode 1 are electrically connected through this contact hole 4, and the gate wiring 10 is covered with an insulating film 9. It had a structure in which it was covered with

[Problem to be solved by the invention]

In the conventional MOS)-transistor described above, there is an insulating film surface level difference h 6 of about 1 μm between the surface of the insulating film 9 above the element formation region and the surface of the insulating film 9 above the field oxidation B 6 and above the contact hole 4. Therefore, there is a possibility that the wiring formed on the upper part of the insulating film 9 may be disconnected, or the gate wiring 10 and other wiring (not shown) formed on the upper part of the insulating film 9 may be short-circuited due to a break in the insulating film 9. There are drawbacks.

[Means to solve the problem]

The insulated gate field effect transistor of the present invention has a gate electrode provided through a gate insulating film in an element formation region defined by a field insulating film selectively provided on the ten surfaces of a first conductivity type semiconductor substrate. a source region and a drain region of a second conductivity type provided in the element formation region on both sides of the gate electrode; 1
A first high-concentration first conductivity type region selectively provided on a conductivity type semiconductor substrate; a second conductivity type region selectively provided on a semiconductor substrate; a second high concentration first conductivity type region provided between the second conductivity type region and the source and drain regions; and a second conductivity type region selectively provided in the semiconductor substrate; A gate wiring is provided above the mold region and connected to the gate electrode.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1(a) is a pattern layout diagram showing one embodiment of the present invention, and FIG. 1(b) is a cross-sectional view of the semiconductor chip taken along the line A--A in FIG. 1(a). However, in Figure 1 (a
), wiring layers such as gate wiring are not shown for convenience.

This embodiment uses a first conductivity type semiconductor substrate (P-type Si substrate 12).
) - field insulating film selectively provided on the main surface (
A gate electrode 1 is provided in an element formation region 2 divided by a field oxide film 6) via a gate insulating film (gate oxide film 7), and a gate electrode 1 is provided in an element formation region 2 on both sides of the gate electrode 1. A first high-concentration first region is selectively provided on the P-type Si substrate 12 across the element formation region 2, including the N-type source region 3S and drain region 3D, and directly under one end of the gate electrode 1. Conductivity type region (P+ type region 13)
, a second conductivity type region (N-type region 11) selectively provided in the P-type Si substrate 12 across the element formation region 2 including immediately below the other end of the gate electrode 1 and its vicinity; mold area 1
1, a second high concentration first conductivity type region (P+ type region 14) provided between the source region 3S and the drain region 3D, and a gate wiring 10 connected to the gate electrode 1 above the N type region 11. It is a MOS transistor with

Gate electrode 1 has a conventional structure and field oxidation M6
The thickness of the field oxide film 6, which protrudes from the surface of the P-type Si substrate 12, is 500t+m.
Therefore, the surface level difference of the insulating film 9 is smaller than the conventional level difference ha. In addition, the contact hole 4 of the gate electrode 1
is on the top of the thin gate oxide film 7, there is a possibility that the gate electrode 1 and the P-type Si substrate 12 may be short-circuited due to misalignment in the photolithography used to create the contact hole 4 and the gate electrode 1. Since the N-type region 11 is formed in the element formation region 2 surrounding the contact hole 4 of the electrode 1, the gate electrode 1 and the P-type Si substrate 12
will not short circuit. Further, a first P+ type region 13 is formed between one end of the gate electrode 1 and the field oxide film 6,
The path indicated by arrow q in FIG. 1(a) prevents leakage current from flowing between the source and drain. Further, a second P+ type region 14 is formed to prevent leakage current flowing between the N type region 11 and the source and train.

Since the level difference on the surface of the insulating film 9 on the surface of this MOS transistor becomes smaller, when used in a semiconductor integrated circuit, the possibility of disconnection of the wiring formed on the upper part of the insulating film 9 or short circuit between such wiring and the gate wiring can be reduced. .

FIG. 2(a) is a pattern layout diagram showing an example of application of one embodiment of the present invention, and FIG. 2(b) is a cross section of a semiconductor chip cut along the line 1-A in FIG. 2(a>). This application example is one in which two MOS transistors of one embodiment are arranged in parallel.

Contact hole 4a of each MOS transistor
,4. b is each gate electrode 1a.

1b and the element formation regions 2a, 2b in the N-type region 11, the N-type region 11 connects the parts of the element formation regions 2a, 2b surrounding the contact holes 4 of the two transistors and 2a, 2b. It is provided over the area 2C. Other parts are the same as in the previous embodiment. Each gate electrode 1 and N region 11 are connected by contact holes.
is conductive, and since the N-type region 11 is a common region of the two transistors, the gate electrodes of the two transistors are conductive. In one embodiment, N-type region 11 is connected to the gate electrode and P
However, in this application example, since the N-type region 11 is used as a wiring between gate electrodes, other Wiring can be passed through.

〔Effect of the invention〕

As explained above, in the present invention, the gate electrode is formed over the entire region of the gate insulating film, and a region of the opposite conductivity type (second conductivity type region) to the substrate surrounding the contact hole region at one end of the gate electrode is formed. and a first . By forming the second high-concentration first conductivity type region, the insulating film surface level difference is approximately 1/1 of the thickness of the field insulating film compared to the conventional structure.
2, and the possibility of short circuit between the gate electrode and the semiconductor substrate in the area surrounding the contact hole of the gate electrode due to misalignment when forming the gate electrode and contact hole is small. It also prevents leakage current from flowing between the second conductivity type region and the source and drain regions, and leakage current from flowing into the region between one end of the gate electrode and the field insulating film. In addition, since the second conductivity type region can be used as wiring between gate electrodes, the semiconductor 4
When used in an A product circuit, there is an effect that the degree of integration can be improved.

[Brief explanation of drawings]

FIG. 1(a) is a pattern layout diagram showing one embodiment of the present invention, FIG. 1(b) is a cross-sectional view of a semiconductor chip taken along line A-A in FIG. 1(a), and FIG. Figure (a) is a pattern layout diagram showing an application example of one embodiment, and Figure 2 (b) is a pattern layout diagram showing an application example of one embodiment.
3(a) is a pattern layout diagram showing a conventional example, and FIG. 3(l) is a cross-sectional view of a semiconductor chip taken along line A-A in FIG. 3(a). FIG. 3 is a cross-sectional view of the semiconductor chip taken along a section corresponding to line A. 1, la, lb --- gate electrode, 2, 2a, 2b. 2C...Element formation area, 3D, 3Da, 3Db...
Drain region, 3S, 3Sa, 3Sb-- Source region, 4.4a, 4b... Contact hole, 6... Field oxide film, 7... Gate oxide film, 8.9...
Insulating film, 10... Gate wiring, 11... N-type region,
12... P type Si substrate, 13... First P+ type region, 14... Second P+ type region.

Claims (1)

[Claims] A gate electrode provided via a gate insulating film in an element formation region partitioned by a field insulating film selectively provided on one main surface of a first conductivity type semiconductor substrate, and the device on both sides of the gate electrode. selectively provided in the first conductivity type semiconductor substrate across the element formation region including a source region and a drain region of the second conductivity type provided in the formation region, and immediately below one end of the gate electrode; The first
a second conductivity type selectively provided on the first conductivity type semiconductor substrate across the element formation region including directly below and in the vicinity of the other end of the gate electrode; a second high concentration first conductivity type region provided between the second conductivity type region and the source and drain regions; and a gate wiring connected to the gate electrode above the second conductivity type region. An insulated gate field effect transistor comprising: