JPH03191565A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the size of an element isolation region and to realize a high integration by a method wherein a MOS transistor is formed in a single- crystal silicon layer and a bipolar transistor is formed in a single-crystal silicon layer which has been epitaxially grown selectively only in a region which has been isolated electrically from it via an insulating layer. CONSTITUTION:An SiO2 film 2 which has been formed in a P-type silicon substrate 1 and a single-crystal silicon layer 3 near the surface are formed; and then, a field oxide film 6 is formed; a MOS transistor formation region 7 is partitioned. The field oxide film 6 and the SiO2 film 2 are etched sequentially; an opening part 9 is formed in a bipolar transistor formation region; implanted arsenic is diffused and activated; and an N<+> type buried layer 10 is formed. A single-crystal silicon layer 12 is grown in the opening part 9 by using a selective epitaxial technique; a bipolar transistor is formed inside the single-crystal silicon layer 12; and a MOS transistor is formed in the MOS transistor formation region 7. Thereby, the size of an element isolation region is reduced and a high integration can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a bipolar transistor and a MOS transistor are mounted together.

[Conventional technology]

A conventional semiconductor device has an N+ type buried layer 21 and a P+ type buried layer 22 on the entire surface of a P type silicon substrate 1, as shown in FIG.
are selectively provided, respectively, and an N- type epitaxial layer 23 is grown on the surface including the N+ type buried layer 21 and the P+ type buried layer 22. Next, P type impurities are selectively introduced into the N~ type epitaxial layer 23 to form a P type well 24 in the region including the P+ type buried layer 22. Next, channel strike, bar 2
A field oxide film 6 is selectively provided on the surface including the P-type well 24 selectively provided with a field oxide film 6 to define a bipolar transistor formation region and a MOS transistor formation region including the N+ type buried layer 21. Next, a collector contact region 26 connected to the N+ type buried layer 21 is formed in the bipolar transistor forming region, and a P type base region 27 and an N+ type emitter region 28 are provided to form a bipolar transistor. Further, in each of the MOS transistor formation regions, an N+ type source/drain region 31 and a P+ type source/drain region 32 are formed in alignment with a gate electrode 30 provided through a gate oxide film 29, thereby forming an N channel MOS transistor and a P+ type source/drain region 32. Each of the P-channel MOS transistors constitutes a Bi-CMO8 semiconductor device in which a bipolar transistor and an 0MO8 transistor are mounted together.

[Problem to be solved by the invention]

In a conventional semiconductor device, since many PN junctions exist inside a silicon substrate, it is not easy to reduce the size of an element isolation region for electrically isolating each transistor to several μm or less. In addition, a part of the above-mentioned PN junction forms a parasitic thyristor structure, which is a structure that can cause so-called latch-up phenomenon, which is one of the main factors that limits the high integration of semiconductor devices. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which the dimensions of the element isolation region are reduced and the latch-up phenomenon is eliminated to improve high integration.

[Means to solve the problem]

The semiconductor device of the present invention includes a buried insulating layer provided in a middle layer region of a - conductivity type semiconductor substrate, a single crystal semiconductor layer provided on the buried insulating layer, and an element formation region provided in the single crystal semiconductor layer. a plurality of element isolation regions for partitioning a plurality of element isolation regions; an opening provided through at least one of the element isolation regions and the buried insulating layer; and an inverse region provided on the semiconductor substrate exposed in the opening It has a conductive type epitaxial layer, a bipolar transistor provided in the epitaxial layer, and a MOS transistor provided in the element formation region.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1A to 1E are cross-sectional views of a semiconductor chip shown in order of steps for explaining a manufacturing method according to an embodiment of the present invention.

First, as shown in FIG. 1(a), a P-type silicon substrate l
The energy of accelerating high concentration of oxygen ions on the life surface of 180
keV, dose amount 2.2 x 10 "cm-" After ion implantation at a substrate temperature of approximately 550°C, a silicon oxide film was deposited on the surface to a thickness of 0.3 μm by vapor phase epitaxy.
Seven anneals for 6 hours were performed in a nitrogen atmosphere at 1300°C.
After recovering the implantation damage, a 0.5 μm thick 5iCh layer 2 buried inside the P-type silicon substrate and a 0.1 μm thick single crystal silicon layer 3 near the surface are formed.

Next, as shown in FIG. 1(b), a single crystal silicon layer 3
After providing a thermal oxide film 4 on the surface of the bipolar transistor, a silicon nitride film 5 is selectively provided on the thermal oxide film 4, and the single crystal silicon layer 3 is selectively oxidized using the silicon nitride film 5 as a mask. A field oxide film 6 reaching the SiOg layer 2 is formed as a formation region and an element isolation region of a MOS transistor, and a MOS transistor formation region 7 is defined.

Next, as shown in FIG. 1C, a photoresist film 8 is provided and patterned on the entire surface, and the field oxide film 6 and SiOx layer 2 are sequentially etched by reactive ion etching technology using the photoresist film 8 as a mask. An opening 9 is provided in the bipolar transistor formation region to expose the surface of the P-type silicon substrate 1.

Next, as shown in FIG. 1(d), arsenic ions are accelerated with an energy of 70 keV using the photoresist film 8 as a mask.
Ion implantation is performed at a dose of 5 x 10" am-2. Next, after removing the photoresist film 8, a few percent
A heat treatment is performed at a temperature of 1150° C. for 3 hours in a nitrogen gas atmosphere containing oxygen gas, and the implanted arsenic is diffused and activated to form an N+ type buried layer 10, and at the same time, on the surface of the P type silicon substrate l. A thermal oxide film 11 is formed to a thickness of about 50 nm, and damage caused by arsenic ion implantation is recovered.

Next, as shown in FIG. 1(e), after removing the thermal oxide film 11 with diluted HF solution, the silicon nitride film 5 is removed with heated phosphoric acid, and the openings 9 are formed using selective epitaxial technique. A single crystal silicon layer 12 is grown on the surface of the N+ type buried layer 10 to fill the inside of the opening 9.

Thereafter, a bipolar transistor is formed in the single-crystal silicon layer 12, and a P-channel MO8 transistor and an N-channel MO8 transistor are formed in the MOS transistor formation region, thereby forming a Bi-CMO8 type semiconductor device.

〔Effect of the invention〕

As explained above, the present invention reduces the dimensions of the element isolation region by forming a bipolar transistor in a single crystal silicon layer that is selectively epitaxially grown only in an electrically completely isolated region of a semiconductor substrate. As a result, the parasitic thyristor structure that causes the latch-up phenomenon can be eliminated, and as a result, high integration of Bi-CMO8 semiconductor devices can be achieved.

In addition, by forming a MOS (MOS) run sister in a single crystal silicon layer on an insulator, the parasitic capacitance between the source and drain and the parasitic capacitance between the wiring Q and the substrate can be reduced.
Since many PN junctions that existed in i-0MO8 can be eliminated, the parasitic capacitance caused by each junction can be reduced, resulting in the effect that the device can be made faster.

[Brief explanation of drawings]

FIGS. 1(a) to 1(e) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a manufacturing method according to an embodiment of the present invention;
FIG. 2 is a sectional view showing an example of a conventional semiconductor device. 1...P-type silicon substrate, 2...Si
O2 layer, 3... Single crystal silicon layer, 4...
...Thermal oxide film, 5...Silicon nitride film, 6...
...Field oxide film, 7...MOS) transistor formation region, 8...Photoresist film, 9
...Opening part, 10...N+ type buried layer,
11... Thermal oxide film, 12... Single crystal silicon layer, 21... N+ type buried layer, 22...
...P+ type buried layer, 23...N- epitaxial layer, 24...P type well, 25...
- Channel stopper, 26... Collector contact region, 27... P-type base region, 28...
...N+ type emitter region, 29...gate oxide film, 30...gate electrode, 31...
・N+ type source/drain region, 32...P+
Source/drain area.

Claims (1)

[Claims] A buried insulating layer provided in a middle layer region of a semiconductor substrate of one conductivity type, a single crystal semiconductor layer provided on the buried insulating layer, and a plurality of element isolations provided in the single crystal semiconductor layer to partition element formation regions. an opening provided through at least one of the element isolation regions and the buried insulating layer; an epitaxial layer provided on the semiconductor substrate exposed in the opening; 1. A semiconductor device comprising: a bipolar transistor provided; and a MOS transistor provided in the element formation region.