JPH03191547A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a short circuit even when a bonding wire comes into contact with a semiconductor element by any chance after the element has been assembled in a package or the like by a method wherein a dicing region is insulated electrically form a potential of a semiconductor substrate. CONSTITUTION:Ions using oxygen as a source are implanted into a region corresponding to a dicing line 3 during a semiconductor-device manufacturing process under conditions, e.g. at an acceleration energy of 250keV and at a dose of 2X10<16>cm<-2>. As a result, a region as a dicing line 3 is constituted of an insulator layer 4. Thereby, when a bonding wire 9 comes into contact with a semiconductor substrate 6 by a loop control error of the wire or by an external force such as a shock or the like, an electric signal of the bonding wire 9 is not short-circuited with a potential of the semiconductor substrate 6 because a contact part P is constituted of the insulator layer 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a dicing line region of a semiconductor device.

[Conventional technology]

Conventionally, semiconductor devices are cut from a semiconductor wafer into individual semiconductor elements using a dicing saw or the like. At this time,
A portion corresponding to the cutting margin of the semiconductor device KFi dicing saw is required, and the semiconductor device 2 shown in FIG. 5 is normally formed in this portion. A dicing line 3a is formed between the field oxide films 5 in an area in which a semiconductor substrate 6 is not covered.

[Problem to be solved by the invention]

In the conventional semiconductor device described above, since the dicing line is formed by the semiconductor substrate, the potential of the semiconductor substrate is applied to the surface of the dicing line.

Therefore, as shown in FIG. 6, the semiconductor element 2 is mounted on the lead frame 7 and the bonding wires 9
Regarding a semiconductor device that is ball-bonded by using the bonding wire 9, if the bonding wire 9 is not properly loop-controlled and an impact is applied to the wire after bonding, the bonding wire 9 will be damaged at the portion Pb in FIG. There is a drawback that the signal potential of the bonding wire is short-circuited with the potential of the semiconductor substrate 6 due to contact with the semiconductor substrate.

Means for Solving the C Line Problem] The semiconductor device of the present invention has a structure in which the dicing line is insulated from the potential of the semiconductor substrate, and ion implantation using oxygen and nitrogen as sources utilizes a PN junction. It is formed by

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a plan view of a semiconductor wafer during the manufacturing process of an AIFI semiconductor device. This semiconductor wafer 1 is made up of a group 9 of identical semiconductor elements 2, and these semiconductor elements 2 are arranged along a dicing line 3. After that, the semiconductor elements 2 are divided into individual semiconductor elements 2 using a cutting machine or the like, and then used for package assembly or the like.

FIG. 1(b) is an enlarged plan view of a portion A including the dicing line 3 in FIG.

FIG. 1 (C1 is a sectional view taken along line BB' in FIG. 1(b).

Field oxide film 5 is formed on semiconductor substrate 6 by a commonly used method.

In this embodiment, ion implantation using oxygen as a source is performed in the region corresponding to the dicing line 3 during the semiconductor device manufacturing process under conditions of an acceleration energy of 250 K e V and a dose of 2×1ocR, for example. The region of the dicing 1lJ3 is made to be composed of the insulator layer 4.

Here, the source of the ion implantation performed to form the insulating layer 4 is not limited to oxygen, but it is also possible to use a source of nitrogen or the like as long as the insulating layer 4 is formed.

FIG. 2 shows an example in which the semiconductor element shown in FIG. 1 is mounted on a lead frame 7, and a bonding wire 9 is ball-bonded onto a bonding pad 8.

At this time, if the bonding wire 9 comes into contact with the semiconductor substrate 6 due to an error in the loop control of the wire or an external force such as an impact, the contact portion P becomes the insulator layer 4, so that the electrical signal of the bonding wire 9 and the semiconductor substrate 6 potential will not cause a short circuit.

FIG. 3 is a plan view of a second embodiment of the invention.

In this embodiment, the area of the dicing line 3 is the exposed area of the substrate, that is, the P-type substrate unmatched area 11 and the N-well area 1.
Consists of 2. FIG. 4 is a plan view for explaining a mounting process using the semiconductor element of FIG. 3.

As can be seen from FIG. 4, the Hewell region 12 is located directly under the bonding wire 9, so that the contact portion P3 between the bonding wire 9 and the semiconductor substrate 6 is at the Hewell region 12 and the potential of the bonding wire 9 is increased. is P
Since the bonding wire 9 is in a reverse/< bias state with respect to the semiconductor substrate 6 of the type, a short circuit will not occur even if the bonding wire 9 contacts the semiconductor substrate 6.

In this example, the case where the contact portion 1o is constituted by an N-well is illustrated, but any layer may be used as long as it is an N-type conductivity type layer. Also,
It goes without saying that if the substrate is of N type, the contact portion should be formed of a 1.deg.P type layer.

〔Effect of the invention〕

As explained above, the present invention electrically insulates the dicing region from the potential of the semiconductor substrate in order to divide the semiconductor device into wafer (ml) devices, so that when assembled into a package etc. This has the effect that even if the bonding wire should come into contact with a semiconductor element, a short circuit will not occur.

[Brief explanation of drawings]

FIG.
3 is a partial plan view of a wafer according to the second embodiment of the present invention, and FIG. 4 is a sectional view for explaining the mounting process of the semiconductor device shown in FIG. 3. FIG. 5 is a plan view for explaining the process, FIG. 5 is a cross-sectional view of an example of a conventional semiconductor element, and FIG. 6 is a cross-sectional view for explaining the bonding process of the semiconductor element of FIG. 1... Semiconductor wafer, 2... Semiconductor element, 3...
- Dicing line, 4... Insulator layer, 5... Field oxide film, 6... Semiconductor substrate, 7... Lead frame, 8... Ponding pad, 9... Ponding wire , 1 C,, - place & II parallel bar 11-D Jul
Embroidery of Mt. beckoning mountain 噌^...Hewell area.

Claims (1)

[Claims] 1. A semiconductor device characterized in that a dicing region of a semiconductor element is insulated from a potential of a semiconductor substrate. 2. The semiconductor device according to item 1, wherein the dicing region is formed by ion implantation using ions such as oxygen or nitrogen as a source. 3. The semiconductor device according to item 1, wherein the dicing region utilizes a reverse bias of a PN junction.