JPH03191445A - Memory circuit device - Google Patents

Abstract

PURPOSE:To improve the reading efficiency of data from a memory by providing a circuit for detecting that all data for one line written in a line memory are 'H' or 'L' to the periphery of the memory. CONSTITUTION:The output D1 of an n-input NAND circuit 2a for inputting data to the line memory 1 goes the data input of the 1st FF 2c and outputted to an output Q1 by a clock, the inverse of WE. When all the input data for one line to the line memory 1 are 'H', the output D1 is always 'L' at the time of inputting the clock, the inverse of WE, and thereby the output Q1 also is always 'L', so that the output QC of the 2nd FF 2e is still held at 'H' even if the writing of the one line data in the memory 1 has been completed. When the input data to the memory 1 are not all 'H', the output QC of the 2nd FF 2e is turned to 'L'. Namely, when even one of the input data is 'L', the FF 2e latches the 'L'. When the output QC of the FF 2e is used as a flag for detecting all 'H', whether data to be read out are all 'H' or not can be detected at the time of reading out the data written in the memory 1.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory circuit device used for image data processing, etc., and is intended to improve the efficiency of data reading.

[Conventional technology]

FIG. 7 shows a block configuration diagram showing a conventional memory circuit. In the figure, D0 to Dn are data inputs to memory 1;
WE is a write enable input to the memory, Addr is an address input to the memory, and Q0 to Q7 are data outputs from the memory.

In image data processing, etc., one line of image data is treated as one unit and processed, so when a memory is used for image data processing, it is used as a line memory in which image data for each line is written and read.

Here, FIG. 8 shows a conceptual diagram when writing and reading one line of image data into the memory.

This example shows a case where part of the image data for one line is written to the memory and then read.

(1) Write operation By passing a document or the like through an optical reading device, the white and black of the document are converted into digital electrical signals of white=“L” and black=“H”. One line of image data converted into digital electrical signals is written a number of times corresponding to the bit configuration of the memory.

In this example, one line is 24 bits and the memory is 8 bits, so when writing one line, there are a total of 3 bits.
need to be written twice. By repeating the write operation a required number of times in this way, 1947 worth of image data is written into the line memory 1.

(2) Read operation When reading partially written image data, for example, when the 1-line 24-bit memory is configured with 8 bits, 1
It is necessary to perform a total of three read operations to read data for a line. By repeating the read operation a required number of times in this manner, one line of image data is read from the line memory 1.

[Problem to be solved by the invention]

A conventional memory circuit device is configured as described above.
Image data is written to and read from the line memory through the above operations, but normally one line of this image data is several thousand bits, and the amount of data is enormous.

Therefore, when writing and reading this image data to memory, it is necessary to repeat the write and read operations hundreds of times, and it takes a very long time just to read and write one line of image data to and from memory. It is said that Therefore, the time for writing and reading data to the memory occupies a very large proportion of the data processing time for the entire system.

This invention was made in view of the above-mentioned problems, and is a memory that can improve the efficiency of reading data from memory and shorten the data processing time for the entire system. The purpose is to obtain a circuit device.

[Means to solve the problem]

The memory circuit device according to the present invention has 154
A circuit is provided around the memory to set a flag when all data for 7 minutes are all "H" or all "L".

[Effect]

In this invention, a circuit is provided around the memory to detect whether all data for one line written in the line memory are all 1H" or all "L", and without reading all data for one line, Since it is detected that the data is all "H" or all "L", there is no need to read out the image data from the line memory in this case.
It is possible to improve the efficiency of reading data from the memory.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail based on the drawings.

FIG. 1 is a principle block diagram of a memory circuit device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a specific example thereof. In the figure, 1 is a memory, and 2 is a NAND circuit 2a.
, OR circuit 2b, first flip-flop 2 C+second
flip-flop 2e, third flip-flop 2d
, a fourth flip-flop 2f.

Next, the operation of this circuit will be explained based on the timing diagrams of FIGS. 3 to 6.

In this timing diagram, one line of data is 24 bits,
This is the case where the data on the left side of one line is allocated to the MSB (Dt) of memory 1 in an 8-bit memory configuration.

(1) First, a case will be described in which it is detected that one line of data is all "H".

This is the output of an n-input NAND circuit 2a (in the example, n = 8 manual inputs) which inputs data to the line memory.

is the data input of the first flip-flop 2C, and is outputted to the output Q by the clock WE. This Q
, is the clock of the second flip-flop 2e.

As shown in FIG. 3, when the input data to the line memory 1 is all "H" for one line, D is always "L" when the lower clock W is input, and therefore Q is also always "L". '', the output QC of the second flip-flop 2e remains at "H" even after writing of one line of data to the line memory 1 is completed.

Next, as shown in FIG. 4, if the input data to line memory 1 is not all "H", DI may become "H" when clock W1 is input, and therefore Q also becomes "H".
”. When Ql becomes “H”, the output QC of the second flip-flop 2e changes to “L”. In other words, in the second flip-flop 2e, if there is even one “L” in the input data, the output QC of the second flip-flop 2e changes to “L”. This "L" will be latched.

The output QC of this second flip-flop 2e is all “
By setting the flag for detecting “H”, line memory 1
By looking at this flag when reading the data written to the
However, I know whether it is true or not.

(2) Next, a case will be described in which it is detected that 1547 minutes of data are all "L".

n-input OR circuit 2 that inputs data to line memory 1
The output Dt of the transistor b (in the example, n=8 human power) is the data input of the third flip-flop 2d, and is outputted to the output Q2 by the crofter WE.

This Q: serves as a clock for the fourth flip-flop 2f.

As shown in FIG. 5, when the input data to line memory 1 is 1 line all °L', Dt is always "L" when clock WE is input, and therefore Q is also always "L". Therefore, the output QC of the fourth flip-flop 2f is “Ho” even if one line of data to the line memory 1 is completed.
It remains as it is.

Next, as shown in FIG. 6, when the input data to the line memory I is not all 1L, Dt may become "H" when the clock W1 is input, and therefore Q! becomes "H".
Become Q! By becoming "Ho", the output QC of the fourth flip-flop 2r changes to @L. In other words, if there is even one "H" in the input data, the fourth flip-flop 2f launches that "H".

The output QC of this fourth flip-flop 2f is all 1
By setting the flag for “L” detection, line memory 1
When reading data that has been written to , by looking at this flag, it can be determined whether the data to be read is all "L" or not.

As explained above, by providing the detection circuit 2 around the memory that detects whether the input data to the line memory 1 is all "Ho" or "all 1L", it is possible to write data to the line memory 1 and read certain data. When processing that data, it is possible to immediately start data processing when all "H" or all "L" are detected by the above two flags. Therefore, the data is all “H”
o or all "L", it is no longer necessary to read all the data for two lines by repeating the read operation hundreds of times as in the past, and the above flag makes all "H".
Alternatively, the time it takes to detect all "1L" becomes the lead time. Therefore, the lead time when all "H" or all "L" is detected can be greatly shortened, and the data processing when viewed as a whole system. It can save time.

In the above embodiment, when inputting data into the line memory l, it is checked whether the input data is all "H" or all "L", the result is held, and the result is viewed when reading data. Accordingly, a detection circuit 2 for detecting whether the data to be read now is all “H” or all “L” is formed by a plurality of flip-flops 2C, 2.
d, 2e+2f, a NAND circuit 2a, and an OR circuit 2b, the circuit configuration of the present invention is not limited to this, but may be a circuit that performs the above operation, that is, when data is all 1H" or all "L" at the time of data input. The same effect as described above can be obtained as long as it is possible to determine and store whether or not there is one, and to detect the determination signal at the time of reading.

〔Effect of the invention〕

As described above, according to the memory circuit device according to the present invention,
Since a detection circuit is installed around the line memory to detect whether all 1547 minutes of data written to the line memory are all "H" or all "L", 1547 minutes of data can be read without reading all the data of one line. is all 'H''
Or, it can detect that all the lines are "L". In this case, there is no need to read data from the line memory, and the data read time can be shortened. As a result,
This has the effect of reducing data processing time in terms of the entire system.

[Brief explanation of drawings]

FIG. 1 is a principle configuration diagram of the memory circuit device of the present invention, and FIG.
The figure is a block diagram of a memory circuit device according to an embodiment of the present invention, and FIGS. 3 to 6 are timing diagrams for explaining the operation of FIG. 2. FIG. 7 is a block diagram showing a conventional memory circuit device, and FIG. 8 is a conceptual diagram when reading and writing image data to a line memory in the conventional memory circuit device. In the figure, 1 is a memory and 2 is a detection circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a memory circuit device used for image data processing, etc., all data of the line written to the memory is all “H”.
Alternatively, a memory circuit device characterized in that a detection circuit for detecting that all "L" states is provided around the memory.