JPS5960573A - Pattern inspecting device - Google Patents
Pattern inspecting deviceInfo
- Publication number
- JPS5960573A JPS5960573A JP57169509A JP16950982A JPS5960573A JP S5960573 A JPS5960573 A JP S5960573A JP 57169509 A JP57169509 A JP 57169509A JP 16950982 A JP16950982 A JP 16950982A JP S5960573 A JPS5960573 A JP S5960573A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- points
- logic
- resolution
- emphasized
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明はパターン検査装］は、特に微小欠陥を見逃すこ
となくパターンの分解能を落として高速でパターンの欠
陥を検査できるようにしたパターン検査装置。Detailed Description of the Invention (1) Technical Field of the Invention The present invention relates to a pattern inspection device which is capable of inspecting pattern defects at high speed by lowering the resolution of the pattern without missing particularly minute defects. .
（２）従来技術の問題点
一般に、プリント板上に形成さびたパターンの欠陥を高
分解能で行うパターン検査方法が採用さｎている。(2) Problems with the Prior Art In general, a pattern inspection method is employed in which defects in a rusty pattern formed on a printed board are detected with high resolution.
しかし、従来技術では微小欠陥全検出するためには分解
能を高くする心安があり欠陥検出に時間がかかるという
問題点があった。この場合高分解能を維持しつつ高速で
検査するにｒま、電気的並びに機械的な制約を受けて、
実現不可能である。However, in the conventional technology, it is necessary to increase the resolution in order to detect all minute defects, and there is a problem in that it takes time to detect defects. In this case, due to electrical and mechanical constraints, it is difficult to perform high-speed inspection while maintaining high resolution.
It is not possible.
（３）発明の目的
本発明の目的は５分解能を落としても微小欠陥部分を見
逃すことなく、パターン検査を高速度で行うことにある
。(3) Purpose of the Invention The purpose of the present invention is to perform pattern inspection at high speed without overlooking minute defects even when the resolution is reduced.
（４）発明の構成
本発明によｎば、微小分解化によりパターンデータを入
力させて複数個の点から成るデジタル化を行い、複数個
の点のうち一部の点ヲマとめて一点にすると共に該一部
の点の周囲の点がパターン内部ならばパターン欠けを強
調し、パターン外部ならばパターン残りを強調し、パタ
ーン境界部ならばいす扛ヲも強調せずに低分解能の出力
を得るようにしたことを特徴とするパターン検査装置が
提供さｎる。(4) Structure of the Invention According to the present invention, pattern data is input through micro-decomposition and digitized into a plurality of points, and some of the plurality of points are combined into one point. At the same time, if the points around the part of the point are inside the pattern, the missing part of the pattern is emphasized, if it is outside the pattern, the remaining part of the pattern is emphasized, and if it is at the boundary of the pattern, the output is obtained at low resolution without emphasizing the part. There is provided a pattern inspection device characterized by the following.
（５）発明の実施例
以下１本発明を実９施例により添付図面を参照して説明
する。(5) Embodiments of the Invention The present invention will be explained below by way of a 9th embodiment with reference to the accompanying drawings.
本発明の対象であるパターンデータは、先ず１０μｍ分
解能で一次メモＩＪ Ｍに入力さ扛、４き込まれる（第
１図）。１から１６までの点はパターン部金論哩「１」
、非パターン部を論理「０」としシフトレジスタ（図示
省略）で第１ピントカウント回路１０．アンドゲート１
５、オアゲート１６に接かにさイｔている。The pattern data that is the object of the present invention is first input into the primary memory IJM at a resolution of 10 μm and written into the primary memory (FIG. 1). Points from 1 to 16 are pattern part gold theory "1"
, the non-pattern part is set to logic "0" and a shift register (not shown) is used in the first focus count circuit 10. and gate 1
5. It's close to ORGATE 16.
メモ＋）Ｍの領域ａ内の４点１，２，３．４をまとめて
アンドゲート１５．オアゲート１６で１点にまるめる。Memo +) Put together the four points 1, 2, 3.4 in area a of M and use AND gate 15. Or gate 16 rounds it to 1 point.
この際に、ａの周囲の点５から１６址での論理「１」の
点の数をカウント回路１０で計測する（第２図）。カウ
ント回路１０の出力ＳＵＭはｑＡ１比較回路１１と＠３
Ｊ２比較回路１２へ供給される。ＳＵＭ≧８ならば、即
ち全体のＷ以上ならばパターン内部としａ内の点すべて
が論理「１」のとき第１比較回路１１からは論理「１」
が出力さｎてアンドゲート１７へ入力さｎる。かつ、ア
ンドゲート１５ ＶＣ入力さ０たａ内の点がすべて論理
「１」ならば、論理「１」がアンドゲート１７へ入力さ
ｎる。At this time, the number of logic "1" points at points 5 to 16 around a is counted by the counting circuit 10 (FIG. 2). The output SUM of the count circuit 10 is the qA1 comparison circuit 11 and @3
The signal is supplied to the J2 comparison circuit 12. If SUM≧8, that is, if it is greater than or equal to the total W, then it is considered to be inside the pattern, and when all the points in a are logic “1”, the first comparison circuit 11 outputs logic “1”.
is output and input to the AND gate 17. And if all the points in the AND gate 15 VC input a are logic "1", a logic "1" is input to the AND gate 17.
ＳＵＭ≦４の場合、即ち全体のμ以下ならばノくターン
外部としａ内の点がいずｎか「１」であｎば、第２比較
回路１２からは論理「１」が出力さしアンドゲート１８
へ入力さ扛る。If SUM≦4, that is, if it is less than the total μ, it is assumed that it is outside the turn. gate 18
Entered into.
その他の場合、ａ内の４点が論理［１］の数を第２ビｙ
）カウント回路１９で計１ｔｔｌｒ ｔ、て第３比較回
路２４へ入力させ、論理「１」の′＆ｉＩＮが２より犬
ならば論ｆ里「１」を１ならば論理「０」をオアゲート
２６へ入力する。またＩＮ＝２のときは第３比較回路２
４から１４ｉδ理「１」を出力させると共に、アンドゲ
ート２０，２１．２２とオアゲート２３により論理「１
」の組合わせ６通りのうち各々３通りずつ論理「１」と
「０」に対応させて出力する。In other cases, the 4 points in a set the number of logical [1] to the second bit y
) The count circuit 19 inputs a total of 1 ttlr t to the third comparison circuit 24, and if '& iIN of logic "1" is greater than 2, logic "1" is input, and if it is 1, logic "0" is input to OR gate 26. input. Also, when IN=2, the third comparison circuit 2
4 to 14iδ logic "1" is output, and AND gates 20, 21, 22 and OR gate 23 output logic "1".
Out of the six combinations of ``, three combinations are output in correspondence with logical ``1'' and ``0''.
最後に３つのアントゲ−）１７．１８及び２７の出力を
オアゲート２８へ入力させて２０μｍ分）う〒能出力を
得る。Finally, the outputs of the three analogues (17, 18, and 27) are input to the OR gate 28 to obtain a power output for 20 μm.
（６）発明の効果
上記の通り１本発明によｎば微小欠陥全見逃すことなく
、１０μｍ分解能入力から２０μｍ分解能出力を得るこ
とができるので、高速でノくターン検査を行うことがで
きる。(6) Effects of the Invention As described above, according to the present invention, it is possible to obtain a 20 μm resolution output from a 10 μm resolution input without overlooking any minute defects, so that high-speed knock-turn inspection can be performed.
第１図は本発明の対象であるノくターンデータが書き込
まｔた一次メモリのね成因、第２図は本発明装（１イの
４１１（成因である。
１０・・・第１ビツトカウント回路、１１・・・ｉｆＧ
１比較回路、１２・・・第２比較回路、１３・・・オ
アゲート、１４・−イ７バータ、１５・・・アンドゲー
ト、１６・・・オアゲート、１７．１８・・・アンドゲ
ート、１９・・・第２ビツトカウント回路、２０．２１
’、２２・・・アットゲート、２３・・・オアゲート、
２４・・・第３比較回路、２５・・・アンドゲート、２
６・・・オアゲート。
２７・・・アンドゲート、２８・・・オアゲート。Fig. 1 shows the cause of the primary memory in which the turn data, which is the subject of the present invention, is written, and Fig. 2 shows the cause of the device of the present invention (411 of 1). 10... 1st bit count circuit , 11...ifG
1 comparison circuit, 12... Second comparison circuit, 13... OR gate, 14...-i7verter, 15... AND gate, 16... OR gate, 17.18... AND gate, 19. ...Second bit count circuit, 20.21
', 22...at gate, 23...or gate,
24... Third comparison circuit, 25... AND gate, 2
6...or gate. 27...and gate, 28...or gate.
Claims (1)
点から成るデジタル化を行い、複数個の点のうち一部の
点をまとめて一点にすると共に該一部の点の周囲の点が
パターン内部ならばパターン欠けを強調し、パターン外
部ならばパターン残りを強調し、パターン境界部ならば
いずｎをも強調せずに低分解能の出力を得るようにした
ことを特徴とするパターン検査装置。By inputting pattern data with minute resolution and digitizing multiple points, some of the multiple points are combined into a single point, and if the surrounding points of some of the points are inside the pattern, A pattern inspection device characterized in that a pattern defect is emphasized if it is outside the pattern, the remaining pattern is emphasized if it is outside the pattern, and a low-resolution output is obtained without emphasizing any n if it is a pattern boundary.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57169509A JPS5960573A (en) | 1982-09-30 | 1982-09-30 | Pattern inspecting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57169509A JPS5960573A (en) | 1982-09-30 | 1982-09-30 | Pattern inspecting device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5960573A true JPS5960573A (en) | 1984-04-06 |
Family
ID=15887826
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57169509A Pending JPS5960573A (en) | 1982-09-30 | 1982-09-30 | Pattern inspecting device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5960573A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5925119A (en) * | 1997-03-28 | 1999-07-20 | Quantum Corporation | Computer architecture for automated storage library |
-
1982
- 1982-09-30 JP JP57169509A patent/JPS5960573A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5925119A (en) * | 1997-03-28 | 1999-07-20 | Quantum Corporation | Computer architecture for automated storage library |
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