JPH03190278A - Offset type mis transistor device - Google Patents

Abstract

PURPOSE:To obtain an MIS transistor with high withstand voltage having stable electrical characteristics by forming a gate electrode symmetrically at both sides for a source region. CONSTITUTION:An island-shaped thick-film selective oxide film 12 is formed at a specified surface part of a substrate 11 and source/drain regions 14 and 13 surrounded by this selective oxide film 12 are formed. Also, an offset region 15 which joins with a curved part 13a of the drain region 13 and with a lower concentration of an impurity which is of the same conductive type as that of the drain region 13 than the drain region 13 is formed at the lower side of the selective oxide film 12. Then, a gate electrode 17 which is symmetrical to the source region 14 left and right is formed the substrate 11 through a gate insulation film 16 and the selective oxide film 12, thus preventing deterioration of characteristic due to dispersion of production of gate length and overlapping length and obtaining an offset-type MIS transistor device with stable characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high voltage offset type MIS transistor device.

[Conventional technology]

Conventionally, this type of MIS transistor device was developed in
No. 1-171165".

The Mis transistor device will be described below with reference to FIG. Incidentally, FIG. 4 shows a sectional view of the device.

That is, in the drawings, ① is a semiconductor substrate, and on a predetermined portion of this substrate 1, a selective oxide film 2 of a certain thickness is formed in the form of an island, and a drain region 3 is surrounded by this selective oxide film 2.
and a source region 4 are formed. Further, below the selective oxide film 2, an offset region 5 is formed which is in contact with the curved portion 3a of the drain region 3 and has a lower concentration of impurities of the same conductivity type as the drain region 3.

Further, 6 is a thin gate insulating film formed between the source and drain regions 4.3, and a gate electrode 7 made of polysilicon is formed on this gate insulating film 6 and on the adjacent selective oxide film 2. is formed.

Therefore, in such a transistor device, by applying a voltage to the gate electrode 7, a channel region is formed under the gate insulating film 6, and current flows from the drain region 3 through the offset region 5 and the channel region to the source region 4. It was like that.

[Problem to be solved by the invention]

However, in the above-described transistor device, the source/drain regions 4.3 are formed by impurity doping using the selective oxide film 2 and the gate electrode 7 as a mask. Depending on the alignment accuracy, the gate length p1 and the overlap length l! between the offset region 5 and the gate electrode 7 are determined. is determined. Therefore, there is a problem in that the channel resistance and the offset resistance change due to variations in mask alignment accuracy, which deteriorates the characteristics of the transistor.

In view of the above-mentioned problems, an object of the present invention is to prevent characteristic deterioration due to manufacturing variations in gate length and overlap length, and to provide an offset-type MIS transistor device with stable characteristics.

[Means to solve the problem]

In order to achieve the above-mentioned object, the present invention includes a thick selective oxide film formed on a predetermined portion of a semiconductor substrate, and a source formed on a portion of the surface portion of the semiconductor substrate surrounded by the selective oxide film.・A drain region and an off-site Sff region that is located below the selective oxide film and is bonded to the curved part of the drain region, and has a lower concentration of impurities of the same conductivity type as the drain region than the drain region. , comprising gate electrodes formed symmetrically on both sides of the source region between the source region and the selective oxide film on the semiconductor substrate via a gate insulating film and a portion of the selective oxide film. This is what I did.

Further, a thick selective oxide film formed on a predetermined portion of the semiconductor substrate, a source/drain region formed in a portion of the surface portion of the semiconductor substrate surrounded by the selective oxide film, and the selective oxide film An offset region is formed on the lower side of the drain region and is connected to the curved part of the drain region, and is formed with a lower concentration of impurity of the same conductivity type as the drain region, and the drain region covers the entire circumference. a gate electrode surrounded by and formed between the source region on the semiconductor substrate and the selective oxide film so as to surround the entire circumference of the source region via a gate insulating film and a portion of the selective oxide film; It is equipped with the following.

[For production]

In the present invention, since the gate electrodes are formed symmetrically on both sides of the source region, changes in the gate length and overlapping length caused by mask misalignment during gate electrode formation are canceled out.

〔Example〕

An embodiment of the apparatus of the present invention will be described based on FIGS. 1 and 2. Note that FIG. 1 shows a sectional view of the device, and FIG. 2 shows a plan view of the device.

That is, in the drawing, reference numeral 11 denotes a semiconductor substrate, and on a predetermined surface portion of this substrate 11, an island-shaped thick selective oxide film 12 is formed, and source/drain regions surrounded by this selective oxide film 12 are formed. 1413 is formed. Further, on the lower side of the selective oxide film 12, an offset region 15 is formed which is in contact with the curved portion 13a of the drain region 13 and has a lower concentration of impurities having the same conductivity type as the drain region 13. There is. Further, the source region 14 and
Between the selective oxide films 12 adjacent on both sides, a gate electrode 17 having a bilaterally symmetrical shape with respect to the source region 14 is formed on the substrate 11 via the gate insulating film 16 and the selective oxide film 12. has been done.

Further, FIG. 3 is a plan view of another device, and according to this, the gate electrode 17i17 surrounds the entire circumference of the source region 14, and the drain region 13 surrounded by the offset region 15 connects the gate electrode 17. It is formed to surround.

Thus, in this device, since the gate electrode 17 is formed symmetrically on both sides of the source region 14, the gate length i due to mask misalignment during patterning of the gate electrode 17 and the overlap with the offset region 15 are reduced. The changes in length 12 cancel each other out. Therefore, changes in channel resistance and offset resistance cancel each other out.

〔Effect of the invention〕

As explained above, according to the present invention, since the gate electrodes are formed symmetrically on both sides of the source region, channel resistance and offset due to changes in gate length and overlapping length caused by mask misalignment during gate electrode formation are reduced. High withstand voltage M with stable electrical characteristics as resistance changes cancel each other out
The above-mentioned problems can be solved by the effect that an IS transistor can be obtained.

[Brief explanation of drawings]

1 to 3 show an embodiment of the device of the present invention, FIG. 1 is a sectional view of the device, FIG. 2 is a plan view of the device, and FIG. 3 is a plan view of another device. FIG. 4 is a sectional view of a conventional device. 11... Semiconductor substrate, 12... Selective oxide film, 13.
...Drain region, 13a...Curved portion, 14...
Source area, X5...offset) STJ area, 16.
...Gate insulating film, 17...Gate electrode, l,...
Gate length, 12... overlap length.

Claims (2)

[Claims] (1) a thick selective oxide film formed on a predetermined portion of the semiconductor substrate; a source/drain region formed in a portion of the surface portion of the semiconductor substrate surrounded by the selective oxide film; an offset region on the lower side of the film that is bonded to the curved portion of the drain region and has a lower concentration of impurities of the same conductivity type as the drain region; and the source region on the semiconductor substrate. An offset type MI characterized by comprising a gate insulating film and a gate electrode formed symmetrically on both sides of the source region through a portion of the selective oxide film between the selective oxide film and the selective oxide film.
S transistor device. (2) a thick selective oxide film formed on a predetermined portion of the semiconductor substrate; a source/drain region formed in a portion of the surface portion of the semiconductor substrate surrounded by the selective oxide film; An offset region is located on the lower side of the film and is bonded to the curved part of the drain region, and is formed with a lower concentration of impurities of the same conductivity type as the drain region, and the entire circumference is formed by the drain region. and a gate formed between the source region on the semiconductor substrate and the selective oxide film so as to surround the entire circumference of the source region via a gate insulating film and a portion of the selective oxide film. An offset type MIS transistor device characterized by comprising an electrode.