JPH0357278A - Mis type field-effect transistor - Google Patents

Abstract

PURPOSE:To enhance breakdown strength of a drain, to perform double diffusion in a source and to realize a short channel and a low ON resistance by utilizing a LOCOS oxidation. CONSTITUTION:A separate region is patterned and an impurity is implanted with an Si3N4 mask 10. Then, an isolation region 8 and a low concentration drain region 3 are formed by selective oxidation. Thereafter, a gate electrode 5 is formed of polysilicon, a high concentration impurity region 9 to become a channel is implanted into the electrode 5 in a self-alignment manner, and thermally diffused. Then, a source 2 and a high concentration drain region 4 are formed by implanting the impurity. An interlayer insulating film is deposited, a connecting hole is formed, and metal wirings are provided to complete it. With this structure, in a MIS type FET in which breakdown strength of the drain 3 only is enhanced, an increase in a driving force due to reductions in the area of the source region 2 and decreases in ON resistance and effective channel length can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high voltage power IC that coexists with logic circuits and small signal circuits.

[Summary of the invention]

This invention is an MIS type field effect transistor that uses LOGOS oxidation to increase the withstand voltage of the drain, and uses double diffusion for the source to shorten the channel.

[Conventional technology]

As the degree of integration increases, it has become possible to configure not only the logic processing section but also the output buffer with a monolithic IC. LOG usually used for isolation between elements
OS (Local Oxidation of
High breakdown voltage transistors using silicon can achieve the above application [C] with a small number of mask configurations.

FIG. 2 shows a cross-sectional view of a high voltage MIS field effect transistor using conventional LOGOS oxidation.

Isolation insulating films 8 formed by LOGOS oxidation are placed on both sides of the gate electrode 5 and introduced into the isolation insulators 8 in a self-aligned manner, forming low concentration impurity regions in the source 2 and drain regions 3. Due to the existence of this low impurity concentration drain region 3,
It has become possible to suppress impact ionization of channel carriers due to high electric fields, and to increase the surface breakdown voltage at the gate edge by using a thick isolation insulating film. However, this structure has the disadvantage that even the source 2, which is not required to have a high breakdown voltage, has a low impurity concentration, which increases the on-resistance. On the other hand, the effective channel length is determined by the length LG of the active region.

JIKSALG is L. The length of the isolation insulating film 8 was required to be four to five times longer because of the birth beak of OCOS oxidation and the deep junction depth of the source and drain in this structure, which tends to cause punch-through. Incidentally, in the case of separation insulation M1 .mu.m, LG-4 to 5 .mu.m was required. In order to improve these drawbacks, an MIS type field transistor has been devised in which a shallow, highly concentrated impurity region is formed only on the source 2 side in a self-aligned manner with the gate electrode, as shown in FIG. In this structure, there is no low impurity region on the source side, and the on-resistance is small. However, even in this case, a new problem arises in that the effective channel length changes due to misalignment between the LOGOS photomask that shapes the train and the gate 71m photomask.
In mass production, LG-3 to 4 μm is required, and it was difficult to shorten it.

[Problem to be solved by the invention]

The present invention provides a structure and a method for manufacturing the same, which simultaneously achieves a reduction in source resistance and an effective channel length while maintaining a high breakdown voltage of the drain using an isolation insulating film.

[Means to solve problems]

The present invention utilizes LOCOS oxidation to increase the withstand voltage of the drain, and uses double diffusion to achieve a short channel and low on-resistance.

[Effect]

Since the channel length is determined by the high concentration impurity region of the same conductivity type as the substrate introduced on the source side, it is possible to avoid variations in the effective channel length due to misalignment between the gate electrode mask and the LOGOS mask. Therefore, the channel can be shortened and the channel conductance can be increased. Furthermore, since a low concentration impurity region does not enter the source region, the on-resistance can be reduced by about half.

〔Example〕

FIG. 1 is a sectional view of an embodiment of a high breakdown voltage MIS type field effect transistor of the present invention.

Highly integrated logic MOS with low voltage drive of 5V or less
In an IC in which a transistor and a high-voltage drive output MOS transistor are arranged on the same substrate, an isolation insulating film and a low concentration impurity region are introduced under it in a self-aligned manner as a manufacturing process to form both transistors relatively easily. A method is being adopted to do so.

On the other hand, in output circuits such as final-stage level shifters, CMOS inverters, oven drains, and the like, the source is almost always used at the same potential as the substrate or well. Therefore, there is no need to increase the withstand voltage of the source except when the source is connected in series or used as a transfer gate.

If a low impurity region like the drain side is not used on the source side, the size of the transistor can be reduced and the on-resistance can be reduced to about 1/2. FIG. 1 is a cross-sectional view of a MIS type field effect transistor for this purpose and with almost no variation in effective channel length due to mask misalignment. The drain has a structure in which impact ionization is difficult to occur due to the low concentration impurity region 3 using the isolation insulating film 8. Furthermore, the low concentration impurity region 3 and the gate electrode 5
Since the thickness of the insulating film gradually increases at the edge of the gate, surface breakdown is less likely to occur when the gate is turned off. On the source side, a high-concentration impurity region 7 serving as a channel and a source region 2 are formed by a double diffusion technique matching the pattern of the gate electrode 5. In this tR structure, the effective channel length LG is due to the double diffusion impurity source and its diffusion.
controlled.

The surface of the substrate 1 between the high degree impurity region 7 and the low concentration drain region 3 is controlled by the gate electrode 5, and when turned on, it is in a strong inversion state, hardly changing the effective channel length LG, and the gate electrode 5 5, it is possible to realize a high voltage MOS transistor which is not affected by the alignment of the isolation insulating film. Furthermore, a very short channel can be formed with an effective channel length of about 1 μm.

An example of the manufacturing process of the MIS type field effect transistor according to the present invention shown in FIG. 1 is shown in FIGS. 4(a) to 4(d). In FIG. 4(a), a region to be an isolation region is patterned using silicon nitride 10, and impurities are introduced by implantation. In FIG. 4(b), selective oxidation is performed using silicon nitride 10 as a mask to form an isolation region 8 and a low concentration drain region 3. Thereafter, a gate electrode 5 is formed by depositing polysilicon, and then a high concentration drain region 3, which will become a channel, is formed. Impurity region 7 is introduced into gate electrode 5 in a self-aligned manner and thermally diffused. In FIG. 4(C), the source 2 and heavily doped drain region 4 are formed by implantation. In FIG. 4(d), an interlayer insulating film is deposited, contact holes are opened, and metal wiring is patterned to complete the process.

〔Effect of the invention〕

In an MIS type field effect transistor in which only the drain has a high breakdown voltage, it is possible to reduce the area of the source region, reduce the ON resistance, and increase the driving capability by reducing the effective channel length.

[Brief explanation of drawings]

FIG. 1 is a sectional view of an MIS type field effect transistor according to the present invention, FIGS. 2 and 3 are sectional views of conventional MIS type field effect transistors, and FIGS. 4(a) to 4(d) are sectional views of a MIS type field effect transistor according to the present invention. FIG. 3 is a cross-sectional view of the manufacturing process of the MrS type field effect transistor. 1... Semiconductor substrate 2... Source region 3... Low impurity concentration drain region 4... High impurity concentration drain region 5... Gate electrode 6... Gate insulating film 7... High concentration impurity Region 8 ・ ・ Isolation insulating film 9 ... Interlayer insulating film or higher

Claims (1)

[Claims] A highly concentrated impurity source region of a second conductivity type provided on a surface portion of a semiconductor substrate of a first conductivity type, a gate insulating film in contact with the source region, a gate electrode on the gate insulating film, and a source region from the source region. an isolation insulating film provided at intervals and thicker than the gate insulating film; a first drain region of a second conductivity type low concentration impurity introduced in a self-aligned manner under the isolation insulating film; and the first drain region. A MIS type field effect transistor comprising a second drain region of high concentration impurity in contact with the source region, and a first conductivity type impurity region having a higher concentration than the semiconductor substrate and introduced into the source region in a self-aligned manner.