JPH03188676A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase the breakdown strength and the reliability by a method wherein a laminated film comprising an Si oxide and an Si nitride is formed on a substrate in a channel region between a source region and a drain region and then thick Si oxide films are provided on both sides of the laminated film. CONSTITUTION:A source region 7, a drain region 8 comprising N type diffused layer are formed in a P type Si substrate 1 and then a laminated film formed of a thin Si oxide film 2 and an Si nitride film 3 to be a tunneling medium is formed only on the substrate 1 in the central part of the channel region held by both regions 7 and 8. Besides, thick Si oxide films 4 are formed on the parts opposite to the substrate 1 on both ends of the channel region. Next, a gate electrode comprising a polysilicon film 6 is formed on the films 3, 4. Through these procedures, the reliability upon a memory cell can be secured.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention aims to improve the reliability of a semiconductor memory device having an MNOS (metal-silicon nitride film-silicon oxide film-semiconductor) type field effect transistor structure. This invention relates to a novel structure that can be used and a method for manufacturing the same.

BACKGROUND OF THE INVENTION Conventionally, EEPROM (El
electrically Erasable and
As one of the programmable ROMs,
MNOS that performs write/erase using tunneling injection
Semiconductor memory devices with this structure are well known. This MNO
In an S-type semiconductor memory device, a high voltage of about 20 V is applied between the gate and the substrate, and charges are transferred from the semiconductor side to the trap level in the silicon nitride film at or near the interface between the silicon oxide film and the silicon nitride film. Information is stored by performing injection and storage and changing the threshold voltage of the transistor.

FIG. 4 shows an example of a cross-sectional structure of a conventional MNO8 type semiconductor memory device. 1 is a P-type silicon substrate, and 7 and 8 are N-type diffusion layers, which are called source and drain regions.

2 is a thin silicon oxide film that can be used as a tunneling medium;
3 is a silicon nitride film, and 6 is a polysilicon electrode. In the MNO3 type semiconductor memory device having the structure as shown in FIG. In order to make it easier for tunneling to occur, the number of people is kept very thin, around 20 people. Further, the thickness of the silicon nitride film 3 on the thin silicon oxide film 2 is relatively thin by 300-500 so that writing and erasing can be performed with a voltage of about 2O-25V. Therefore, in the MNO8 type semiconductor memory device as shown in FIG. 4, the gate is Ov and the drain is 2O-
When a high voltage of 25V is applied, the electric field between the gate electrode and the drain greatly affects the electric field between the drain and the substrate, and electric field concentration occurs in the channel region near the drain.
This method has disadvantages in that breakdown occurs between the drain and the substrate, and the thin silicon oxide film on that region is easily destroyed.

Therefore, in order to eliminate the above-mentioned drawbacks, conventionally, as shown in FIG. 5, the silicon oxide film at both ends of the channel region is made 300 to 500 times thicker, and the electric field is concentrated in the channel region near the drain. It is well known that the structure avoids this and improves the withstand voltage.
6265).

If such a structure is adopted, as shown in the equivalent circuit of FIG. The transistor becomes a selection transistor necessary to realize selective writing, erasing, and reading of the memory.

Problems to be Solved by the Invention However, in an MNO8 type semiconductor memory device equipped with normal transistors on both sides as shown in FIG.
Although the normal transistors on both sides have a thick silicon oxide film, they have an MNOS structure, so long-term B
When T treatment (bias applied to the gate at high temperature) is applied, the threshold voltages of normal transistors on both sides vary, making it extremely difficult to ensure the reliability of the memory cell.

In view of these problems, an object of the present invention is to improve the withstand voltage and reliability of an MNO3 type semiconductor memory device at the same time.

Means for Solving the Problems In order to achieve the above object, the present invention first provides a source region and a drain region in a semiconductor substrate of one conductivity type, and a channel region sandwiched between the source region and the drain region. A laminated film of at least two layers consisting of a thin silicon oxide film and a silicon nitride film serving as a tunneling medium is provided only in the central portion facing the semiconductor substrate, and a thick layer is provided in the portions facing the semiconductor substrate at both ends of the channel region. The device includes a silicon oxide film, and has a structure in which the stacked film and the thick silicon oxide film are covered with a gate electrode film.Secondly, the stacked film serves as a tunneling medium.
It is a three-layer laminated film consisting of a silicon oxide film, a silicon nitride film, and a second silicon oxide film.Thirdly, a tunneling medium is formed only in the portion that will become the tunneling region on the semiconductor substrate of one conductivity type. After forming a thin layered film of a silicon oxide film and a silicon nitride film, an oxidation treatment is performed to form a thick silicon oxide film on the semiconductor device other than the tunneling region and a thin silicon oxide film on the silicon nitride film. and forming an electrode layer covering a thick silicon oxide film on the semiconductor substrate and a thin silicon oxide film on the silicon nitride film.

Operation In the structure of the present invention as described above, the gate insulating films of the normal transistors on both sides of the MNOS memory transistor or the MONOS memory transistor in which a top silicon oxide film is formed on the silicon nitride film of the MNOS are made of only a silicon oxide film. Unlike the conventional laminated structure of silicon nitride film and silicon oxide film,
Even if BT processing is performed for a long time, the threshold voltages of the normal transistors on both sides do not change, making it very easy to ensure the reliability of the memory cell.

Further, according to the manufacturing method of the present invention as described above, it is possible to make the gate insulating films of the normal transistors on both sides of the memory transistor with a structure of only a silicon oxide film, thereby improving the reliability of the MNOS type semiconductor memory device. can be created.

Example Specific embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a sectional view showing another embodiment of the semiconductor memory device of the present invention.

As shown in FIGS. 1 and 2, a P-type silicon substrate 1
(Impurity concentration of about 1 x 10 l5a11-3), an N-type diffusion layer (impurity concentration of about I x 10"CIl+-3)
) source region 7. A drain region 8 is formed;
Source area 7. Very thin silicon oxide film 2 and silicon nitride film 3 serve as tunneling media only on the semiconductor substrate in the center of the channel region sandwiched between drain region 8.
or a very thin first silicon oxide film 2
A three-layer stacked film consisting of a silicon nitride film 3 and a second silicon oxide film 5 (in this example, a thin silicon oxide film 2
The thickness of the silicon nitride film 3 is 20, and the thickness of the silicon nitride film 3 is 300.
Assuming a person, the thickness of the silicon oxide film 5 on silicon nitride is 3
A thick silicon oxide film 4 (400 layers in this example) is formed on the silicon nitride film 3 and the portions facing the semiconductor substrate at both ends of the channel region. The structure is such that a gate electrode made of a polysilicon film 6 is formed to cover a thick silicon oxide film 4. In the structure of the present invention, MN
The gate insulating film of the regular transistors on both sides of an OS memory transistor or a MONOS memory transistor in which a top silicon oxide film is placed on the silicon nitride film of MNOS has a structure of only a silicon oxide film, so it is different from the conventional silicon nitride film. Unlike a stacked structure with a silicon oxide film, the threshold voltage of the normal transistors on both sides does not change even after long-term BT processing, making it extremely easy to ensure the reliability of the memory cell. Become.

Next, a specific example of a method for manufacturing a semiconductor memory device having the structure of the present invention will be described with reference to the drawings.

First, as shown in FIG. 3(A), a P-type silicon substrate 1
A very thin silicon oxide film 2 that can serve as a tunneling medium is formed thereon by a known thermal oxidation method. In this example, oxidation was performed at 800° C. in a diluted oxygen atmosphere, and the number of participants was about 20. Next, a silicon nitride film 3 is formed on the thin silicon oxide film 2 by a known vapor phase growth method. In this example, NH3/S i H2C12 = 10.750°C was obtained using a reduced pressure vapor phase growth method based on a chemical reaction between dichlorosilane (SiH2CI!2) and ammonia (NH3).
Approximately 300 people were formed under these conditions.

Next, as shown in FIG. 3B, etching is performed using a known photoetching technique so that the silicon nitride film 3 and silicon oxide film 2 remain only in predetermined portions that will become tunneling regions.

Next, as shown in FIG. 3(C), oxidation treatment is performed by a normal thermal oxidation method. At this time, since the silicon nitride film 3 has oxidation resistance, a thick silicon oxide film 4 is formed only in the portion other than the tunneling region. In this example,
The test was carried out at 900° C. in a steam atmosphere, and the thickness of the thick silicon oxide film 4 was 400. Furthermore, during this oxidation treatment, the top of the silicon nitride film 3 is also oxidized to some extent, and a silicon oxide film 5 having a thickness of about 30 mm is formed. In addition, since this process utilizes the oxidation resistance of the silicon nitride film, which is the gate insulating film of the memory, the thick silicon oxide film 4 can be formed in a self-aligned manner. It becomes possible to make the gate insulating films of normal transistors on both sides of the gate using only silicon oxide films.

Next, as shown in FIG. 3(C), a polysilicon film 6 doped with phosphorus (approximately 3 x 1020 am-') is formed.
Approximately 4,000 layers are formed on the entire surface by a known vapor phase growth method.

Next, as shown in FIG. 3(D), the polysilicon film 6-oxide silicon film 4 is etched using a known photo-etching technique so as to leave only a portion that can become a gate. After that, phosphorus was implanted by ion implantation (100 KeV).

2X10150-2) Source region7. A drain region 8 is formed. Next, a silicon oxide film 9 is deposited on the entire surface by a known vapor phase growth method, and then a source layer is formed.

In order to push in the drain and make the silicon oxide film 9 dense, heat treatment is performed at 1000° C. in a nitrogen atmosphere.

Finally, in order to provide electrodes in the source and drain regions 7 and 8, the silicon oxide film 9 is etched to form contact holes and aluminum electrodes 10 are formed.
A semiconductor memory device as shown in D) can be manufactured.

In the embodiment of the manufacturing method described above, the structure shown in FIG. 2 can be realized, but as another embodiment to realize the structure shown in FIG. 1, the following method is used.

That is, among the steps shown in FIG. 3, after the oxidation treatment shown in FIG. 3(C), the thin silicon oxide film 5 on the silicon nitride film 3 is etched by a normal etching method using a fluorine-based aqueous solution. This can be achieved by etching away and then forming a polysilicon film 6.

As is clear from the detailed description of the invention, according to the structure and manufacturing method of the present invention, both MNOS memory transistors and MONOS memory transistors in which a top silicon oxide film is formed on a silicon nitride film of MNOS can be manufactured. Since the gate insulating film of the normal transistor on the side is formed only with a silicon oxide film, it is possible to improve its breakdown voltage and at the same time reduce the variation in characteristics due to BT processing, etc., and improve its reliability. This greatly contributes to increasing the reliability of storage devices.

[Brief explanation of drawings]

1 and 2 are sectional views for explaining one embodiment of the structure of the present invention, FIG. 3 is a step-by-step sectional view for explaining one embodiment of the manufacturing method of the present invention, and FIG. 4 is a sectional view for explaining an embodiment of the structure of the present invention. and FIG. 5 is a cross-sectional view for explaining the structure of a conventional semiconductor memory device.
FIG. 6 is a diagram showing an equivalent circuit of FIG. 5. 1...P-type silicon substrate, 2...Thin silicon oxide film that can be used as a tunneling medium, 3...
...Silicon nitride film, 4...Thick silicon oxide III, 5...Thin silicon oxide film, 6...
...Polysilicon film, 7...Source region,
8...Drain region, 9...Silicon oxide film, 10...Aluminum electrode.

Claims (3)

[Claims] (1) A source region and a drain region are provided in a semiconductor substrate of one conductivity type, and a thin silicon oxide that can serve as a tunneling medium is located only in the central portion of the channel region sandwiched between the source region and the drain region, which faces the semiconductor substrate. a laminated film of at least two layers consisting of a silicon nitride film and a silicon nitride film, a thick silicon oxide film is provided at both ends of the channel region facing the semiconductor substrate, and a gate electrode is provided on the laminated film and the thick silicon oxide film. A semiconductor memory device characterized by having a structure covered with a film. (2) The semiconductor memory according to claim 1, wherein the laminated film is a three-layer laminated film consisting of a thin first silicon oxide film, a silicon nitride film, and a second silicon oxide film that can serve as a tunneling medium. Device. (3) After forming a laminated film of a thin silicon oxide film and a silicon nitride film, which can serve as a tunneling medium, only in the portion of the semiconductor substrate of one conductivity type that will become the tunneling region, an oxidation treatment is performed, and the semiconductor substrate other than the tunneling region is forming a thick silicon oxide film on the silicon oxide film and a thin silicon oxide film on the silicon nitride film, and forming an electrode layer covering the thick silicon oxide film on the semiconductor substrate and the thin silicon oxide film on the silicon nitride film. 1. A method of manufacturing a semiconductor memory device, the method comprising the step of: