JPH03185787A - Manufacture of printed wiring board - Google Patents
Manufacture of printed wiring boardInfo
- Publication number
- JPH03185787A JPH03185787A JP32476289A JP32476289A JPH03185787A JP H03185787 A JPH03185787 A JP H03185787A JP 32476289 A JP32476289 A JP 32476289A JP 32476289 A JP32476289 A JP 32476289A JP H03185787 A JPH03185787 A JP H03185787A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- plating
- thickness
- film
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000002184 metal Substances 0.000 claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 238000007747 plating Methods 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000004020 conductor Substances 0.000 claims abstract description 7
- 238000007740 vapor deposition Methods 0.000 claims description 18
- 239000000126 substance Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 10
- 239000012808 vapor phase Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 abstract description 16
- 238000000151 deposition Methods 0.000 abstract description 11
- 230000008021 deposition Effects 0.000 abstract description 5
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 238000001771 vacuum deposition Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 23
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 238000005530 etching Methods 0.000 description 9
- 229910052759 nickel Inorganic materials 0.000 description 9
- 230000005611 electricity Effects 0.000 description 5
- 239000007788 liquid Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 230000008719 thickening Effects 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- -1 polyethylene Polymers 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 239000011135 tin Substances 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 229920000742 Cotton Polymers 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- 239000004721 Polyphenylene oxide Substances 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 230000005389 magnetism Effects 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920000570 polyether Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000009774 resonance method Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、気相法により形成した回路パターンの蒸着部
分を厚膜化するプリント配線板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a printed wiring board, in which a vapor-deposited portion of a circuit pattern formed by a vapor phase method is thickened.
(従来の技術およびその課題)
プリント配線板は、コンピュータ、オーディオ機器、ビ
デオ機器、自動車電装品、電話交換器、ワードプロセッ
サ、ファクシミリ、レーザディスクブレヤー、カメラ、
電子時計など種々の用途に使用されているが、小型化、
性能向上のため高密度化した精度のよいプリント配線板
が望まれている。(Prior art and its problems) Printed wiring boards are used in computers, audio equipment, video equipment, automobile electrical equipment, telephone exchanges, word processors, facsimile machines, laser disc players, cameras,
It is used for various purposes such as electronic watches, but it has become smaller and
In order to improve performance, high-density, high-precision printed wiring boards are desired.
従来、プリント配線板は基板材料に導電性金属板を貼着
し、その上にフォトレジストを塗布又は貼付したものに
、フォトマスクを介して露光し、現像するか、又は、レ
ジストにレーザー光を照射して直描することによってパ
ターンを形成した後、エツチングにより回路を形成する
方法にて通常、作成されている。Conventionally, printed wiring boards have been made by pasting a conductive metal plate onto a substrate material, coating or pasting a photoresist on it, exposing it to light through a photomask and developing it, or exposing the resist to laser light. Usually, a pattern is formed by irradiation and direct drawing, and then a circuit is formed by etching.
しかしながら、レジストとエツチング工程とを必要とす
る、これらの方法においては、■工程が煩雑である、■
エツチング液が導電性金属板とフォトレジスト膜との界
面に侵入し侵食しやすいため、また厚い金属板をエツチ
ングするため得られる回路の精度が悪い、■エツチング
により厚い金属板が溶解され、溶解液が廃棄されるため
資源的に損失が大きい、■現像液やエツチング液の廃液
処理が必要である等の問題がある。However, these methods, which require a resist and etching process, have the following problems: (1) The process is complicated;
The etching solution easily invades and erodes the interface between the conductive metal plate and the photoresist film, and the accuracy of the circuit obtained is poor because the thick metal plate is etched. There are problems such as large losses in terms of resources as the liquid is discarded, and (2) waste liquid treatment of developer and etching liquid is required.
これらの問題を解決するため、回路パターンに対応した
透孔を有するメタルマスクを介して基材上に蒸着物質を
蒸着させて回路を形成する方法が提案されている。しか
しながら、この方法においては上記の問題は解決できる
ものの、蒸着によって形成される回路の導電部分は薄膜
であるため、導通できる電気量が少量であり、用途が大
きく限定されるという問題があった。In order to solve these problems, a method has been proposed in which a circuit is formed by depositing a deposition substance onto a base material through a metal mask having through holes corresponding to the circuit pattern. However, although this method can solve the above problem, since the conductive part of the circuit formed by vapor deposition is a thin film, the amount of electricity that can be conducted is small, and the application is greatly limited.
(課題を解決するための手段)
本発明者らは、レジストとエツチング工程とを必要とす
る方法における、前記■〜■の問題がなく、しかも、メ
タルマスクを介して蒸着により形成される回路のように
用途が大きく限定されることがない、プリント配線板の
製造方法について鋭意研究を行なった結果、蒸着により
形成された回路をメッキにより厚膜化することによって
、上記問題点がすべて解決できることを見出し本発明に
至った。(Means for Solving the Problems) The present inventors have solved the above-mentioned problems of (1) to (3) in methods requiring resist and etching steps, and moreover, a circuit formed by vapor deposition through a metal mask. As a result of intensive research into the manufacturing method of printed wiring boards, which is not severely limited in application, we have found that all of the above problems can be solved by thickening the circuit formed by vapor deposition by plating. Heading This invention has been achieved.
すなわち本発明は、回路パターンに対応した透孔を有す
るメタルマスクを介して、プリント配線板基材表面に気
相法により蒸着物質を蒸着させて、厚さ1.0X10−
”P〜10Pの導電部を有する回路を形成した後、該導
電部に導電性材料をメッキすることによって該導電部の
メッキ後の厚さがメッキ前の厚さの2倍以上となるよう
厚膜化することを特徴とするプリント配線板の製造方法
を提供するものである。That is, in the present invention, a vapor deposition substance is deposited on the surface of a printed wiring board substrate by a vapor phase method through a metal mask having through holes corresponding to a circuit pattern, to a thickness of 1.0×10−.
``After forming a circuit having a conductive part of P to 10P, plate the conductive part with a conductive material so that the thickness of the conductive part after plating is at least twice the thickness before plating. The present invention provides a method for manufacturing a printed wiring board characterized by forming it into a film.
本発明方法においては、まずメタルマスクを介してプリ
ント配線板基材表面に蒸着物質を蒸着させて回路を形成
する。In the method of the present invention, a circuit is first formed by depositing a vapor deposition substance on the surface of a printed wiring board substrate through a metal mask.
上記基材としては、ポリイミド、ポリエーテルポリイミ
ド、ポリアミドポリイミド、ポリエチレンテレツクレー
トなどの有機材料、セラミックス、シリコンなどが挙げ
られる。Examples of the base material include organic materials such as polyimide, polyether polyimide, polyamide polyimide, and polyethylene terecrate, ceramics, and silicon.
この基材表面にメタルマスクを介して蒸着させる蒸着物
質としては、金属や金属酸化物などが挙げられ、具体例
としては、銅、ニッケル、銀、金、クロム、錫、アルミ
ニウムおよびこれらの金属の合金、酸化錫などが挙げら
れる。これらの蒸着物質は、真空蒸着、スパッタリング
、イオンブレーティング、電子サイクロトロン共鳴等を
用いて、膜厚が1.0X10−”F〜10P、好ましく
は0.1〜3戸程度となるよう蒸着を行なう、膜厚が1
.0xlO−”Pより薄い場合には、メッキされない場
所が残存するなどバラツキによる蒸着膜の不良率が増大
するため好ましくない。Examples of the vapor deposition substance to be vapor-deposited on the surface of this base material through a metal mask include metals and metal oxides, and specific examples include copper, nickel, silver, gold, chromium, tin, aluminum, and the like. Examples include alloys and tin oxide. These evaporation substances are deposited using vacuum evaporation, sputtering, ion blating, electron cyclotron resonance, etc., so that the film thickness is 1.0×10-”F to 10P, preferably about 0.1 to 3 mm. , film thickness is 1
.. If it is thinner than 0xlO-''P, it is not preferable because the defect rate of the deposited film increases due to variations such as unplated areas remaining.
一方、膜厚がIOFを超える場合、これだけの膜厚をつ
けるための蒸着時間が多くかかり実用的でなくなる。ま
た蒸着を行なう際、2種以上の蒸着物質を同時に蒸着し
て2種以上の金属の混合膜としてもよく、また蒸着物質
を蒸着させた後、さらに別の蒸着物質を蒸着させて複層
の蒸着膜を形成してちまい。On the other hand, if the film thickness exceeds the IOF, it would take a long time to deposit the film to this thickness, making it impractical. In addition, when performing vapor deposition, two or more types of vapor deposition substances may be simultaneously vapor-deposited to form a mixed film of two or more metals, or after vapor-depositing one vapor-deposition substance, another vapor-deposition substance may be vapor-deposited to form a multilayer film. A vapor deposited film will be formed.
本発明方法におけるメタルマスクは、目的とする回路パ
ターンの形状に対応して透孔を有する金属板であり、蒸
着時、透孔から蒸着物質が基材表面に蒸着され、透孔以
外の部分では遮へいされて金属が基材表面に蒸着されな
いため透孔の形状に応じた回路パターンを有する蒸着膜
を形成できる。メタルマスクの材質としては、鋼、ニッ
ケル、銀、金、アルミニウムおよびこれらの金属の合金
などが挙げられ、これらのうちニッケルが磁性を有して
いるためプリント配線板基材の裏面から磁石などの磁力
を作用させて基材表面に密着させることができ、かつ錆
びにくい点から好ましい、メタルマスクの厚さは約10
pm〜約500P程度であることが好ましく、さらには
30〜200Pの範囲であることがより好ましい。メタ
ルマスクは金属板をレーザーによって直描する方法、ス
クリーン印刷やパターンフィルムを介してのレジストの
硬化、現像によって金属板上に回路パターンを形成し、
薬液にてエツチングする方法、ベースフィルム上に回路
パターンを有するレジスト層を形成し、凹部をメッキす
ることによって回路を形成した後、残存レジスト層およ
びベースフィルムを除去するアディティブ法による方法
などによって作成することができる。The metal mask used in the method of the present invention is a metal plate having through holes corresponding to the shape of the intended circuit pattern, and during vapor deposition, the deposition substance is deposited on the surface of the base material through the through holes, and the material is deposited on the surface of the base material through the through holes. Since metal is not deposited on the surface of the base material due to shielding, a deposited film having a circuit pattern corresponding to the shape of the through hole can be formed. Materials for metal masks include steel, nickel, silver, gold, aluminum, and alloys of these metals. Among these, nickel has magnetism, so it cannot be used with a magnet or the like from the back side of the printed wiring board substrate. The thickness of the metal mask is preferably about 10 mm because it can be brought into close contact with the surface of the base material by applying magnetic force and is resistant to rust.
The range is preferably from pm to about 500P, and more preferably from 30 to 200P. Metal masks are made by forming a circuit pattern on a metal plate by directly drawing on the metal plate with a laser, curing resist through screen printing or pattern film, and developing it.
It is created by etching with a chemical solution, or by an additive method in which a resist layer with a circuit pattern is formed on a base film, a circuit is formed by plating the recesses, and then the remaining resist layer and base film are removed. be able to.
本発明方法においては、蒸着によって回路の導電部を形
成した後、この導電部に導電性材料をメッキすることに
よって導電部を厚膜化する。蒸着後、メタルマスクを取
りはずし、ついでメッキ工程へ進めることができる。In the method of the present invention, after forming the conductive part of the circuit by vapor deposition, the conductive part is plated with a conductive material to thicken the conductive part. After vapor deposition, the metal mask can be removed and the plating process can then proceed.
導電部にメッキする導電性材料としては、銅、ニッケル
、金、銀、クロム、錫、亜鉛などが挙げられ、従来公知
のメッキ浴組成、メッキ方法を用いて、無電解メッキ、
電解メッキのいずれの方法にてもメッキを行なうことが
できる。メッキ層を形成するにあたり、導電部にメッキ
する導電性材料は、蒸着膜と同種であっても異種の材料
であってもよく、また2種以上の材料を複層にメッキし
てもよい。Conductive materials to be plated on conductive parts include copper, nickel, gold, silver, chromium, tin, zinc, etc., and can be electroless plated using conventionally known plating bath compositions and plating methods.
Plating can be performed by any electrolytic plating method. In forming the plating layer, the conductive material to be plated on the conductive portion may be the same kind of material as the deposited film or a different kind of material, or two or more kinds of materials may be plated in a multilayer.
本発明方法において、蒸着によって得られる回路の導電
部は、次工程であるメッキのための種づけの役目を果し
ており、メッキ後の導電部の厚さがメッキ前の導電部で
ある蒸着膜の厚さの2倍以上、好ましくは5〜100倍
となるようメッキすることが必要である。メッキによっ
て蒸着膜より厚い膜厚を確保することによって、回路に
導通できる電気量を大幅に増大させることができるもの
であって、メッキ厚さは用途に応じて適宜選択すればよ
いが、通常、約IJffil〜約100Pの厚さのメッ
キを施すことが好ましい、メッキ後の導電部の厚さがメ
ッキ前の導電部の厚さの2倍未満では、メッキによって
導通できる電気量の増大が少なくメッキによる効果が十
分でないという問題がある。In the method of the present invention, the conductive part of the circuit obtained by vapor deposition serves as a seed for the next step, plating, and the thickness of the conductive part after plating is equal to that of the vapor deposited film, which is the conductive part before plating. It is necessary to plate the plate so that it is at least twice the thickness, preferably 5 to 100 times the thickness. By ensuring a film thickness thicker than the vapor-deposited film through plating, the amount of electricity that can be conducted through the circuit can be greatly increased.The plating thickness can be selected as appropriate depending on the application, but usually, It is preferable to apply plating to a thickness of about IJffil to about 100P.If the thickness of the conductive part after plating is less than twice the thickness of the conductive part before plating, the amount of electricity that can be conducted by plating will not increase much and the plating will not be possible. There is a problem that the effect is not sufficient.
(発明の効果) 本発明方法は、メタルマスクを用いて蒸着し。(Effect of the invention) The method of the present invention performs vapor deposition using a metal mask.
蒸着膜にメッキを施して導電部を厚膜化するものである
ため、レジストとエツチング工程とを必要とする従来の
方法に比べ、工程が簡単で、回路の精度が高く、エツチ
ング工程による資源の損失がなく、また、現像液やエツ
チング液の廃液処理が不要であるという利点を有してい
る。また、本発明方法によって得られるプリント配綿板
はメッキによって導電部を厚膜化して導通できる電気量
を大幅に多くできるため、電気量による用途の制限がな
くなる。また、回路の導通部の保護、酸化防止、接合の
容易さなどが必要な場合には、目的に応じた導電性材料
をメッキすることによって厚膜化と同時に上記の目的も
達成することができる。Since the conductive parts are made thicker by plating the deposited film, the process is simpler, the circuit precision is higher, and the etching process saves resources compared to the conventional method that requires a resist and etching process. It has the advantage that there is no loss and there is no need to treat waste liquids such as developer and etching liquid. Further, in the printed cotton distribution board obtained by the method of the present invention, the amount of electricity that can be conducted can be greatly increased by thickening the conductive portion by plating, so that there are no restrictions on the use due to the amount of electricity. In addition, if protection of the conductive parts of the circuit, prevention of oxidation, ease of bonding, etc. are required, the above objectives can be achieved at the same time as thickening the film by plating with a conductive material suitable for the purpose. .
以下、実施例を挙げて本発明をより具体的に説明する。Hereinafter, the present invention will be explained in more detail with reference to Examples.
実施例1
厚さ50JIMのポリイミド基板表面にメタルマスクを
被せ、真空蒸着法により銅を幅1mm、長さ100mm
、厚さO,1mに蒸着して回路パターンを作成した。つ
いでメタルマスクを外し、回路パターンを有する基板を
銅の無電解メッキ液中に4時間浸漬し、銅膜上に厚さ2
0戸の銅層を形成し回路を得た。得られた回路に電流5
00mAを流したところ抵抗は8.6X10−”Ωであ
り、熱流は2. l 5X I 0−2Wであった。Example 1 A metal mask was placed on the surface of a polyimide substrate with a thickness of 50 JIM, and copper was deposited to a width of 1 mm and a length of 100 mm using a vacuum evaporation method.
, a circuit pattern was created by vapor deposition to a thickness of 0.1 m. Next, the metal mask was removed, and the board with the circuit pattern was immersed in a copper electroless plating solution for 4 hours, and a 2-thick layer was deposited on the copper film.
A circuit was obtained by forming 0 copper layers. In the resulting circuit a current of 5
When 00 mA was applied, the resistance was 8.6 x 10-''Ω and the heat flow was 2.15 x I0-2W.
なおメッキ前の、銅を蒸着した回路に電流500mAを
流した場合、抵抗は8.7Ωであり、熱流は2.17W
であった。Furthermore, when a current of 500 mA is passed through a circuit with copper deposited before plating, the resistance is 8.7 Ω and the heat flow is 2.17 W.
Met.
実施例2
厚さ70pのポリエチレンテレフタレート(PET)の
基板にメタルマスクを被せスパッタリング法により銅を
幅1mm、長さ100mm、厚さ0.5Pに気相析出さ
せ回路パターンを作成した。ついでメタルマスクを外し
、回路パターンを有する基板をニッケルのメッキ液中に
浸漬し、電解メッキを行なって銅膜上に厚さ20戸のニ
ッケル層を形成した。ついで、このニッケル層上に電解
メッキにより金を厚さ1戸となるよう析出させ回路を得
た。Example 2 A circuit pattern was created by covering a polyethylene terephthalate (PET) substrate with a thickness of 70p with a metal mask and depositing copper in a vapor phase to a width of 1 mm, a length of 100 mm, and a thickness of 0.5P using a sputtering method. Then, the metal mask was removed, and the substrate having the circuit pattern was immersed in a nickel plating solution, and electrolytic plating was performed to form a nickel layer with a thickness of 20 mm on the copper film. Next, gold was deposited on the nickel layer to a thickness of one layer by electrolytic plating to obtain a circuit.
得られた回路に電流1.OOOmAを流したところ抵抗
は0.29Ωであり、熱流は0.29Wであった。なお
、メッキ前の、銅を蒸着した回路に電流1.OOOmA
を流したところ抵抗は3.5Ωであり、熱流は3.5W
であった。A current of 1. When OOOmA was applied, the resistance was 0.29Ω and the heat flow was 0.29W. Note that a current of 1. OOOmA
When flowing, the resistance was 3.5Ω, and the heat flow was 3.5W.
Met.
実施例3
厚さ5OO−のアルミナ基板にメタルマスクを被せ電子
サイクロトロン共鳴法にてニッケルを幅1mm、長さ1
00mm、厚さtPに蒸着させ回路パターンを作成した
。メタルマスクを外し、回路パターンを有する基板のニ
ッケル膜上に無電解メッキ法により厚さ2戸の銀層を形
成し回路を得た。Example 3 An alumina substrate with a thickness of 500- is covered with a metal mask, and nickel is coated with a width of 1 mm and a length of 1 mm using an electron cyclotron resonance method.
A circuit pattern was created by vapor deposition to a thickness of 00 mm and a thickness of tP. The metal mask was removed, and a two-layer thick silver layer was formed on the nickel film of the circuit patterned substrate by electroless plating to obtain a circuit.
得られた回路に電流300mAを流したところ抵抗は7
.3XIO−’Ωであり、熱流は6.6×10−”Wで
あった。なお、メッキ前の、ニッケルを蒸着した回路に
電流300mAを流したところ抵抗は7.2Ωであり、
熱流は6.5XlO−’Wであった。When a current of 300 mA was passed through the resulting circuit, the resistance was 7.
.. 3XIO-' Ω, and the heat flow was 6.6 x 10-' W. When a current of 300 mA was passed through the nickel-deposited circuit before plating, the resistance was 7.2 Ω.
The heat flow was 6.5XlO-'W.
Claims (1)
を介して、プリント配線板基材表面に気相法により蒸着
物質を蒸着させて、厚さ1.0×10^−^2μm〜1
0μmの導電部を有する回路を形成した後、該導電部に
導電性材料をメッキすることによって該導電部のメッキ
後の厚さがメッキ前の厚さの2倍以上となるよう厚膜化
することを特徴とするプリント配線板の製造方法。1. A vapor deposition substance is deposited on the surface of the printed wiring board substrate by a vapor phase method through a metal mask having through-holes corresponding to the circuit pattern to a thickness of 1.0 x 10^-^2 μm to 1 μm.
After forming a circuit having a conductive part of 0 μm, the conductive part is plated with a conductive material so that the thickness of the conductive part after plating is at least twice the thickness before plating. A method for manufacturing a printed wiring board, characterized by:
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32476289A JPH03185787A (en) | 1989-12-14 | 1989-12-14 | Manufacture of printed wiring board |
DE19904037747 DE4037747A1 (en) | 1989-11-27 | 1990-11-27 | Printed circuit board - made by vapour coating substrate prepd. with photoresist pattern |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32476289A JPH03185787A (en) | 1989-12-14 | 1989-12-14 | Manufacture of printed wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03185787A true JPH03185787A (en) | 1991-08-13 |
Family
ID=18169394
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32476289A Pending JPH03185787A (en) | 1989-11-27 | 1989-12-14 | Manufacture of printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03185787A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10322156A (en) * | 1996-06-10 | 1998-12-04 | Fuji Electric Co Ltd | Noise filter for power inverter |
US7758222B2 (en) * | 2001-01-18 | 2010-07-20 | Ventra Greenwich Holdings Corp. | Method for vacuum deposition of circuitry onto a thermoplastic material and a vehicular lamp housing incorporating the same |
-
1989
- 1989-12-14 JP JP32476289A patent/JPH03185787A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10322156A (en) * | 1996-06-10 | 1998-12-04 | Fuji Electric Co Ltd | Noise filter for power inverter |
US7758222B2 (en) * | 2001-01-18 | 2010-07-20 | Ventra Greenwich Holdings Corp. | Method for vacuum deposition of circuitry onto a thermoplastic material and a vehicular lamp housing incorporating the same |
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