JPH04179297A - Connecting circuit pattern on multi-layer wiring board - Google Patents
Connecting circuit pattern on multi-layer wiring boardInfo
- Publication number
- JPH04179297A JPH04179297A JP30750090A JP30750090A JPH04179297A JP H04179297 A JPH04179297 A JP H04179297A JP 30750090 A JP30750090 A JP 30750090A JP 30750090 A JP30750090 A JP 30750090A JP H04179297 A JPH04179297 A JP H04179297A
- Authority
- JP
- Japan
- Prior art keywords
- circuit pattern
- layer
- signal layer
- photosensitive polyimide
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229920001721 polyimide Polymers 0.000 claims abstract description 29
- 239000004642 Polyimide Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052802 copper Inorganic materials 0.000 abstract description 8
- 239000010949 copper Substances 0.000 abstract description 8
- 238000007747 plating Methods 0.000 abstract description 7
- DOBRDRYODQBAMW-UHFFFAOYSA-N copper(i) cyanide Chemical compound [Cu+].N#[C-] DOBRDRYODQBAMW-UHFFFAOYSA-N 0.000 abstract description 3
- 239000011889 copper foil Substances 0.000 abstract description 2
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 abstract description 2
- 238000001771 vacuum deposition Methods 0.000 abstract description 2
- 230000001186 cumulative effect Effects 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 8
- 238000009713 electroplating Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000009719 polyimide resin Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- UOACKFBJUYNSLK-XRKIENNPSA-N Estradiol Cypionate Chemical compound O([C@H]1CC[C@H]2[C@H]3[C@@H](C4=CC=C(O)C=C4CC3)CC[C@@]21C)C(=O)CCC1CCCC1 UOACKFBJUYNSLK-XRKIENNPSA-N 0.000 description 1
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000003618 dip coating Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 231100000331 toxic Toxicity 0.000 description 1
- 230000002588 toxic effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、多層配線基板、特に、絶縁層に感光性ポリイ
ミドを用いた場合におりる回路パターン接続力法に関す
る。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a multilayer wiring board, and particularly to a circuit pattern connection force method when photosensitive polyimide is used as an insulating layer.
〈従来の技術〉
ＩＣの高密度化に伴ない、回路パターンを多層化し、絶
縁層に連結孔を形成して、各回路パターンを接続する多
層配線基板か製造されている。 特に、絶縁層には、ポ
リイミド樹脂を用い、連結孔を介し、金に次いて電気抵
抗の低い銅で形成した各回路パターンを接続する銅−ポ
リイミド基板が重要視されている。<Prior Art> With the increase in the density of ICs, multilayer wiring boards are manufactured in which circuit patterns are multilayered and connecting holes are formed in an insulating layer to connect the circuit patterns. Particularly important is a copper-polyimide substrate that uses polyimide resin for the insulating layer and connects circuit patterns made of copper, which has the second lowest electrical resistance after gold, through connection holes.
ところで、このような銅−ボリイミト基板を多層配線基
板に適用する際には、絶縁層であるポリイミドに、これ
を挟んで配線される回路パターンを接続するためのパイ
ヤポールや、電極ビンと回路パターンを接続するための
スルーホール等の連結孔を作製する必要がある。By the way, when applying such a copper-bolyimide board to a multilayer wiring board, it is necessary to connect the polyimide insulating layer with a wire pole for connecting the circuit pattern to be wired across the polyimide layer, or to connect the electrode bin and the circuit pattern. It is necessary to create a connecting hole such as a through hole for connection.
このポリイミド層形成には、感光性ボリイミ１〜か有効
である。 感光性ポリイミドとけ、感光性をイづ与した
ポリイミド樹脂であり、フォ］・レジストと同様に、フ
才）・マスクを介し紫外線照射した後、所定の現像液で
現像することによリ、連結孔を容易に形成できる。For forming this polyimide layer, photosensitive polyimide 1 to 1 are effective. Photosensitive polyimide is a polyimide resin that has been imparted with photosensitivity and can be bonded by irradiating it with ultraviolet rays through a photoresist and developing it with a designated developer. Holes can be easily formed.
感光性ポリイミド２を用い紫外線照射した場合、ポリイ
ミド膜厚が厚いときに底の方が露光量不足になり、第２
図に示すように現像、熱硬化して得られた連結孔７がテ
ーパー形状になる。 １は第１信号層である。When photosensitive polyimide 2 is irradiated with ultraviolet rays, when the polyimide film is thick, the amount of exposure is insufficient at the bottom, and the second
As shown in the figure, the connecting holes 7 obtained by development and thermosetting have a tapered shape. 1 is the first signal layer.
連結孔がテーパー形状になると、公知の成膜法であるＰ
Ｖ Ｄ （Ｐｈｙｓｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏ
ｓｉｔｉｏｎ）法、ＣＶ Ｄ （Ｃｈｅｍｉｃａｌ Ｖ
ａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法等では連結孔を同
一膜厚で被覆することができない。 そのため、配線抵
抗の増加や、各上下回路パターンの接続不良が発生しや
すい。When the connecting holes have a tapered shape, P
V D (Physical Vapor Depo
(Chemical V) method, CV D (Chemical V
The connecting pores cannot be coated with the same film thickness using the apor deposition method or the like. Therefore, an increase in wiring resistance and a connection failure between the upper and lower circuit patterns are likely to occur.
そこで、従来技術では、連結孔形成後、ヒドラジン系溶
液によるフラッシュエツチングを行い、丸みを付ける対
策を行りていた。Therefore, in the prior art, after forming the connecting holes, flash etching was performed using a hydrazine solution to round the holes.
〈発明が解決しようとするｉｉ！！！題〉前記ヒドラジ
ン系溶液は、強い毒性を示し、危険である。 また、水
と反応すると発熱し、危険である。 また、ヒドラジン
系溶液によるフラッシュエツチングで連結孔テーパー角
を大きくするためには、エツチング時間を長くする必要
があるが、そのために連結孔付近以外のポリイミドもエ
ツチングされてしまう。 これを防止するため、連結孔
付近を露出させたフォトレジストによるマスキングが考
えられるが、工程が繁雑になり感光性ポリイミドを用い
ることによる工程簡略化の意味が失われる。<The invention tries to solve ii! ! ! Problem: The hydrazine solution is highly toxic and dangerous. Also, when it reacts with water, it generates heat and is dangerous. Furthermore, in order to increase the taper angle of the connecting hole by flash etching with a hydrazine solution, it is necessary to lengthen the etching time, but this also causes polyimide in areas other than the vicinity of the connecting hole to be etched. To prevent this, masking with a photoresist that exposes the vicinity of the connecting hole may be considered, but the process becomes complicated and the meaning of process simplification by using photosensitive polyimide is lost.
本発明の目的は、テーパー形状のままの連結孔を介し各
回路パターンを接続する、多層配線基板における回路パ
ターン接続方法を提供することにある。An object of the present invention is to provide a method for connecting circuit patterns in a multilayer wiring board, in which circuit patterns are connected through connection holes that remain tapered.
〈課題を解決するための手段〉
上記目的を達成するために本発明によれば、絶縁層とし
て感光性ポリイミドを適用し、テーパー形状を有する回
路パターン接続用の連結孔を形成する多層配線基板にお
いて、前記連結孔に電解めっきを施すことを特徴とする
多層配線基板における回路パターン接続方法が提供され
る。<Means for Solving the Problems> In order to achieve the above object, the present invention provides a multilayer wiring board in which photosensitive polyimide is applied as an insulating layer and connecting holes for connecting circuit patterns having a tapered shape are formed. , there is provided a method for connecting circuit patterns in a multilayer wiring board, characterized in that the connecting holes are electrolytically plated.
以下に本発明をさらに詳細に説明する。The present invention will be explained in more detail below.
第１〜４図に未発明の多層配線基板における回路パター
ンの接続の一例を示す各段階の断面図が示されている。1 to 4 are cross-sectional views showing each stage of connection of circuit patterns in an uninvented multilayer wiring board.
第１図は、フォトマスク３を介した感光性ポリイミド２
の露光の様子を示す断面図である。FIG. 1 shows a photosensitive polyimide 2 through a photomask 3.
FIG. 3 is a cross-sectional view showing the state of exposure.
本発明では、絶縁層に絶縁性有機物として感光性ポリイ
ミドを用いる。In the present invention, photosensitive polyimide is used as an insulating organic substance in the insulating layer.
前記感光性ポリイミド２は、回路パターンを構成する第
１信号層１上に形成される。The photosensitive polyimide 2 is formed on the first signal layer 1 constituting a circuit pattern.
なお、本発明に適用される感光性ポリイミドは、フィル
ム状、シート状に加工されたものであっても、液体状あ
るいは各種の溶剤に溶解されたものを公知の方法で塗布
し、硬化するものであっても良い。Note that the photosensitive polyimide applied to the present invention may be processed into a film or sheet, but it may be applied in liquid form or dissolved in various solvents and cured by a known method. It may be.
また、回路パターンを形成する導電体（第１信号層１）
としては、銅をはじめ金、銀、アルミニウムおよびその
合金等各種の公知のものがいずれも適用可能である。
しかしながら、コスト、電気抵抗等の点で、銅が最も好
ましい。In addition, a conductor (first signal layer 1) forming a circuit pattern
As the material, various known materials such as copper, gold, silver, aluminum, and alloys thereof can be used.
However, in terms of cost, electrical resistance, etc., copper is most preferred.
第１信号層１上に、スピンコードによって感光性ポリイ
ミド樹脂を塗布し、硬化して、絶縁層を構成する感光性
ポリイミド層２を形成する。 なお、感光性ポリイミド
の塗布方法としては上述のスピンコードに限定されるも
のではなく、ロールコート、デイツプコート等、公知の
方法がいずれも適用可能である。A photosensitive polyimide resin is applied onto the first signal layer 1 using a spin cord and cured to form a photosensitive polyimide layer 2 constituting an insulating layer. Note that the method for applying the photosensitive polyimide is not limited to the above-mentioned spin coating, and any known method such as roll coating or dip coating can be applied.
次いで、第１図に示されるように、感光性ポリイミド層
２の所定の位置に、フォトマスク３を介して紫外線４を
照射し現像、熱硬化し、連結孔７を形成する（第２図参
照）。Next, as shown in FIG. 1, a predetermined position of the photosensitive polyimide layer 2 is irradiated with ultraviolet rays 4 through a photomask 3, developed, and thermally cured to form a connecting hole 7 (see FIG. 2). ).
前記紫外線の照射条件は限定せず、公知の方法が適用で
きる。The conditions for irradiating the ultraviolet rays are not limited, and known methods can be applied.
つぎに第３図に示すように前記連結孔７のみにめっき膜
５を形成する。Next, as shown in FIG. 3, a plating film 5 is formed only on the connecting hole 7.
このめっきＩＩ！ ５は電解めっきにより行う。This plating II! Step 5 is performed by electrolytic plating.
電解めっき浴としては硫酸銅浴またはホウフッ化銅浴は
、浴組成か単純で、管理も簡単な点、シアン化銅浴また
はビロリン酸銅浴は電着性やつきまわりが良く、めっき
が微粒子である点て好ましい。 めっき条件は限定せず
公知の方法を用いることがてきる。As electrolytic plating baths, copper sulfate baths and copper borofluoride baths have a simple bath composition and are easy to manage, while copper cyanide baths and copper birophosphate baths have good electrodepositivity and coverage, and the plating is fine-grained. It's preferable in some respects. Plating conditions are not limited and any known method may be used.
なお、ＣＶＤ法、ＰＶＤ法等では、連結孔７かテーパー
形状であるため均一被膜の形成か困難であり、配線抵抗
の増加や回路パターンの接続不良が避けられない。In addition, in the CVD method, PVD method, etc., it is difficult to form a uniform coating because the connecting hole 7 has a tapered shape, and an increase in wiring resistance and poor connection of circuit patterns are unavoidable.
つぎに第４図に示すように第２信号層６を形成するため
、下地層として、Ｔｉを真空蒸着または、イオンブレー
ティングまたは他のＣＶＤ法によって形成し、さらにそ
の上に真空蒸着、またはイオンブレーティングまたは他
のＣＶＤ法により銅を積層し、第２信号層６を完成させ
る。Next, in order to form the second signal layer 6 as shown in FIG. Copper is deposited by brating or other CVD methods to complete the second signal layer 6.
なお、本発明は上述の例に限定されるものではなく、本
発明の要旨を変更しない範囲において適宜選定できる。Note that the present invention is not limited to the above-mentioned examples, and can be appropriately selected without changing the gist of the present invention.
〈実施例〉 以下に本発明を実施例に基づき具体的に説明する。<Example> The present invention will be specifically explained below based on Examples.
（実施例１）
３５μｍ厚さの銅箔（第１信号層）１に、スピンコード
により感光性ポリイミド２を１５μｍ塗布し、Ｎ２雰囲
気中で、９５℃で７５秒および１１５℃で７５秒のブリ
ヘークをした後、第１図に示すようにフォトマスク３を
介し、積算光量２００ ｍ、１７ｃｍ２で紫外線４を照
Ｑ」し、現像、熱硬化（Ｎ２７１囲気中３５０℃で６０
分）した。 その後、得られた連結孔７のみをシアン化
銅洛中で電気めっきし、めつき膜５を形成した（第３図
参照）。 めっきは、液温６０℃、電流密度２ Ａ ／
ｄ ｍ ’で１５分行った。(Example 1) 15 μm of photosensitive polyimide 2 was coated on a 35 μm thick copper foil (first signal layer) 1 using a spin cord, and then subjected to brihage heating at 95° C. for 75 seconds and at 115° C. for 75 seconds in an N2 atmosphere. After that, as shown in Figure 1, the film was exposed to ultraviolet light 4 through a photomask 3 at an integrated light intensity of 200 m and 17 cm2, developed, and heat cured (60°C at 350°C in an N271 atmosphere).
minute) did. Thereafter, only the resulting connecting holes 7 were electroplated in copper cyanide to form a plated film 5 (see FIG. 3). Plating was carried out at a liquid temperature of 60°C and a current density of 2 A/
dm' for 15 minutes.
その後、真空蒸着法により純度９９９％のＴｉを５００
人、純度９９．９９０％の銅（第２信号層）６を４μｍ
形成し、フォ１〜エッヂングにより第２信号層６を形成
し回路パターンを形成した（第４図参照）。After that, 500% of Ti with a purity of 999% was applied using a vacuum evaporation method.
99.990% pure copper (second signal layer) 6 to 4μm
Then, a second signal layer 6 was formed by photo-etching to form a circuit pattern (see FIG. 4).
得られた第１（：３号層１および第２信号層６は、連結
孔７によって好適に連結されてい／こ。The obtained first signal layer 1 and second signal layer 6 are suitably connected by a connecting hole 7.
〈発明の効果〉
本発明は、以上説明したように構成されているから、ヒ
ドラジン系溶液を用いることによる問題点を全て解決で
きた。<Effects of the Invention> Since the present invention is configured as described above, all the problems caused by using a hydrazine solution can be solved.
また、連結孔をめっきで埋めているので、各回路パター
ン間の接続不良の発生か防止できるという効果を奏する
。Furthermore, since the connecting holes are filled with plating, it is possible to prevent connection failures between the circuit patterns.
第１図は、本発明の多層配線基板におりる回路パターン
の接続において、フォトマスクを介した感光性ポリイミ
ドの露光の様子を示す断面図である。
第２図は、第１ｆｇ号層およびテーパー形状なイ」する
感光性ポリイミドの断面図である。
第３図は、電解めっきを施した連結孔の様子を示す断面
図である。
第４図は、第２信号層を形成した様子を示す断面図であ
る。
符号の説明
１・・・第１信号層、
２・・・感光性ボリイミ１−１
３・・・フォトマスク、
４・・紫外線、
５・・・めっき膜、
６・・・第２信号層、
７・・・連結孔、
１０・・・多層配線基板
％、７１１．−．ＺFIG. 1 is a sectional view showing how photosensitive polyimide is exposed through a photomask in connection of circuit patterns on a multilayer wiring board of the present invention. FIG. 2 is a sectional view of the No. 1fg layer and the tapered photosensitive polyimide. FIG. 3 is a sectional view showing the state of the connecting hole subjected to electrolytic plating. FIG. 4 is a cross-sectional view showing how the second signal layer is formed. Explanation of symbols 1... First signal layer, 2... Photosensitive polyimide 1-1 3... Photomask, 4... Ultraviolet rays, 5... Plated film, 6... Second signal layer, 7... Connection hole, 10... Multilayer wiring board%, 711. −． Z
Claims (1)
ー形状を有する回路パターン接続用の連結孔を形成する
多層配線基板において、前記連結孔に電解めっきを施す
ことを特徴とする多層配線基板における回路パターン接
続方法。(1) A circuit in a multilayer wiring board in which a photosensitive polyimide is applied as an insulating layer and connecting holes for connecting a tapered circuit pattern are formed, wherein the connecting holes are electrolytically plated. Pattern connection method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30750090A JPH04179297A (en) | 1990-11-14 | 1990-11-14 | Connecting circuit pattern on multi-layer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30750090A JPH04179297A (en) | 1990-11-14 | 1990-11-14 | Connecting circuit pattern on multi-layer wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04179297A true JPH04179297A (en) | 1992-06-25 |
Family
ID=17969832
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30750090A Pending JPH04179297A (en) | 1990-11-14 | 1990-11-14 | Connecting circuit pattern on multi-layer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04179297A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11284345A (en) * | 1998-03-31 | 1999-10-15 | Kyocera Corp | Ceramic multi-layer wiring board |
| JP2015012286A (en) * | 2013-07-01 | 2015-01-19 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Printed circuit board and method of manufacturing the same |
| WO2018131285A1 (en) * | 2017-01-13 | 2018-07-19 | 東レエンジニアリング株式会社 | Method for producing flexible printed board, and flexible printed board |
| JP2021039979A (en) * | 2019-08-30 | 2021-03-11 | イビデン株式会社 | Printed wiring board and manufacturing method of the same |
-
1990
- 1990-11-14 JP JP30750090A patent/JPH04179297A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11284345A (en) * | 1998-03-31 | 1999-10-15 | Kyocera Corp | Ceramic multi-layer wiring board |
| JP2015012286A (en) * | 2013-07-01 | 2015-01-19 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Printed circuit board and method of manufacturing the same |
| WO2018131285A1 (en) * | 2017-01-13 | 2018-07-19 | 東レエンジニアリング株式会社 | Method for producing flexible printed board, and flexible printed board |
| JP2021039979A (en) * | 2019-08-30 | 2021-03-11 | イビデン株式会社 | Printed wiring board and manufacturing method of the same |
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