JPH03185546A - Information processor - Google Patents

Abstract

PURPOSE:To obtain a device reducing its I/O space and having no restriction to the number of substrates by mutually connecting a CPU, a memory part and an I/O part through a common bus line, connecting the bus line to a substrate whose connection can be switched and changing data read out in each time when a CPU identifies an ID register. CONSTITUTION:In the case of reading out the contents of the ID register 8 by a CPU 1, an EN signal 14 is turned to 'H', the output 30 of an inverter 29 is turned to 'L', the address of the ID register 8 is outputted to an address bus 24, the output signal 26 of an address decoder 25 is turned to 'L', a IORD signal 22 is turned to 'L' to turn the output 28 of a negative logical AND circuit 27 to 'L' and drive a buffer 23, and the contents of the ID register 8 are outputted to a data line 3. Consequently, only the minimum I/O space is used for identifying the substrate 5 and the substrate 5 can be easily extended without changing the original substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic information processing device that connects and disconnects switchable boards, for example, connects and disconnects a plurality of boards to make a determination.

[Prior Art] Conventionally, as shown in FIG.
There are many ID registers in the 0 space, and the number of ID registers is predetermined.

In the example shown in FIG. 5, there are 3M of 10 8-bit registers, and the maximum number of boards that can be distinguished is (8x8x8).

"Identify" is used here to mean "determine whether or not they are the same."

[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, the ID register is
There are problems such as requiring a large number of ID registers in the space, and because the number of ID registers is determined in advance, there is a limit to the number of boards, and once the maximum number is used, it is impossible to increase the number of boards any more. There were problems, such as if you tried to force the increase, you would have to start over from the first board.

The purpose of this invention is to provide a device in which the I10 weight layer is as small as possible and the number of substrates is not limited even if the number of substrates is increased.

[Means for Solving the Problems] The present invention comprises at least one CPU as a central processing unit necessary for information processing, a memory unit that exchanges data with the CPU, and an input/output mechanism for the data. 110 part, the CPU, the memory part, and the 110 part are connected by a common bus line, and further, the bus line is connected to a board whose connection can be switched, and each of the boards can be identified. The present invention is characterized in that it includes at least one ID register, and includes means for changing data read each time the CPU identifies the ID register.

[Example] The details of the present invention will be explained below based on the illustrated example.

FIG. 1 is a diagram of an embodiment of a device for identifying each connection board of the present invention, in which l is a CPU, 2.3 is a data line generally used as a common bus line, 4 is an electronic device, 5 is a removable connection board, 6.7 is a connector for connecting the boards, and 8 is an ID register. As shown in FIG. 1, by connecting the connectors 6.7, the data lines 2 and 3 are connected, and the ID register 8 can be read by the CPUI.

FIG. 2 shows the ID register 8 of FIG. 1, which is a feature of this product.
In one embodiment, FIG. 3 is a timing diagram illustrating FIG. 2. In FIG. 2, 11 to 13 are flip-flop circuits (hereinafter abbreviated as F/F), and the EN signal 14 is "L".
As a result, F/Fll becomes “H” and F/F 1
2 and 13 are initialized to "L". The outputs of F/Fil-13 are signals 15-17, respectively. Signal 15-1
7 is ANDed by the AND circuits 18 to 20 and further ORed in the OR circuit #i21 to become the 7th bit of the data in the ID register.

Actually, the AND circuit is 18 to 20, and the OR circuit 21 is 8.
! There are 8 bits of the ID register. These 8 bits are output to the data line 3 by the buffer 23. When the CPUI reads the ID register, it first reads E.
The N signal 14 is set to "H", the output 30 of the inverter 29 is set to "L", the address of the ID register is outputted to the address bus 24, and as a result, the output signal 26 of the address decoder 25 is set to "L", and then the output signal 26 of the address decoder 25 is set to "L". This is done by setting the l0RD signal 22 to "L", thereby setting the output 28 of the negative logic AND circuit 27 to "L", driving the buffer 23, and outputting the contents of the ID register to the data line 3.

With reference to FIG. 3, the operation of the circuit of FIG. 2 will be explained. F/Fs 11 to 13 are initialized by the EN signal "l" and "jf". First, the EN signal 14 becomes "H" and the inverter 2
It is assumed that the output 30 of the address decoder 25 becomes "L", the address indicates the address of the ID register, and the output 26 of the address decoder 25 is already "L". When the l0RD signal 22 first becomes "L", only the signal 15 is "Hut",
Signals 16 and 17 are “L”, so AND times! ! a19.
The output of F/F 20 becomes 91 L", and the state of the switch 31 becomes the output of the OR circuit 21. At the rising edge of the l0RD signal, F/Fs 11 to 13 output the state of 0 manual power to Q,
Since the input of F/F l 1 is fixed at ``L'', the signal 15 goes to ``L''.For F/F 12, the output of F/Fll is manually input, so the signal 16 goes to ``H'', and for F/F 13, Since the output of the F/F 12 is input, the signal 17 becomes "L".

Next, when the IO'RD signal becomes "L", only signal 16 is "H" and signals 15.17 are "L", so switch 3
The state of 2 becomes the output of the OR circuit 21.

In the same way, continue < l0 At the rising edge of the RD signal, F/Fi
The output signal 15 of F/F12 is "L", and the output signal 1 of F/F12 is "L".
6 is “L”, and the output signal 17 of F/F 13 is pp H
“For this reason, the third [)RDIN No. II
When Ll+, only the signal 17 is II HIT, so the state of the switch 33 becomes the output of the OR circuit 21. In this way, three different states can be read out in succession with the ID register at the same address. In this way, by setting the ID number of the board in the switches 31 to 33, the CPU 1 can read it and identify the board.

In FIG. 2, switches 31 to 33 are used to provide versatility, but l! If HIT II L,''' is fixed, AND circuits 18 to 2o are not necessary.
II When HIT, input signals 15 to 17 to the OR circuit 21, and when “L” input the OR circuit 21 to +lLI+
It can be fixed or human power can be removed.

Of course, the same effect can be obtained even if the logic is reversed in both FIGS. 2 and 3.

FIG. 4 shows the ID register space realized by the circuit shown in FIG. 2, and one ID register can distinguish between (8×8×8) boards.

Furthermore, if you want to increase the number of boards, use the OR circuit 2 in Figure 2.
1 is powered by 4 people and 5 people, each is equipped with a switch, ant circuit, and F/F, and the 4th read from CPU 1,
It is sufficient to perform the fifth lead.

Further, this addition can be performed only on the newly added board without affecting the identification of the previous board.

[Implementation Effects] As described above, according to the present invention, only the minimum I10 space is required to identify a board, and additional boards can be easily added without changing the previous board. It made it possible to do this.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram showing the entire electronic device of this invention, Fig. 2 is an explanatory diagram of an embodiment showing the configuration of the ID register in Fig. 1, and Fig. 3 is a timing diagram explaining Fig. 2. , 4th
The figure is an explanatory diagram of an ID register realized by the present invention, and FIG. 5 is an explanatory diagram of a conventional ID register. 1: CPU 2. 3: Data line (common bus line) 4: Electronic equipment 5: Connection board 6. 7: Connector 8: ID register or higher

Claims (1)

[Claims] at least one CPU as a central processing unit necessary for information processing; a memory unit that exchanges data with the CPU; an I/O unit that constitutes an input/output mechanism for the data;
The CPU, the memory section, and the I/O section are connected by a common bus line, and the bus line is further connected to a board whose connection can be switched, and each board has at least one part that can be identified. 1 ID
A register is provided, and the ID register is connected to the CPU.
1. An information processing device comprising means for changing data read each time the device is identified.