JPH03185492A - Allocating method for image memory and address generation circuit - Google Patents

Abstract

PURPOSE:To efficiently allocate an image with size hard to allocate to memory size by effectively arranging the image on a memory by dividing into two parts. CONSTITUTION:Two frames of the image with frame of (m1 X n1) are allocated on s emiconductor memory with size of (M X N) as shown in figure. The image of (m1 X n1) is divided into two parts with an N/2 line, which generates a split image 1 of (m1 X N/2) and a split image 2 of (m1 X(n1-N/2)). In the split image 1, the horizontal address and the vertical address of the image are conformed to the column address and the row address of the memory, respectively, and a memory area of (m1 X N) is occuplied by the split image of two frames. Meanwhile, in the split image 2, such conversion as to conform the horizontal and vertical addresses of the image to the row and column addresses of the memory is performed, the vertical and horizontal lines of the image are set adversely. Thereby, it is possible to efficiently allocate the image with size hard to allocate to universal memory size(power on 2).

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory allocation method for image data handling high-definition signals and the like, and an address generation circuit thereof.

Conventional technology In Japan, in 1987 the Broadcasting Technology Development Council (B
A studio standard for high-visitan signals has been established in TA), and in this standard, the effective pixels of high-visitan signals are 1920x1035. Since the capacity of a general-purpose memory is a power of 2, it is difficult to efficiently allocate an image of this size to the memory. As one method, FIG. 5 shows an example in which two frames of images are allocated on a 2048×204B memory. In this case, image data from the 1st line to the 1035th line of 1 frame is packed in order from the top.

Problem to be Solved by the Invention However, when image data is arranged in memory as described above, what are the horizontal and vertical addresses (line numbers) of the image, and the column and row addresses of the memory? j
Because of this, complex calculations are required to obtain the real address on the memory from the image address, or a large-capacity ROM (read-only memory) for address conversion is required.

! 1! Means for Solving the Problems The present invention solves the above problem, and when allocating two frames of an image of ml Divided image 1 is divided into two parts and assigned to memory column addresses 0 to (m1-1) and row addresses O to (N-1), and divided image 2 has horizontal and vertical addresses assigned to memory row and column addresses, respectively. This is an image memory allocation method in which the image memory is allocated to column addresses m1 to (M-1) and row addresses 0 to (ml-1) by corresponding substitution. This address generation circuit includes means for generating an identification signal, and means for generating a row address and a column address of an image memory using the area identification signal and frame identification signal.

Effect The present invention uses the above-described method of allocating image data on the memory and its address generation circuit to divide the image into two parts and effectively arrange them on the memory when the size of the image is not a power of two. , and can be realized with a simple circuit configuration to access image data at any position.

As shown in FIG. 1, a 1ia2 frame with a size of 1 frame ml Xn is allocated on a semiconductor memory with a size of MXN that satisfies the conditions of the embodiment. m, Xn.

image - divided into two by a line, each m.

The division of! In the 0-divided image l, which is 12, the horizontal address and vertical address of the image correspond to the column address and row address of the memory, respectively, and the divided image 1 of 2 frames occupies a memory area of m, XN. On the other hand, division i1 ([2 is converted so that the horizontal and vertical addresses of the image correspond to the row and column addresses of the memory, and the vertical and horizontal directions of the image are reversed, as shown in Figure 1. Figure 2 shows the address generation circuit of the memory to which image data is allocated in this way.In Figure 2, l is a horizontal address generation section, 2 is a vertical address generation section, and 3 is an area identification signal generation section. Department,
4 is a column address generator, and 5 is a row address generator.

When accessing certain data (k, 1) from the image data of 1 frame of ml xn, first the horizontal address generator 1 outputs the horizontal address k, and the vertical address generator 2 outputs the vertical address l. Then, in the area identification signal generation unit 3, the vertical address l and the value □ are compared in size, and when l is □, it is determined that it is the area of divided image 1, and when l≧, it is determined that it is the area of divided image 2. A region identification signal is generated. The horizontal address and vertical address are converted by the above-mentioned area identification signal as well as the frame identification signal for selecting frame 1 or frame 2, and the column address generator 4 and the row address generator 5 output the memory as shown in Table 1. The upper column address and row address are generated.

(Margins below) As can be understood from Table 1, the column and row addresses of the memory can be used as they are, such as the horizontal and vertical addresses of the image, or can be added with appropriate values.

This can be done with an operation similar to subtraction.

Next, as a specific example, M, N-21/204B.

The case where m, -1920, 1024<n, ≦1088 will be explained with reference to FIG. FIG. 3 shows the allocation of image data to the memory in the case of the above setting values, and FIG. 4 shows the address generation circuit in this case.
8, so both the column address and row address of the memory are 11.
Since it can be expressed in bits, the column address can be changed from ADO to ADIO.
Let the 1-row address be ADII-AD21. frame l
, the image data of up to 1024 lines in frame 2 is set as divided image 1, and each memory column address is 0 to 1919.
, row addresses 0-1023 and column addresses 0-1919,
It is allocated to the area of row addresses 1024 to 2047.

The image data in the area exceeding 1024 lines is split image 2.
Convert the vertical and horizontal as
~1983, row address 0-1919 and column address 19
84 to 2047. ii! If the number of lines of the ii image is 1088, the entire area of divided image 2 on the memory will be used, and if it is less than that, the unused area in the memory will increase. An address generation circuit for such a memory is shown in FIG. 4. In FIG. 4, 6 is a horizontal address counter, 7 is a vertical address counter, 8 is a selector for selecting one signal from two signals, and 9 is a horizontal address counter.゜10.11.12 is the buffer y (BuFl ~ B
uF4), and 13 is an inverter. When accessing image data (k, jl) at an arbitrary position, L
Give 1 to the load value A and 1 to the load value B, load the horizontal address counter 6 and vertical address counter tuff with the Load signal, and output 1 vertical address 1 to the horizontal address from the horizontal address counter 6 and vertical address counter 7, respectively. do. The horizontal address counter 6 outputs the horizontal addresses of the image from 0 to 1919, and the vertical address counter 7 only needs to output values up to 1087 as the vertical address, so both output 11 bits. (
In order to determine in which region of the divided image 11 divided image 2 the image data at the position k, ff1) is included, it is sufficient to compare the value of the vertical address l with the value of 1024 m t'M
If the area identification signal is 1 bit and a time-division image of "L@ level" is created, and when it is at "H" level, it is divided image 2, the most significant bit of the vertical address output from the vertical address carantuff is shown in Figure 4. can be treated as an area identification signal as is. If the frame identification signal is an 1-bit signal that is at the "L" level when selecting frame 1 and the "H" level when selecting frame 2, then the image horizontal address, vertical address, memory column address, row The conversion to addresses is as shown in Table 2.

(Margin below) Frame identification signal “L” r ell area identification signal “L” (
In the case of frame 1, divided image 1), the column address and row address are the horizontal address and vertical address themselves, respectively, so the column address ADO-ADIO is B u F
1 Select the output of (9), while one line address ADII
-Address signals for ADII to AD20 of AD21 are output from BuF3 (II), and AD21 is output from selector 8. B u F 1 (9) ~ B u F 4 (m
The buffer is a tri-state output, and when the output enable (OE) signal is 'L', the input to the buffer is output, and when it is 'H', it is a high impedance output. Therefore, in this case , 8uF 1(9)
, BuF30D's OB signal is a region identification signal inputted manually, so the column address and row address are output as described above.

In addition, in the selector 8, the area identification signal is input to the input switching signal, and when it is "Lo", the frame identification signal is selected, and ""H
'', the highest focus point of the output of the horizontal address counter is selected.From Table 2, when the area identification signal is "L", the horizontal address is selected as the column address, so B u
An area identification signal is input as the OE of F 1 (9).

When the sI area identification signal is 'H', B u is used as the column address.
F 4 (In the mountain man figure 4 of in, B u Fl (
9) ~ B u F 4G21 is a three-state output, and when the OE signal is L1, the input to the buffer is output, and when it is 'H', it becomes a high impedance output.B
The OE signals of u F 1 (9) and Bu F 300 are input with area identification signals, while BuF2Ql.

As the OB signal of BuF4Q21, a signal obtained by inverting the area identification signal by an inverter 13 is input. B u F L (9
) is the 11-bit output from the horizontal address counter 6, and BuF2QII1 is the 11-bit output from the horizontal address counter 6.
0 bit is input. In addition, the output lO bit of the vertical address counter 7 is input to BuF3QD, and Bu
The 6 bits from the least significant bit, a frame identification signal, and a load value C are input to F40B. In the selector 8, an area identification signal is input as an input switching signal, and when the area identification signal is "L", a frame identification signal is output, and "
(2) When the value is ``, the most significant bit of the horizontal address counter 6 is output.

Therefore, as shown in Table 2, when the area identification signal is L'', Bu
From F 1 (9), the horizontal address is selected as the column address, and from B u F 3 (from 10, the row address A
D! A vertical address is outputted to AD21 through selector 8, and a frame identification signal is outputted to AD21 to obtain a desired memory address signal. Further, when the area identification signal is "H", the output of the horizontal address generation circuit 6 is selected by the selector 8 and the output of the BuF 20 as the row address, while the output of the BuF 4 G21 is selected as the column address. The hour column address is 102 from the vertical address.
It is the sum of the value minus 4 and a predetermined value, and the former can be the signal of the lower 6 bits of the vertical address, and the latter takes the value 1920.1984 depending on frame 1 and frame 2, so it can be expressed in hexadecimal. "780", 7CO" and bottom 6
ADO of the column address where all bits are at L” level ~
Assign the lower 6 bits of the vertical address signal to AD5,
AD7 to ADIO are all set to "H" level, AD6 is set to "L" during frame 1, and set to II HII during frame 2.

Therefore, in FIG. 4, a frame identification signal is input to B u F 40Z so that it is output to AD6, and Lo
ad4Iic becomes a 4-bit signal of all H''.

As explained above, in the address generation circuit shown in FIG. 4, it is possible to convert the horizontal address and vertical address of arbitrary data of an image into the actual column address and row address of the memory.

In addition, in FIG. 4, Load(!A and Load value B are both O'', and the horizontal address counter 6 is 0 to 1919.
Each time the vertical address counter 7 is counted, the vertical address counter 7 is increased by one, and the vertical address counter 7 is 0 to n1 (1025
~108B) By counting, it is possible to access all the truth data of 1 frame from the upper left corner.

As described in detail of the invention, the image memory allocation method according to the present embodiment and its address generation circuit efficiently allocate an image of a size that is difficult to allocate to a general-purpose memory size (power of 2), and furthermore, the horizontal address of the image, Conversion from vertical addresses to real memory addresses can be performed with a simple circuit.

[Brief explanation of drawings]

FIG. 1 is a memory map diagram showing the image memory allocation method of this embodiment, FIG. 2 is an address generation circuit diagram of the image memory, FIG. 3 is an explanatory diagram showing a specific example of FIG. 1, and FIG. FIG. 3 is an image memory address generation circuit diagram, and FIG. 5 is a memory map diagram showing a conventional image memory allocation method. 3... Area identification signal generation section, 4... Column address generation section, 5... Row address generation section.

Claims (3)

[Claims] (1) [N=2^n, M=2^m 2n_1>N>n_1 N>m_1 M-m_1>2n_1-N] (where n, m, n_1, m_1 are positive integers) satisfies the following conditions. One frame m_1× on M×N semiconductor memory
When allocating two frames of an image of size n_2, one frame image is divided by N/2 lines, and divided image 1 up to N/2 line and divided image 2 after N/2 line are created.
The divided image 1 is divided into column addresses 0 to (
m_1-1), row address 0 to (N/2・1) and column address 0 to (m_1-1), row address N/2 to (N-1)
), and the divided image 2 is replaced so that the horizontal and vertical addresses of the image correspond to the row and column addresses of the memory, respectively, and the column address m_ in the area excluding divided image 1 is
1 to (M-1) and row addresses 0 to (m_1-1). (2) m=n=11, m_1=1920, 1024<n
_1≦1088, and the memory area of divided image 2 is set to column address 1920~(n_1+895) and row address 0.
~1919 and column address 1984~(n_1+959)
2. The image memory allocation method according to claim 1, wherein the image memory allocation method is characterized in that the image memory is allocated to row addresses 0 to 1919. (3) When accessing the image memory according to the image memory allocation method of claim (1), means for generating an area identification signal for identifying whether image data belongs to divided image 1 or divided image 2; , a row address generation unit and a column address generation unit for converting horizontal and vertical addresses of an image into row addresses and column addresses of an image memory using a frame identification signal for selecting frame 1 or frame 2 and the area identification signal. An address generation circuit comprising: