JPS59132478A - Access circuit of random access memory - Google Patents

Abstract

PURPOSE:To attain access from both column and row directions by providing two kinds of access means accessing a memory chip to both row and column directions to an access circuit. CONSTITUTION:In performing row (lateral) direction access, a signal appearing at an address terminal A4 of a CPU 27 goes to an L level. Then, a row decoder 21 decodes an input signal and enables a memory chip 11 of a designated row. Further, data selector bidirectional buffers 23-1-23-4 select one terminal group among the left half terminal groups of the memory side and access four memory chips 11 of the disignated row at the same time. In performing column (longitudinal) direction access next, a signal appearing at the address terminal A4 goes to an H level. A column decoder 22 decodes the input signal in this state and enables the memory chip 11 of the designated column. Further, the buffers 23-1-23-4 select one terminal group among the right half terminal groups of the memory side.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a random access memory access circuit for writing and reading from a random access memory.

[Technical Background of the Invention] For example, in a facsimile copying machine in which image information can be edited electronically, a random access memory is used to perform processing such as enlarging or reducing image information.

FIG. 1 is a simplified representation of one random access chip. This memory chip 11 has dip select 1 terminal O8, address terminals A1, A
O and data terminal D are provided. As shown in Fig. 2, when signal "1'' is input to chip select terminal O8, the data terminal becomes high impedance. .When the signal OIT is input manually, this menu 11 becomes enabled, and the address terminals A1 and A
4 types of data [1 to D] depending on the signal input to O
One of the four is selected.

``Prior Art'' FIG. 3 shows a conventional address circuit using a random access memory in which the metric chips described above are arranged in a matrix.

In the figure, memory depths 11-11 to 11.7! are arranged in 4 rows and 4 columns!
14 are arranged. The terminal configuration of these memory chips 11 is as shown in FIG. This random access memory is equipped with a decoder 12 for selecting memory chips 11 row by row. CPLI (
The central processing unit 13 selects data based on four types of addresses output from address terminals A'1 and A. The human output data of the memory chip 11 is read by the CPU.
Thirteen data terminals D3 to D2 are output or input in units of columns.

In electronic devices using such synonymous access memory address circuits, it is easy to read and write data row by row, but it requires many steps to access data in the column direction. However, the disadvantage is that it takes a long time to process. Random address that selects memory chips in columns by decoder
In memory, on the other hand, processing data row by row is in-house work. However, with conventional Ackles circuits like this, it takes time to convert vertical (column) data and horizontal (row) data, such as when rotating image information by 90 degrees. Rough 1 ~ There was a drawback that the wear itself was complicated.

[Object of the Invention] In view of these circumstances, the present invention provides a random access system that can be accessed from either the row direction or the column direction.
Its purpose is to provide an access circuit (for access memory).

[Means for achieving the object] In the present invention, there are two kinds of access means: a row direction access means for accessing the memory chip in the fi'/'j direction, and a column direction access means for accessing the memory chip in the column direction. The knock access circuit is provided with u1 to achieve the above-mentioned purpose.

The present invention will be described in detail below with reference to Examples. .

[Embodiment j FIG. 4 shows the access circuit of this embodiment. The terminal configuration t of a memory chip 11 consisting of a 1.times.4 bit random access memory is as shown in FIG. This circuit includes a row decoder 21 for selecting a memory chip 11 in row units and a column decoder 22 for selecting a memory chip 11 in the middle of a column. There are also four data selectors and bidirectional Bano I23-1 to 23- for data selection and buffer linking.
4 corresponding to each column and row. Each memory chip 11-11 to 11-. 44 chip select terminal O
8 is an OR circuit 24-11 to 2 that calculates the logical sum of two people.
/l-/14 are arranged correspondingly. 1st
A first row select signal 25-1 is supplied from the row direction decoder 21 to one input terminal of the four OR circuits 24-11 to 24-14 in the row. Similarly, the second to fourth row select signals 25-2 to 25-2 corresponding to the Ono 7 circuits 24=~21 to 24-44 in other rows on a row-by-row basis
4 is supplied J: Sea urchin. On the other hand, 4 in the first row
One Onono Circuit 11-'+ 1.11-21.11-3
The first column direct signal @26-1 is supplied from the column direction decoder 22 to the other human horn terminal of 1.11-41. Similarly, A circuits 11-12 in other columns
．． 11-22.11-32,...'...11-34
．． 11-4/I is also supplied with second to fourth column select signals (26-2 to 26-4) corresponding to the column unit C'. Row direction decoder 21 and column direction decoder 22
From the three address terminals A4, AI, Δ■ of U27 to the respective input sides (here, CI) of memory chip '11
7 addresses are provided for individually specifying. Among them, the fourth address: child△4 hl
+ and others select one of the two decoders 21 and 22.
An address is provided to access the address.

The designations of 71 to 71 of each memory deep 11 connected to this circuit are made using the two address terminals A3 and A2 of the CPU 27.
It is now carried out by

Next, the relationship between the data filler and the bidirectional buffer 23 that serve this circuit will be explained. 4 memory chips in the first row 11-11.11-21.11-3-1.11
-4.1 data terminal is 1 to 1 data terminal.
It is connected to the terminal group on the left half of the memory side of the bidirectional battery 7'23-1. Memory chip 1 in other row
1-12.11-22.11-32,...11
The data terminal of -34.11=/1.4 is the memory side half of the second to fourth data selectors/bidirectional buffers 23-2 to 23-4 corresponding to each column. connected to the terminal group. On the other hand, the data terminals of the four memory chips 11-11 to 11-14 in the first row are connected to the right half terminal group on the memory side of the first data selector/bidirectional buffer 23-1. The data terminals of the memory depths 11-21 to 11-44 in other rows are also connected to the right half of the memory side in the second to fourth data selectors/bidirectional balanoas 23-2 to 23-/I corresponding to each row. connected to the terminal group. Each data selector/bidirectional Balanor 23-1/-23-4 CI) tJ side has a data terminal D h< Similarly, there are terminals on the CPU side for selecting the row or dead direction and the address to be added to the memory chip 11.
l27 address terminal A71. C is connected to A3 and Δ2, respectively. FIG. 5 shows the specific circuit configuration of each data selector/bidirectional buffer 23-1 to 23-'I.

First, we will explain the case where the access circuit of this random access memory performs access in the row direction and the horizontal direction. In this case, the signal appearing at the address terminal A4 of CI-)t, I27 becomes a low) level. - Then, the row-direction decoder 21 decodes the code II and enables the memory chip 1 in the designated row. In addition, each data selector/bidirectional buffer 23-1-23-/
I selects one of the terminals on the right half of the memory side and simultaneously accesses the four memory chips 11 in the designated row. Next, address the column direction (#ih direction)? If yes, the signal appearing at address terminal A4 of CPtJ27 becomes 1-I<bin level. Column direction decoder 2
2 deciphers the incoming horn signal in this state, and at the designated evening 1j
Enable memory chip 1-1. In addition, each data selector/bidirectional buffer 23-1 to 23-4 is
One of the terminals on the right half of the memory side is selected, and the four memory chips 11 in the designated column are simultaneously accessed.

The circuit of the embodiment described above uses a data selector/bidirectional buffer that performs both data selection, reading, and writing, but is not limited to this. It is also possible to perform data conversion in the row direction and column direction after only one side of writing. Further, in the embodiment, a memory chip for a 1×4 pixel 1 has been described, but it is understood that the present invention is not limited to this. Further, in this circuit, selection in the row or column direction is performed using address information directly output from CI), but it can also be performed via I10 baud1~.

[Effect of the invention 1] As explained below, according to the present invention, a data selector for selecting data is provided on the data line, so that data can be selected in the row or column direction (horizontal or vertical direction). I made it. Therefore, the higher the number of bits of data, the faster the processing speed can be compared to the conventional method. This has the advantage of being able to perform advanced data processing.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram showing the arrangement of the terminals of the rank "A-access memory," Fig. 2 is an explanatory diagram showing the relationship between the signals appearing at each terminal of the sindam access memory, and Fig. 3 is an explanatory diagram showing the arrangement of the terminals of the rank "A-access memory." -111/y diagram showing an example of an access circuit of a random access memory according to an embodiment of the present invention; Figure 5 is a diagram showing the specific configuration of the data selector/bidirectional buffer of this circuit. 11... Memory chip, 23... Data selector/ bidirectional buffer,
27...CI) U 0 Application Fuji Xerox Co., Ltd. Ne1- Representative Patent Attorney Ume Yamauchi M1

Claims (1)

[Claims] 1. Random access memory access characterized by comprising a row direction addressing means for addressing memory chips arranged in a matrix in the row direction thereof, a column direction access means for addressing the memory chips in the column direction, etc. circuit.