JPH0318333B2 - - Google Patents
Info
- Publication number
- JPH0318333B2 JPH0318333B2 JP56096141A JP9614181A JPH0318333B2 JP H0318333 B2 JPH0318333 B2 JP H0318333B2 JP 56096141 A JP56096141 A JP 56096141A JP 9614181 A JP9614181 A JP 9614181A JP H0318333 B2 JPH0318333 B2 JP H0318333B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon nitride
- nitride film
- film
- silicon dioxide
- dioxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 31
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 25
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 17
- 235000012239 silicon dioxide Nutrition 0.000 claims description 15
- 239000000377 silicon dioxide Substances 0.000 claims description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 8
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 238000002048 anodisation reaction Methods 0.000 claims 1
- 230000003647 oxidation Effects 0.000 description 12
- 238000007254 oxidation reaction Methods 0.000 description 12
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 8
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 4
- 230000003139 buffering effect Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、特に窒
化ケイ素膜の除去方法の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for removing a silicon nitride film.
半導体装置の高集積化に対する有効な方法であ
る選択酸化法を行なう場合、一般に耐酸化マスク
として窒化ケイ素膜が用いられており、選択酸化
終了後に上記窒化ケイ素膜を除去する方法として
は、従来、以下に述べるように熱リン酸による除
去方法が行なわれていた。 When performing selective oxidation, which is an effective method for increasing the integration of semiconductor devices, a silicon nitride film is generally used as an oxidation-resistant mask, and conventional methods for removing the silicon nitride film after selective oxidation are A removal method using hot phosphoric acid was used as described below.
すなわち、第１図に示すように、最初に半導体
基板１を酸化して緩衝用二酸化ケイ素膜２を形成
し、その上に耐酸化用マスクの窒化シリコン膜３
を形成した後に選択酸化を行なつているが、この
とき上記窒化ケイ素膜３表面も少し酸化され、二
酸化ケイ素膜４に変化する。それで、窒化ケイ素
膜を除去しようとする場合には、前処理としてフ
ツ酸系エツチング液により上記二酸化ケイ素膜４
を除去することが必要であつた。さらに、この工
程後、熱リン酸を用いて上記窒化ケイ素膜３を除
去する場合にも、上記窒化ケイ素膜３が完全に除
去されたか否かの終点判定が困難であり、また用
いた熱リン酸の温度、濃度等の条件によつてはフ
イールド二酸化ケイ素膜５も大きくエツチングさ
れる場合があつた。さらにまた、この工程終了
後、半導体基板１を露出させるためには、フツ酸
系エツチング液を用いて、緩衝用二酸化ケイ素膜
を除去する必要があつた。 That is, as shown in FIG. 1, a semiconductor substrate 1 is first oxidized to form a buffering silicon dioxide film 2, and a silicon nitride film 3 as an oxidation-resistant mask is formed thereon.
After forming, selective oxidation is performed, and at this time, the surface of the silicon nitride film 3 is also slightly oxidized and changes to a silicon dioxide film 4. Therefore, when attempting to remove the silicon nitride film, the silicon dioxide film 4 is etched using a hydrofluoric acid-based etching solution as a pretreatment.
It was necessary to remove the Furthermore, even when the silicon nitride film 3 is removed using hot phosphoric acid after this step, it is difficult to determine the end point whether or not the silicon nitride film 3 has been completely removed. Depending on the conditions such as the temperature and concentration of the acid, the field silicon dioxide film 5 may also be etched to a large extent. Furthermore, after completing this step, in order to expose the semiconductor substrate 1, it was necessary to remove the buffering silicon dioxide film using a hydrofluoric acid-based etching solution.
以上に述べたように、従来の窒化ケイ素膜除去
方法によれば、熱リン酸で１回、フツ酸系エツチ
ング液で２回のエツチングが必要であり、さらに
窒化ケイ素膜除去の際の終点判定方法および熱リ
ン酸によるエツチング条件の管理等に問題があつ
た。 As mentioned above, according to the conventional silicon nitride film removal method, it is necessary to perform etching once with hot phosphoric acid and twice with a hydrofluoric acid-based etching solution, and to determine the end point when removing the silicon nitride film. There were problems with the method and the management of etching conditions using hot phosphoric acid.
本発明はかかる欠点を除去したもので、その目
的は窒化ケイ素膜除去方法の改良である。 The present invention eliminates these drawbacks, and its purpose is to improve the method for removing silicon nitride films.
第２図において、選択酸化終了（第２図Ｂ）ま
では、従来の方法と全く同様である。選択酸化終
了後、第２図Ｃに示すとおり、プラズマ陽極酸化
法により、窒化ケイ素膜３を完全に二酸化ケイ素
膜６にかえてしまう。このとき、従来の熱酸化法
を用いずに、プラズマ陽極酸化法を用いることに
より、半導体基板１のケイ素と窒化ケイ素膜３は
ほぼ同じ速度で酸化することができる。この結果
第２図Ｃに示すとおり、窒化ケイ素膜３は完全に
二酸化ケイ素膜に変化しており、フツ酸系のエツ
チング液を用いてエツチングすることにより、容
易に除去することができる。 In FIG. 2, the process up to the end of selective oxidation (FIG. 2B) is exactly the same as the conventional method. After the selective oxidation, as shown in FIG. 2C, the silicon nitride film 3 is completely converted into a silicon dioxide film 6 by plasma anodic oxidation. At this time, by using the plasma anodic oxidation method without using the conventional thermal oxidation method, the silicon of the semiconductor substrate 1 and the silicon nitride film 3 can be oxidized at approximately the same rate. As a result, as shown in FIG. 2C, the silicon nitride film 3 has completely changed to a silicon dioxide film, and can be easily removed by etching using a hydrofluoric acid-based etching solution.
本発明は、以上に示したように、フツ酸系エツ
チング液を用いた１回のエツチングで半導体基板
を露出させることができ、しかもエツチング終点
の判定が容易に行なえるなど、工程の平易化、簡
略化にすぐれた効果を有するものである。 As described above, the present invention simplifies the process by exposing the semiconductor substrate in a single etching process using a hydrofluoric acid-based etching solution, and making it easy to determine the etching end point. This has an excellent effect of simplification.
第１図Ａ〜Ｅは、従来の窒化ケイ素膜除去方法
を示すプロセス断面図、第２図Ａ〜Ｄは本発明に
よる窒化ケイ素膜除去方法の一実施例を示すプロ
セス断面図である。
１……半導体基板、２……緩衝用二酸化ケイ素
膜、３……窒化ケイ素膜、４……選択酸化により
窒化ケイ素膜が酸化されてできた二酸化ケイ素
膜、５……プラズマ陽極酸化により窒化ケイ素膜
が酸化されてできた二酸化ケイ素膜。
1A to 1E are process sectional views showing a conventional silicon nitride film removal method, and FIGS. 2A to 2D are process sectional views showing an embodiment of the silicon nitride film removal method according to the present invention. 1...Semiconductor substrate, 2...Silicone dioxide film for buffering, 3...Silicon nitride film, 4...Silicon dioxide film formed by oxidizing a silicon nitride film by selective oxidation, 5...Silicon nitride by plasma anodic oxidation. A silicon dioxide film created by oxidizing a film.
Claims (1)
する工程、前記第１の二酸化ケイ素膜上の所望の
部分に窒化ケイ素膜を形成する工程、前記窒化ケ
イ素膜をマスクとして前記半導体基板を選択的に
酸化し第２の二酸化ケイ素膜を形成する工程、前
記窒化ケイ素膜をプラズマ陽極酸化法により酸化
し、前記窒化ケイ素膜全てを第３の二酸化ケイ素
膜とする工程、前記第１の二酸化ケイ素膜及び前
記第３の二酸化ケイ素膜をフツ酸系エツチング液
による１回のエツチングにより除去し前記半導体
基板を選択的に露出させる工程を有することを特
徴とする半導体装置の製造方法。1. A step of forming a first silicon dioxide film on a semiconductor substrate, a step of forming a silicon nitride film on a desired portion of the first silicon dioxide film, and a step of selectively forming a silicon nitride film on the semiconductor substrate using the silicon nitride film as a mask. a step of oxidizing the silicon nitride film to form a second silicon dioxide film; a step of oxidizing the silicon nitride film by a plasma anodization method to make all the silicon nitride films into a third silicon dioxide film; a step of forming the first silicon dioxide film; and a step of selectively exposing the semiconductor substrate by removing the third silicon dioxide film by one-time etching with a hydrofluoric acid-based etching solution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9614181A JPS57211235A (en) | 1981-06-22 | 1981-06-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9614181A JPS57211235A (en) | 1981-06-22 | 1981-06-22 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57211235A JPS57211235A (en) | 1982-12-25 |
| JPH0318333B2 true JPH0318333B2 (en) | 1991-03-12 |
Family
ID=14157104
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9614181A Granted JPS57211235A (en) | 1981-06-22 | 1981-06-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57211235A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52112281A (en) * | 1976-03-17 | 1977-09-20 | Fujitsu Ltd | Manufacture of semiconductor |
-
1981
- 1981-06-22 JP JP9614181A patent/JPS57211235A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52112281A (en) * | 1976-03-17 | 1977-09-20 | Fujitsu Ltd | Manufacture of semiconductor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57211235A (en) | 1982-12-25 |
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