JPH03183215A - Decoder - Google Patents

Abstract

PURPOSE:To avoid the abnormality of an output control signal through a simple circuit configuration by constituting the logic circuit of a preceding stage of plural NAND gates, and constituting the logic circuit of a following stage of plural NOR gates, and using the rise characteristic of each gate. CONSTITUTION:The output control signals Y0 to Y7 are outputted respectively from the NOR gates 8 to 15 according to the bit pattern of each input signal C, B, A. In this case, the leading time of the NAND gates 4 to 7 that their outputs vary from 'L' level to 'H' level is short, and the trailing time of them that their outputs vary from 'H' level to 'L' level is long. As for the NOR gates 8 to 15 of the following stage, the leading time and the trailing time become contrary to those above mentioned. Accordingly, always after the outputs of the NAND gates 4 to 7 of the preceding stage rise up to 'H' level, the outputs of the NOR gates 8 to 15 of the following stage rise up to 'H' level. Accordingly, two or more output control signals Y0 to Y7 never become 'H' level at a time, or an unnecessary pulse is never generated in Y0 to Y7.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a decoder suitable for application to an address decoder or the like.

"Prior Art" As is well known, all logic circuits constructed by combining OR gates, AND gates, etc. can be constructed from NAND gates and NOR gates. Therefore, various logic circuits are constructed by combining only NAND gates or only NOR gates so as to be suitable for mass production. For example, an address decoder that generates an output control signal for selecting a specific memory or I10 port from the bit pattern of an address signal output to an address bus is usually constructed by connecting NOR gates in multiple stages.

``Problems to be Solved by the Invention'' However, as mentioned above, when an address decoder is configured simply by connecting NOR gates in multiple stages, unnecessary pulses called so-called whiskers may occur in the output control signal. More than one output control signal may become active at the same time, causing memory and
There was a risk that peripheral circuits such as 10 ports could not be controlled properly.

In order to avoid such a situation, each gate circuit has conventionally been controlled using a synchronous timing signal such as a clock signal, but this has the problem of complicating the circuit configuration.

This invention was made in view of the above-mentioned circumstances, and without using any synchronized timing signals such as clocks,
It is an object of the present invention to provide a decoder that can avoid abnormalities in output control signals with a simple circuit configuration.

``Means for Solving the Problems'' The present invention is characterized in that the front-stage logic circuit is composed of a plurality of NAND gates, and the rear-stage logic circuit is composed of a plurality of NOR gates.

"Function" In general, a NAND gate has a short rise time for its output to change from the "L" level to the "II" level, and the "I" level is short.
4" level to "L" level is characterized by a long fall time. Conversely, a NOR gate has a characteristic that a rise time is long and a fall time is short. Therefore, by adopting the above configuration, , the output of each NAND gate in the previous stage always rises before the output of each NAND gate in the latter stage rises, so two or more output control signals may become "H" level (active state) at the same time, or the output This avoids the occurrence of unnecessary pulses in the control signal.

"Embodiments" Hereinafter, embodiments ζ of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a three-man power eight-output decoder which is an embodiment of the present invention. In this figure, an input signal C is supplied to one input terminal of NAND gates 4 and 5 in the preceding stage, and after being inverted by an inverter I, is supplied to one input terminal of NAND gates 6 and 7 in the preceding stage. Ru. Furthermore, the human input signal B is supplied to the other input terminals of NAND gates 4 and 6, and after being inverted by inverter 2, is supplied to the other input terminals of NAND gates 5 and 7, respectively. Each output signal of these NAND gates 4 to 7 is
They are each supplied to one input terminal of the NOR gates 8 to I5 in the subsequent stage. In addition, the input signal A is the NOR gate 9, 11, 13
．． 15, and after being inverted by the inverter 3, the NOR gates 8, 10 . I 2,
14, respectively.

In the above configuration, depending on the bit pattern of each input signal C, B, and A, from the NOR gates 8 to 15 in the subsequent stage,
Output control signal Y as shown in FIG. ~Y7 are output respectively. In this case, the NAND gates 4 to 7 in the previous stage have a characteristic that the rise time for the output to change from the "L" level to the "H" level is short, and the fall time for the output to change from the "H" level to the "L" level is long. On the other hand, the NAND gates 8 to I5 in the subsequent stage have a long rise time and short fall time, so the outputs of the NAND gates 4 to 7 in the previous stage always rise to the "11" level. The output of the subsequent NOR gates 8 to 15 is “H”
It will rise to the level. Therefore, more than one output control signal Y. -I7 becomes the "I(" level) at the same time, and unnecessary pulses are not generated in the output control signal Y.-I7, making it possible to control the peripheral circuits normally.

"Effects of the Invention" As explained above, according to the present invention, the logic circuit at the front stage is composed of a plurality of NAND gates, the logic circuit at the latter stage is composed of a plurality of NOR gates, and the rising characteristics of each of these gates are utilized. By doing this, the output of each NAND gate in the previous stage always rises after the output of each NAND gate in the subsequent stage rises, so two or more output control signals may become active at the same time.
The advantage is that the occurrence of unnecessary pulses in the output control signal is avoided, and therefore, abnormalities in the output control signal can be avoided with a simple circuit configuration without using any synchronized timing signals such as clocks. It will be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
FIG. 2 is a diagram for explaining the operation of the same embodiment. 1-3...Inverter, 4-7...Nand gate, 8-15...Noah gate.

Claims (1)

[Claims] A decoder characterized in that a front-stage logic circuit is constructed of a plurality of NAND gates, and a rear-stage logic circuit is constructed of a plurality of NOR gates.