JPH03181069A - Digital signal processor - Google Patents

Abstract

PURPOSE:To surely demodulate a reproduced signal with a simple constitution by dividing the storage area of a memory circuit and successively cyclically assigning divided areas to respective blocks. CONSTITUTION:The storage area of a memory circuit 44 is divided to three or more areas B1PCM to B3PCM. At the time of recording, respective divided areas B1PCM to B3PCM are successively cyclically assigned to a digital signal input/output circuit 52, an error detecting and correcting circuit 56, and a recording signal generating circuit 60 in periods T1 to T3. At the time of reproducing, divided areas B1PCM to B3PCM are successively cyclically assigned to a reproduced signal processing circuit 58, the error detecting and correcting circuit 56, and the digital signal input/output circuit 52 in periods T1 to T3. Consequently, data is independently processed in each circuit block. Thus, the reproduced signal is surely demodulated by the simple constitution.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial field of application B. Overview of the invention C. Conventional technology Problems to be solved by the invention ErJ1 Means for solving the problem (Figs. 1, 2, and 5) (Gl-1) Effects of the Example (Gl-1-1) Audio signal processing (Gl-1-2
) Memory circuit and memory interface circuit (G2) Operation of the embodiment (G3> Effects of the embodiment (G4) Other embodiments H Effects of the invention A Field of industrial application The present invention relates to a digital signal processing device, for example, a digital audio It can be applied to magnetic recording and reproducing devices that record and reproduce signals.

B Summary of the Invention The first invention provides a digital signal processing device having a simple configuration by dividing the storage area of a memory circuit and sequentially and cyclically allocating each divided area to each circuit block. can be obtained.

Furthermore, a second invention is a digital signal processing device in which, in addition to the first invention, by switching the operation mode of each circuit block at a predetermined timing, it is possible to reliably perform continuous recording.

C. Prior Art Conventionally, some magnetic recording and reproducing apparatuses (hereinafter referred to as digital audio recorders) are capable of recording and reproducing digital audio signals using a rotating drum.

That is, during recording, the digital audio signal is divided into blocks at predetermined interleaving cycles, and interleaving processing is performed within the block.

Furthermore, a parity code (that is, an inner code and an outer code) for error detection and correction is generated for each block of the interleaved digital signal, and then converted into a recording signal and output to the magnetic head.

On the other hand, during playback, the playback signal is demodulated, error detection and correction is performed on a block-by-block basis, and then deinterleaved and output, contrary to the time of recording.

Since digital audio signals can be recorded and reproduced in this manner, deterioration in sound quality can be effectively avoided and audio signals can be recorded and reproduced with high density.

D Problems to be Solved by the Invention As described above, in a digital audio tape recorder that can record and play back audio signals while effectively avoiding sound quality deterioration, if continuous recording can be performed, the usability can be further improved. it is conceivable that.

However, in digital audio recorders, there is a problem in that it is difficult to perform smooth splice recording simply by switching the operation mode from playback mode to record mode.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a digital signal processing device that is capable of neatly splicing and recording.

E Means for Solving the Problem In order to solve the problem, in the first invention, the memory circuit 44 and the input digital data (Da
u) is divided into blocks at predetermined cycles T1, T2, T3, . . . and output to the memory circuit 44, and during reproduction, the reproduced digital data (D□) stored in the memory circuit 44 is read and output. The digital signal input/output circuit 52 generates an error detection and correction code for input digital data (DAU) stored in the memory circuit 44 during recording, outputs the error detection and correction code to the memory circuit 44, and during reproduction, An error detection and correction circuit 56 detects and corrects errors in the reproduced data D□ stored in the memory circuit 44 to generate reproduced digital data (D□), and outputs the reproduced digital data (DPI) to the memory circuit 44; At this time, the input digital data (Dau) stored in the memory circuit 44 and the error detection and correction code are converted into the recording signal Sll! The memory circuit 44 includes a recording signal generation circuit 60 that converts the data into the data D and outputs it, and a reproduction signal processing circuit 58 that demodulates the reproduction signal S□ and outputs the reproduction data D□ to the memory circuit 44 during reproduction. 3 storage areas
The areas B 1pcx , B 2PCM , B3 . . The period T
1, T2, T3, . . . are sequentially and cyclically allocated, and during reproduction, the reproduced signal processing circuit 58 and the error detection and correction circuit 5
6. In the digital signal input/output circuit 52, each divided area B lPCM , 82PCM, 83PCM is connected to the period T.
I, T2, T3, . . . are sequentially and cyclically allocated.

Furthermore, in the second invention, a memory circuit 44 and control data D. 1, and when recording, the input digital data (DAL+) is switched at a predetermined period T1, T2.
, T3, . . . into blocks and the memory circuit 44
A digital signal input/output circuit 52 reads and outputs the reproduced digital data (Drs) stored in the memory circuit 44 during playback, and a digital signal input/output circuit 52 which switches operations based on control data D Co)l and outputs the reproduced digital data (Drs) stored in the memory circuit 44 during playback. An error detection and correction code is generated for the human-powered digital data (Dau) stored in the circuit 44, and the error detection and correction code is sent to the memory circuit 4.
4, and at the time of playback, the playback data D stored in the memory circuit 44 is error-detected and corrected, and the playback digital data (
Dpm) and outputs the reproduced digital data (D□) to the memory circuit 44; Digital data (DA(+) and error detection and correction code are recorded as a signal 5RI
A recording signal generation circuit 60 that converts the signal into an IC and outputs it, and a reproduction signal processing circuit that switches operations based on control data D cost, demodulates the reproduction signal S□ during reproduction, and outputs reproduction data Drl to the memory circuit 44. 58, the memory circuit 44 has three storage areas B IPcN , B2
rc, 1, B3p.

During recording, the digital signal input/output circuit 52
, error detection and correction circuit 56, and recording signal generation circuit 60, each divided area B LpcM, B2PCM, B3FC-
are sequentially and cyclically allocated at cycles T1, T2, T3, . , 82FCM, B3PcN are sequentially and cyclically allocated at cycles T1, T2, T3, . . . to the memory circuit 44 and the digital signal input/output circuit 52.
, the error detection and correction circuit 56, the recording signal generation circuit 60, and the reproduction signal processing circuit 58, the control data D,. 8. switches from playback mode to recording mode, cycles T1, T2, T
After a predetermined period of time has elapsed based on 3, . . . , the reproducing operation is switched to the recording operation.

1 working storage area is 3M area B 1pc, l, B 2PCM, B
Each area BIPCM, B 2-eM, B is divided into 3 tcn or more and is divided into a digital signal input/output circuit 52, an error detection and correction circuit 56, and a recording signal generation circuit 60 during recording.
3PC- is sequentially and cyclically allocated at cycles T1, T2, T3, . . . , and during reproduction, the reproduction signal processing circuit 58,
Error detection and correction circuit 56, digital signal input/output circuit 52
Each area divided into Blpcw, B2□, B3. . By sequentially and cyclically allocating the signals at periods T1, T2, T3, etc., NTial can be easily obtained, and the transmission speed of the reproduced signal S0 can be maintained at a constant value, thereby simplifying the overall configuration. can be converted into

Furthermore, in addition to this, the memory circuit 44, digital signal input/output circuit 52, error detection and correction circuit 56, recording signal generation circuit 60, and reproduction signal processing circuit 58 are
3. If you switch from playback to record after a predetermined period of time has elapsed based on 3...., you will be able to reliably record continuous recording when you switch the entire operation from playback to record mode. I can do it.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

(G1) First Embodiment (Gl-1) Configuration of the Embodiment In FIG. 1, 1 indicates a digital audio recorder as a whole, which converts stereo audio signals into digital signals and records them.

That is, in the digital audio tape recorder 1, the input display circuit 2 having an arithmetic processing circuit configuration outputs operation data D3° in response to the operation of the operator. At the same time, the display on the display panel is switched based on predetermined control data.

As a result, in the digital audio tape recorder 1, the operating mode can be switched in response to the operation of the operator, and the operating state can be confirmed through the display on the display panel.

At the time of recording, the system control circuit 6 controls the operation data I)s.
It generates control data DCO, , based on ou, and outputs the control data I)co□ to the digital signal processing circuit 8, the mechanical control circuit 10, and the servo circuit 12.

Thereby, the system control circuit 6 is configured to switch the operation of the digital audio tape recorder 1 in response to the operation of the operator.

On the other hand, during playback, the system control circuit 6 outputs the operation data D,. 0, the control data D cost is generated based on the status byte data output from the digital signal processing circuit 8, and thereby the operation of the digital audio tape recorder 1 is switched in response to the operation of the operator. , the magnetic tape 15 is reproduced according to the recording format of the digital audio signal recorded on the magnetic tape 15.

Therefore, in this embodiment, by switching control data I mode and performs continuous recording.

Furthermore, during recording, the system control circuit 6 provides time information necessary for recording on the digital audio tape recorder 1;
Information DATA such as frame address information and back ID is outputted to the digital signal processing circuit 8 in an interleave period, and thereby the time information, frame address information, etc.
Audio signals can be recorded based on information DATA such as a back ID.

The mechanical control circuit 10 drives and controls the tape cassette loading/unloading mechanism, the magnetic tape loading mechanism, etc. based on the control data DeoNt output from the system control circuit 6.

On the other hand, the servo circuit 12 uses control data I) cos
The reel motor 16 is driven based on y, thereby rotating the reel of a magnetic tape cassette (not shown) at a predetermined speed.

Further, the servo circuit 12 generates a switching pulse signal SWP whose signal level changes at the cycle of one revolution of the rotary drum 20, and outputs control data D,. 1, the drum motor 22 is driven so that the phase of the switching pulse signal SWP becomes a predetermined phase with respect to the rotating drum reference signal DREF.

Here, the rotating drum reference signal DREF is set to the long-time mode (
(hereinafter referred to as LP mode) and standard time mode (hereinafter referred to as S
P mode) 60 C11sec) and 3
The reference signal has a duty ratio of 50% and is repeated at an interleave period of 0 (a+5ec).

As a result, the servo circuit 12 drives the drum motor 22 so that the rotary drum 20 rotates once in one interleave period when recording and when reproducing the magnetic tape 15 recorded in the SF' mode. When reproducing the magnetic tape 15 recorded in the SP mode, the drum motor 22 is driven at twice the rotational speed at the time of recording.

Furthermore, the servo circuit 12 is configured such that the magnetic tape 15 is
The capstan motor 26 is driven so as to travel two track pitches in an interleave period, thereby making it possible to sequentially record recording tracks in a format standardized for the digital audio tape recorder.

On the other hand, the servo circuit 12 drives the capstan motor 26 so that the magnetic tape 15 travels two track pitches in one interleave period, as in the case of reproduction and recording. Tracking control is performed based on the output tracking error signal.

That is, when reproducing a magnetic tape recorded in SP mode, the magnetic tape 15 and rotating drum 2 are
0 is driven, each magnetic head 28A and 28
A to ensure that B scans the corresponding recording track.
TF (automatic track findi)
ng) Tracking control is performed using a tracking servo (hereinafter referred to as ATF servo) method.

On the other hand, when playing back a magnetic tape recorded in the LP mode, the rotating drum 20 rotates at twice the rotational speed during recording, so when each magnetic head 28A and 28B scans twice, it only covers two track pitches. A magnetic tape 15 runs.

Therefore, the servo circuit 12 controls the capstan motor 26 (hereinafter referred to as NT servo) so that the amount of tracking error gradually changes based on the output signal of the tracking control circuit 24, thereby controlling the magnetic head 28.
A and 28B ensure that the corresponding recording tracks are scanned twice each.

Thus, in this embodiment, when reproducing the magnetic tape 15 recorded in the LP mode, the rotation speed of the rotary drum 20 is set to twice that of recording, so that the reproduction signal SmF is transmitted twice from each recording track. At the same time, the transmission speed of the reproduced signal S□ is maintained at twice the transmission speed of the recording signal, thereby obtaining the reproduced signal SIF with the same transmission speed in the SP and LP modes, and the digital signal processing circuit 8 and The structure of the recording/reproducing amplifier circuit 32 is simplified.

Therefore, when playing back the magnetic tape 15 in SP mode, the digital audio signal can be played back by sequentially processing and demodulating the re-outgoing signal S□, whereas when playing back the magnetic tape 15 in LP mode, it is possible to play back the digital audio signal twice. A digital audio signal can be reproduced by selectively processing the reproduced signal S□ that is repeated at a time.

On the other hand, in continuous recording, the servo circuit ■2
Regardless of the switching of the operation mode, the drum motor 22 and capstan motor 26 are driven under the conditions of recording and reproducing in the SP mode, thereby driving the capstan motor 26 and the rotating drum 20 at a constant speed, and smoothly It is designed so that it can be recorded continuously.

(Gl-1-1) Audio signal processing The audio signal conversion circuit 30 is composed of an analog-to-digital conversion circuit, a digital-to-analog conversion circuit, and a digital filter circuit, and converts the audio signal SIN into a digital audio signal D1 during recording. Digital signal processing circuit 8
Output to.

On the other hand, during playback, the audio signal conversion circuit 30
The digital audio signal DAt+ output from the digital signal processing circuit 8 is converted into an analog signal set+t
Convert and output.

The digital signal processing circuit 8 receives control data D during recording.
Based on C01, digital audio signal, υ
After converting into a recording signal 5IIIC, the recording signal S,
c to the magnetic head 28A via the recording/reproducing amplifier circuit 32.
and 28B, whereby the digital audio signal D1 is sequentially transferred to the magnetic tape 15 in a format standardized for the digital audio recorder.
to be recorded.

On the other hand, during playback, the digital signal processing circuit 8 switches its operation based on the control data D C0NT, thereby converting the playback signal S□ into the digital audio signal DAt.
+ and output to the audio signal conversion circuit 30.

As a result, the reproduced signal S1 output from the magnetic heads 28A and 28B is demodulated to produce an audio signal S. . It has been made so that it can be played.

As shown in FIG. 2, in the digital signal processing circuit 8, the data input/output circuit 40 inputs the control data DC, . Store in area.

Furthermore, the data input/output circuit 40 provides time information, frame address information, backrD, etc. necessary for generating subcode data in the subcode data area and main data area during recording.
input data such as DATA from the system control circuit 6,
The memory circuit 4 via the memory interface circuit 42
4 in a predetermined area.

On the other hand, during reproduction, the data input/output circuit 40 outputs the demodulated subcode data stored in the memory circuit 44 to the system control circuit 6, thereby
Information such as the recording format of No. 5 (ie, consisting of status byte data, etc.) is sent to the system control circuit 6.

The input/output circuit 46 extracts a clock signal from the AES/EBU format digital audio signal RX input to the digital audio tape recorder 1, and converts the digital audio signal RX into a predetermined format digital audio signal based on the clock signal. and outputs it to the digital signal input/output circuit 52.

As a result, the digital audio tape recorder 1
In this case, the audio signal SIN consisting of an analog signal is
Instead, it is possible to record digital audio signals RX in AES/EBU format.

Further, the input/output circuit 46 includes the digital signal input/output circuit 5
The digital audio signal output from 2 is converted into AES/
The digital audio signal TX is converted into an EBU format digital audio signal TX, thereby making it possible to send out an AES/EBU format digital audio signal TX in addition to the analog audio signal s out.

The digital signal input/output circuit 52 receives a data bus D from the memory circuit 44 via the memory interface circuit 42.
control data DCo output to the T port; 4. Enter
As a result, the operation is switched at a predetermined tying based on the control data I)co, 4t.

Furthermore, the digital signal input/output circuit 52 sequentially counts a predetermined clock signal with a built-in counter circuit, and generates a rotating drum reference signal with an interleave period of 60 [5ec] and 30 [eisec] in the LP and SP modes, respectively. Create DREF.

Further, during recording, the digital signal input/output circuit 52 selectively inputs the digital audio signal D0 output from the input/output circuit 46 or the audio signal conversion circuit 30, and converts the digital audio signal based on the count value of the counter circuit. Create blocks at interleave intervals.

At this time, the digital signal input/output circuit 52 sequentially outputs the digital audio signal to the memory interface circuit 42 based on the count value of the counter circuit, thereby interleaving the digital audio signal divided into blocks for each block. to generate input audio data.

On the other hand, during playback, the digital signal input/output circuit 52 sequentially inputs the playback audio data stored in the memory circuit 44 via the memory interface circuit 42, and at this time, the corresponding By inputting reproduced audio data, the reproduced audio data is subjected to deinterleaving processing and converted into a digital audio signal, and then outputted to the input/output circuit 46 and the audio signal conversion circuit 30.

At this time, the digital signal input/output circuit 52 performs an interpolation calculation on the reproduced audio data whose error could not be corrected based on the error correction result stored in the memory circuit 44 and outputs the result.

Furthermore, during reproduction, the digital signal input/output circuit 52 outputs predetermined set data to the memory interface circuit 44, thereby storing the reproduced data DP in a predetermined area of the memory circuit 44 allocated for storing the error detection result of the C1 code.
A flag indicating that there is an error in I is set, and the area is set to the initial state.

The error detection and correction circuit 56 is connected to the digital signal input/output circuit 5.
2, the data bus DT@U3 is connected from the memory circuit 44.
Inputs the control data Dc08T outputted to the control data D, and thereby controls the control data D. 1, the operation is switched at a predetermined timing.

At this time, the error detection and correction circuit 56 sequentially loads the input audio data stored in the memory circuit 44 via the memory interface circuit 42 during recording, and generates a parity consisting of an inner code and an outer code for error correction in block units. After generating the code (ie, consisting of the C1 code and C2 code), the parity code is stored in the memory circuit 44.

At the same time, the error detection and correction circuit 56 receives data DATA such as time information, frame address information, and back ID from the memory circuit 44, generates a parity code for the serve code data to be recorded on the magnetic tape 15, and stores it in the memory. It is stored in the circuit 44.

On the other hand, during playback, the memory interface circuit 42
The playback data D□ stored in the memory circuit 44 via
are sequentially loaded, error detection and error correction are performed on the reproduced data DPI, and the resultant data is stored in the memory circuit 44.

That is, the error detection and correction circuit 56 stores the reproduction audio data in advance in the memory circuit 4 among the reproduction data D□.
Based on the error detection result using the 01 code stored in 4, the error is corrected using the C1 code, and then the error detection and correction process using the C2 code, C1 code, and C2 code is sequentially repeated. The error correction process is repeated twice in total to reduce bit errors.

At this time, the error detection and correction circuit 56 stores error correction results (hereinafter referred to as C1 and C2 demodulation flags) in the memory circuit 44 for each C1 code and C2 code.

In this manner, the digital signal input/output circuit 52 uses the memory circuit 4 based on the C1 demodulation and C2 demodulation flags.
By interpolating and outputting the playback data DPI+ of a predetermined area stored in 4, playback audio data can be reliably obtained.

On the other hand, in the subcode data recorded in the subdata area of the reproduced data DP11, the C
1 code error correction is performed, and the correction result (hereinafter referred to as the C1 demodulation flag, as in the case of reproduced audio data) is stored in a predetermined area of the memory circuit 44.

Therefore, the data input/output circuit 40 can reliably detect only error-free data of the subcode recorded in the subdata area based on the C1 demodulation flag.

The recording signal generation circuit 60 is a digital signal input/output circuit 5
2, the data bus DTmus is connected from the memory circuit 44.
Control data output to D eON? is input, thereby switching the operation at a predetermined timing according to the control data DCONT.

That is, during recording, the input audio data, parity code, time information, frame address information, back ID, etc. stored in the memory circuit 44 are sequentially loaded and 5-io modulated.

Further, the recording signal generation circuit 60 converts the modulation signal into serial data, adds a pilot signal for ATF tracking control, a synchronization signal, etc. to generate a recording signal sate, and generates the recording signal S□. recording/reproducing amplification circuit 32
The signal is outputted to the magnetic heads 28A and 28B via the magnetic heads 28A and 28B.

As a result, it is possible to obtain a recording signal 5IItc modulated with a parity code etc. after being interleaved in units of blocks via the recording signal generation circuit 60, and output the recording signal S0° to the magnetic heads 28A and 28B. By doing so, digital audio signals can be sequentially recorded on the magnetic tape 15.

At this time, the recording signal generation circuit 60 uses a predetermined clock signal as a reference, and uses a transmission rate of 4 in the LP and SP modes.
．． 704 (Mbps) and 9.408 (Mbps
] Modulation signal S11! . According to the running speed of the rotating drum 20 and the magnetic tape 15, digital audio signals are sequentially recorded in a format standardized in the LP mode and the SP mode.

On the other hand, during reproduction, the recording signal generation circuit 60 generates the recording signal S□ based on the control data DCONT. stop generation.

In the playback mode, the clock signal extraction circuit 62 extracts a playback clock signal from the playback signal S□ obtained via the recording/playback amplification circuit 32, and sends the playback clock signal together with the playback signal S1 to the playback signal processing circuit 5. Output.

The reproduction signal processing circuit 58 receives control data D,. In contrast, during reproduction, the reproduction signal S□ is demodulated by 10-8 based on the reproduction clock signal, and the resulting reproduction data D□ is sent to the memory circuit 4.
Output to 4.

Furthermore, when outputting the reproduced data D□ to the memory circuit 44, the reproduced signal processing circuit 58 detects errors in the reproduced audio data and pack data using the C1 code.

At this time, the repeat signal processing circuit 58 sequentially resets the predetermined areas set to the initial state by the digital signal input circuit 52 based on the error detection result, and stores the error detection result using the 01 code in the memory circuit 44. Store.

Furthermore, when reproducing the magnetic tape 15 in the LP mode, the reproduction signal processing circuit 58 outputs one block of reproduction signal 5IIF which is repeatedly output twice.
By demodulating using the method disclosed in Publication No. 1, it is possible to reliably demodulate the reproduced data D□.

That is, the reproduced data D□ obtained by demodulating the reproduced signal SIF and repeating it twice is obtained, and among the reproduced data D□,
The first reproduction data DPI is sequentially stored in the memory circuit 44 together with the error detection results.

Further, the error detection result stored in the memory circuit 44,
Based on the error detection result of the subsequently obtained reproduced data DPI, the first reproduced data D□ already stored in the memory circuit 44 is updated with the second reproduced data DPI.

Based on the error detection result, the error-free reproduction data D□ out of the repeatedly obtained reproduction data D9 is selectively stored in the memory circuit 44 (hereinafter referred to as NT demodulation), and the probability of error occurrence during reproduction is determined. Efforts are being made to reduce this.

Of the reproduced data D□ demodulated in this way, the reproduced audio data is first stored in the memory circuit 44, then error-corrected in the error detection and correction circuit 56, and sequentially transmitted to the digital signal input/output circuit 52 as needed. Accordingly, interpolation calculation processing is performed and output, whereby a digital audio signal can be reproduced.

On the other hand, among the demodulated reproduced data D□, the subcode data is stored in the memory circuit 44 for -1 days, and then
Errors are corrected by the error detection and correction circuit 56 and output to the system control circuit 6 via the data input/output circuit 40, thereby making it possible to detect desired information as necessary. It is designed so that it can be played according to the format.

(Gl-1-2) Memory circuit and memory interface circuit As shown in FIG.
Blpcx-82F--,8
It is divided into 3 PCMs, and the input and playback audio data and the C1 and C2 codes of the input and playback audio data are stored in block units.

Furthermore, the memory circuit 44 divides the remaining 64 (KB) memory area into banks, and stores the packed data of the sub data area and its C1 code in three banks Blrw, 82PK, and B3rx in block units. It is made to be.

On the other hand, four banks B lr , B2P , B
3P and 84F are each block units, and when playing, C
1 demodulation and C2 demodulation flags are stored.

Three more banks Blsum, B2□1, B55us
is allocated to an area for storing subcode data in the main data area and subdata area in blocks, and a portion of the remaining area BCONT contains control data D,
. Of NY, mode byte data representing the recording/reproducing mode of the digital signal processing circuit 8, etc. is stored.

The memory interface circuit 42 has an address bus AD.
mus and the data bus DTsus, the digital signal input/output circuit 52, which is the main processing circuit of the digital signal processing circuit 8, the data input/output circuit 40, the error detection and correction circuit (ECC) 56, the reproduced signal processing circuit 58, and It is connected to the recording signal generation circuit 60 and to the memory circuit 44 via a dedicated bus BU.

Thereby, the memory interface circuit 42 connects to the data bus AD. The data output to the memory circuit 44 is stored in a predetermined bank or recording area of the memory circuit 44, and the data stored in the memory circuit 44 is output to the data bus ADmus.

At this time, the memory interface circuit 42 receives information DATA such as time information, frame address information, and back ■D.
are stored in respective predetermined areas to generate subcode data and subcode data in the main data area, while mode byte data of the control data I) coNt is stored in the control data storage area B C0NT of the memory circuit 44.
Store in.

Further, the memory interface circuit 42 switches the operation based on the control data D C0NT, and outputs the control data DCoN to the data bus AD□3 at a predetermined timing, thereby switching the operation of the digital signal processing circuit 8. It is done like this.

That is, as shown in FIG. 4, during playback, the memory interface circuit 42 inputs and outputs data by sequentially switching banks cyclically at an interleave cycle, thereby generating the rotating drum reference signal DREF (FIG. 4). The reproduced signal 5IF (FIG. 4(B)) is processed in synchronization with (A)).

Note that here symbols A and B respectively indicate the magnetic head 28A.
and 28B, and in this embodiment, the 90 degree winding is the angle of the magnetic tape 1.
Magnetic heads 28A and 28B with different azimuth angles are mounted on a rotating drum 20 with a diameter of 30 (*m) and a
Since they are mounted at angular intervals of 80 degrees, each magnetic head 28A and 28
A reproduced signal SRF can be obtained from B.

The memory interface circuit 42 connects the first banks Blrcx, Blsam,
Bl□ and Bl are assigned to the processing of the reproduction signal processing circuit 58 (represented by symbol RF+s), and the second bank B2. Initialization processing of the digital signal input/output circuit 52 (symbol NGW
).

That is, the memory interface circuit 42 outputs the reproduced audio data and the C of the reproduced audio data out of the reproduced data D□ output from the reproduced signal processing circuit 58.
1 and C2 code I) pc+a to the first bank BIPCM
In contrast, the back data of the L sub data area and its C1 code D□ are stored in the bank Bl□ (Fig. 4 (D)). Code data D 511m in bank B1
g□ (Fig. 4 (E) and (F)).

Furthermore, the bank BIF initialized by the digital signal input/output circuit 52 one interleaving period ago is loaded with the C1 demodulation flag F 31111 and FCI (corresponding to back data and reproduced audio data, respectively) detected by the reproduced signal processing circuit 58. Figure 4 CG) and (H))
, 2 bank B2. is initialized by the digital signal input/output circuit 52.

In the interleaving period T2 that follows, the second
The banks B2P□, B25us, B2□ and B2F are processed by the reproduction signal processing circuit 58, and the third bank B3. are assigned to the initialization processing of the digital signal input/output circuit 52, and the first banks BIPCM, B1□, and BIF are assigned to the processing of the error detection and correction circuit 56 (represented by the symbol ECC).

That is, the second bank 82PCM , B 2sum ,
In B2PII, B2F and the third bank 83F, the first bank B lP in the interleaving period T1
CM, B 1sus, B lrw, Blp and 2nd
Data is input in the same manner as in bank 82F.

On the other hand, in the first bank Blpcx%BIPII, the reproduced data I)re is sequentially output together with the C1 demodulation flag of the bank BIP to the error detection and correction circuit 56, thereby repeating error detection and correction of the reproduced data D□.

Furthermore, the first bank BIF. , updates the playback data D□ of BIPII with the error-corrected playback data DPI, and updates the initialized area of the bank Bit with the C1 demodulation flag F'st++s and FCI of the resulting back data and playback audio data. Bank BIF
C2 of the playback audio data is stored in the remaining uninitialized area of
A demodulation flag F0 is stored ((1) in FIG. 4).

In the subsequent interleaving period T3, the fourth bank B4F is assigned to the initialization process of the digital signal input/output circuit 52, and the third bank 83PCM, , B
3sum, B3PIl, and B3p are assigned to the processing of the reproduced signal processing circuit 58.

Furthermore, second banks 82PCM, B2□ and B2. is assigned to the processing of the error detection and correction circuit 56, and the first bank B
1 pcpi , B 1-us , , B IPl[, B
l, is assigned to the output processing (represented by symbol DAaot) of the digital signal input/output circuit 52 and the data input/output circuit 40.

In this way, in the reproduced audio data of the reproduced data D□, three banks B are
1pcx, B2PCM, B3rcx, and after error correction, it is converted into a digital audio signal D1 by the digital signal input/output circuit 52, and at this time, it is stored in the corresponding banks BIF, B2p, B3F.
, 84F, interpolation calculation processing is performed based on the error detection and correction results stored in 84F.

Therefore, in the playback signal processing circuit 58 that performs input processing, the error detection and correction circuit 56 that performs error correction processing, and the digital signal input/output circuit 52 that performs output processing, the playback audio data is independently and sequentially chronologically processed for each circuit block. can be processed.

Therefore, even if NT demodulation is performed in the reproduced signal processing circuit 58, NT demodulation can be performed without affecting input processing, error correction processing, and output processing, and thus NT
The reproduced data D□ can be reliably demodulated by the amount of demodulation.

Therefore, the transmission speed of the reproduced signal S□ is changed to SP and LP accordingly.
The clock signal extraction circuit 62, recording/
The configurations of the regenerative amplifier circuit 32 and the regenerative signal processing circuit 58 can be simplified.

Actually, in the NT servo that performs NT demodulation, when each magnetic head 28A and 28B scans twice, the magnetic tape 15 travels two recording tracks, so the signal level of the reproduced signal S changes in a triangular wave shape, and the ATF There is a characteristic that the SN ratio of the reproduced signal S1 is partially degraded compared to the case of servo.

Therefore, as in this embodiment, if N'rvtm, SN
The occurrence of errors caused by a partial decrease in the ratio can be reduced, and the reproduced data D□ can be reliably demodulated.

On the other hand, the bank data in the sub data area, the main data area, and the sub code data D! in the sub data area. Similarly, in 111, the reproduced signal processing circuit 58 performs input processing by being cyclically stored in three banks Bl□ and Blsum, B2□ and B25us, B3□ and B3g+++s in one interleave period. , the error detection and correction circuit 56 that performs error correction processing, and the data input/output circuit 40 that performs output processing can independently perform time-series processing in block units, thereby detecting recorded information, etc. with a simple configuration as a whole. I can do it.

Similarly, demodulation flags F 5IJI , F C1 and FCl
, a reproduced signal processing circuit 58 which is sequentially stored cyclically in four banks BIP 5B2P, B3F, and B4F in one interleave period and performs input processing;
The error detection and correction circuit 56 that performs error correction processing and the digital signal input/output circuit 52 that performs initialization processing and output processing can perform processing independently for each circuit block.

On the other hand, the memory interface circuit 42 processes data by sequentially and cyclically switching banks at an interleave period, similarly to when recording and reproducing.

That is, the memory interface circuit 42 sequentially transfers the input audio data output from the digital signal input/output circuit 52 to the first bank B I PCM, the second bank B2rcx, the third bank 83PCM, the first bank BIPCM, etc. ..., while the data output from the data input/output circuit 40 is stored in the corresponding first
banks Blrx and B 1 sum , second banks B2□ and B25ui, third banks B3PII and B
3som, first bank B1□ and B1sum,
It is stored cyclically in...

Furthermore, the memory interface circuit 42 outputs the data stored in each bank to the error detection and correction circuit 56, and at this time, the data stored in each bank are sequentially output to the first bank BIFCM, B1□, and B1.
3u1, second bank B2rcx, B2PK and 82
sun-third bank 83PCM%B3□ and B531
11% first bank B12. , BIPm [and Bls
A code for error detection and correction is stored cyclically in um, . . . .

Subsequently, the memory interface circuit 42 outputs the data stored in each bank together with an error detection and correction code to the recording signal generation circuit 60, and at this time, the data stored in the first bank B are sequentially outputted to the recording signal generation circuit 60.
1 de CN, B I PK and B1. I, , second bank 82 PCM , B 2 ,* and B2MUm, third bank B3a. , B3□ and B3sum, first bank B lPCM , B IPI [and Blsum,
Outputs the data stored in...

In this way, even during recording, since banks are sequentially switched, the digital signal input/output circuit 52 and data input/output circuit 4o that perform input processing, the error detection and correction circuit 56 that performs error correction processing, and the recording signal generation circuit 60 that performs output processing. , it is possible to process data independently and in time series for each circuit block, and as a result, the recording signal S can be processed with a simple configuration as a whole.
RtC can be generated.

On the other hand, as shown in Figure 5, in continuous recording, the circulation order of banks is kept the same as during recording and playback, and the circuit blocks that are the processing targets of each bank are processed together with the operation of each circuit block. By sequentially switching from time t1, continuous recording can be performed smoothly.

In the digital audio tape recorder I, the SP mode in which the drum motor 22 and capstan motor 26 are driven at the same speed during recording and reproduction is a mode in which continuous recording can be performed.

Since splice recording occurs when the operation mode is switched from playback mode to record mode, the digital audio tape recorder 1 first operates in playback mode and outputs the rotating drum reference signal DREF (see FIG. 5). The reproduction signal 5IF (FIG. 5(B)) is set to be obtained every l interleaving period in synchronization with A)>.

Therefore, control data DCON? The mode byte (FIG. 5(C)) is set to the reproduction mode, and correspondingly the operation mode of the memory interface circuit 42 (FIG. 5(D)) is set to the playback mode.
), the operating mode of the digital signal input/output circuit 52 (FIG. 5(E)), the operating mode of the data input/output circuit 40 (FIG. 5(F)), and the operating mode of the error detection and correction circuit 56 (FIG. 5(F)). G)), the operation mode of the recording signal generation circuit 6o and the reproduction signal processing circuit 58 (FIG. 5(H)) are all maintained in the reproduction mode.

As a result, in the reproduced signal S0 of the frame addresses sequentially indicated by numbers 1.2, . . ., the memory circuit F11
Banks of 144 B I FCM, 82 PCM and 8
3 are sequentially and cyclically stored in the PCM (Fig. 5 (I)),
The signal is delayed by two interleaving periods and converted into a digital audio signal, and correspondingly, frame data DADT (FIG. 5 (J)) is obtained as one of the subcode data via the data input/output circuit 40. be able to.

In this state, when the control data Dcost output from the system control circuit 6 is switched to the recording mode at time tl, the memory interface circuit 42, digital signal input/output circuit 52, and data input/output circuit 40 are output in the following interframe period. At the rising time t2, the mode is switched to the recording mode.

Point L at the rising edge of a further interframe cycle
3, the error detection 1r positive circuit 56 switches to the recording mode.

Therefore, the interframe period T from time t2 to time t3
In step 7, the recording signal generation circuit 6o and the reproduction signal processing circuit 58 are kept in the reproduction mode, and the memory interface circuit 42, the digital signal input/output circuit 52, and the data input/output circuit 4o are kept in the recording mode.

At this time, the memory interface circuit 42 transmits the reproduced audio data in the previous interframe period Stores the input audio data output from.

Similarly, the memory interface circuit 42 stores the time information etc. output from the data input/output circuit 4o in the bank in the order in which the subcode data is stored in the frame period T7.

In addition, in the system control circuit 6, the frame data ADDT (FIG. 5 (K)) obtained by adding the value 5 to the frame data DADT obtained at the interframe period T6 is
The data is outputted to the data input/output circuit 40 at the frame period T7.

Therefore, in the subcode bank, frame data with a value of 6 is stored in the frame period XIIT7.

Furthermore, the memory interface circuit 42 sets the bank 82FCM that has undergone error correction processing in the previous interframe period T6 and outputs the playback audio data in the frame period T7 as a processing target of the playback signal processing circuit 58.

Similarly, the memory interface circuit 42 also controls the bank B 1p for audio data processing for other banks.
Similarly to cH, B 2pcn and B 3re, the processing target is switched and data is input and output, respectively.

On the other hand, in bank 83PCM, the memory interface circuit 42 retains the error detection and correction circuit 56 in the original order as a processing target, and thereby performs error detection and correction on the reproduced audio data D stored at the interframe period T6. It is designed to be processed.

On the other hand, at time t4 after one frame period has passed, the error detection and correction circuit 56 switches to the recording mode, so the memory interface circuit 42 performs The audio data stored in the bank BIFCM is sequentially output to the error detection and correction circuit 56 and the C1 and C2 codes are stored in the memory circuit 44 (represented by symbol P), and are output from the digital signal input/output circuit 52. The input audio data is stored in bank B2pc, and the reproduced audio data output from the reproduced signal processing circuit 58 is stored in bank B3PC.

Furthermore, the memory interface circuit 42 also connects the other banks to the bank B I P for audio data processing.
Similarly to CM, 82PCM, B 3pcn, the processing target and data input/output operation are switched.

On the other hand, at time point t5 after one frame cycle has passed, the recording signal processing circuit 60 and the reproduction signal processing circuit 58 switch to the recording mode, thereby changing the operation mode of the entire digital signal processing circuit 8 to the recording mode. Switch to .

As a result, the memory interface circuit 42 outputs the audio data stored in the bank Bl-CM together with the C1 and C2 codes and the like to the recording signal generation circuit 60 at the interframe period T9.

Furthermore, the memory interface circuit 42 stores input audio data banks B 1 raw, B 2 PCM,
The banks other than B5Pc are switched in the same manner, and following the recording track in which the frame data of value 5 is recorded, the recording signal 5 with frame data of value 6 is recorded.
llIC (indicated by diagonal lines in FIG. 5(A)) can be recorded.

Furthermore, the memory interface circuit 42 sequentially outputs the audio data stored in the bank B2rcx to the error detection and correction circuit 56 at the interframe period T9.
1 and C2 codes, whereas bank 83PC1
1 stores audio data output from the digital signal input/output circuit 52.

By repeating the processing in the sequential recording mode in successive frame periods in this way, the frame data is continuous and the audio signal can be recorded in a spliced manner without switching the reference signal such as the rotating drum reference signal DREF.

In fact, in this type of digital audio chip recorder, during playback, data is processed in the order from the playback signal processing circuit 58 to the error detection and correction circuit 56, whereas during recording, the data is processed from the error detection and correction circuit 56 to the recording signal processing circuit. Since the flow of data is reversed in the order of 60, if the memory circuit 44 is used without being divided into banks, immediately after switching from playback to recording, when the rotating drum is rotated at a constant rotation speed, recording will not be possible. A situation occurs in which the signal generation cannot be done in time.

Therefore, in the case of continuous recording, it is necessary to change the scanning timing of the magnetic head immediately after switching from playback to recording, which makes it difficult to perform smooth continuous recording.

However, as long as the data is processed in the memory circuit 44*bank in this way and the data to be recorded is already processed in the error detection and correction circuit 56 one interleaving cycle before,
Immediately after switching from playback to recording, a recording signal can be outputted immediately, and thus smooth continuous recording can be performed.

Note that when the continuous recording is completed, the digital signal processing circuit 8 operates the memory interface circuit 42, the data input/output circuit 40, the digital signal input/output circuit 52, and the recording The signal generation circuit 60, reproduction signal processing circuit 58, and error detection and correction circuit 56 sequentially switch their operations after a predetermined period of time has elapsed, and are configured to quickly switch to the reproduction mode.

(G2) Operation of the embodiment In the above configuration, in the digital signal processing circuit 8, the memory interface circuit 42, the data input/output circuit 40, the digital signal input/output circuit 52, the reproduction signal processing circuit 58, the recording signal generation circuit 60, and the error The detection and correction circuit 56 detects the control data D stored in the memory circuit 44 at a predetermined timing. 1, thereby switching the operation based on the control data I)co)lt.

That is, during recording, the audio signal conversion circuit 3
The digital audio signal inputted through 0 is divided into blocks at an interleaving period, and then subjected to interleaving processing and converted into input audio data.

The input audio data is stored in a predetermined bank of the memory circuit 44, and at this time, the banks are sequentially switched at an interleaving period and stored cyclically.

The input audio data stored in the memory circuit 44 is
A parity code is created by the error detection and correction circuit 56. At this time, banks are sequentially and cyclically switched, and parity codes are created sequentially and time-sequentially for each block of input audio data stored in each bank.

Once the parity code is generated, the input audio data is outputted to the recording signal generation circuit 60 in the subsequent interleave cycle, where it is converted into a recording signal 5IItc and sequentially outputted to the magnetic heads 28A and 28B, thus being recorded on the magnetic tape 15. can record digital audio signals.

On the other hand, during reproduction, the recording signal generation circuit 60
stops operating, and the reproduced signal processing circuit 58 starts operating.

That is, the reproduction signal S□ obtained via the magnetic heads 28A and 28B is demodulated by the reproduction signal processing circuit 58 after the reproduction clock signal is extracted by the clock signal extraction circuit 62.

The demodulated playback data DPI is temporarily stored in the memory circuit 44, and at this time, banks are sequentially switched to sequentially store the playback data D□ block by block in time series.

The reproduced data stored in the memory circuit 44 is sequentially outputted to the error detection and correction circuit 56, where it is subjected to error detection and correction, and then stored in the memory circuit 44 again. Stored.

The error-detected and corrected reproduced data is outputted via the digital signal input/output circuit 53 in the subsequent interleave cycle, thereby making it possible to reproduce the digital audio signal.

At this time, at a predetermined timing, the control data Del), l
When t switches to the recording mode, the memory interface circuit 42 switches to the recording mode from the immediately following interleave cycle, and processes the processing target of each bank while maintaining the switching order of each bank of the memory circuit 44 in the same manner as during playback. Switch.

At the same time, the digital signal input/output circuit 52 and the data input/output circuit 40 switch to the recording mode and start processing input audio data for continuous recording.

Subsequently, with a delay of one inter-remap period, the error detection and correction circuit 56 switches to the recording mode, and generates a parity code for the data processed by the digital signal input/output circuit 52 and the data input/output circuit 40.

Further, with a delay of one interleaving period, the recording signal generation circuit 60 and the reproduction signal processing circuit 58 switch to the recording mode, and thereby the recording data pre-processed by the error detection and correction circuit 56 becomes the recording signal S0°. converted and recorded.

(G3) Effects of the Embodiment According to the above configuration, by allocating a bank to each circuit block and switching the bank at an interleaving period, the reproduced signal S□ repeatedly obtained is processed and the reproduced data DPI is selectively transferred. can be obtained, thus N
By performing T demodulation, it is possible to reliably obtain reproduced data D□.

Furthermore, in addition to this, by sequentially switching the operation of each circuit block at a predetermined timing, reliable continuous recording can be achieved.

(G4) Other Embodiments In the above-described embodiments, the case where three banks were provided was described, but the present invention is not limited to this, and three or more banks may be provided as necessary.

Furthermore, in the above embodiment, the magnetic heads 28A and 28B are mounted on the rotating drum 20 with a drum diameter of 30 [open].
Although the case has been described in which the drums are arranged at angular intervals of 100 degrees, the present invention is not limited to this.
It can be widely applied when using a rotating drum of 5 (am) or 20 (m+Il).

Further, in the above-described embodiment, a case was described in which an audio signal was recorded and played back, but the present invention is not limited to this, and can be applied to an external storage device of an arithmetic processing unit to input/output between the arithmetic processing unit and the arithmetic processing unit. It can be widely applied when recording and reproducing data.

Effects of the H invention As described above, according to the first invention, by dividing and allocating a storage area to each circuit block and sequentially switching the area at a predetermined period, data can be processed independently in each circuit block. This makes it possible to obtain a digital signal processing device that can reliably demodulate the reproduced signal.

Furthermore, according to the second invention, in addition to this, by sequentially switching each circuit block from the reproduction operation to the recording operation, it is possible to obtain a digital signal processing device that can reliably perform continuous recording.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a digital audio chip recorder according to an embodiment of the present invention, FIG. 2 is a block diagram showing a digital signal processing circuit, FIG. 3 is a route diagram for explaining memory space division, and FIG. 4 5 is a timing chart for explaining bank switching, and FIG. 5 is a timing chart for explaining continuous recording. l...Digital audio recorder,
6... System control circuit, 15... Magnetic tape, 20... Rotating drum, 28A, 28
B...Magnetic head, 44...Memory circuit, 52...Digital signal input/output circuit, 56
. . . error detection and correction circuit, 58 . . . reproduction signal processing circuit, 6o . . . recording signal generation circuit.

Claims (2)

[Claims] (1) A memory circuit, and a digital signal input/output circuit that blocks input digital data at a predetermined period and outputs it to the memory circuit during recording, and reads and outputs the reproduced digital data stored in the memory circuit during playback. and, when recording, generates an error detection and correction code for input digital data stored in the memory circuit, outputs the error detection and correction code to the memory circuit, and when playing back, generates an error detection and correction code for the input digital data stored in the memory circuit, and when playing back, generates an error detection and correction code for the input digital data stored in the memory circuit. an error detection and correction circuit that detects and corrects errors in data to generate the reproduced digital data and outputs the reproduced digital data to the memory circuit; The memory circuit includes a recording signal generation circuit that converts a correction code into a recording signal and outputs it, and a reproduction signal processing circuit that demodulates the reproduction signal during reproduction and outputs the reproduction data to the memory circuit. The storage area is divided into three or more areas, and during recording, each of the divided areas is sequentially and cyclically assigned to the digital signal input/output circuit, the error detection and correction circuit, and the recording signal generation circuit at the above period, and during playback. , a digital signal processing device characterized in that each of the divided regions is sequentially and cyclically allocated to the reproduced signal processing circuit, the error detection and correction circuit, and the digital signal input/output circuit at the period. (2) A memory circuit, which switches its operation based on control data, blocks input digital data at a predetermined period and outputs it to the memory circuit during recording, and outputs the input digital data into blocks at a predetermined period during playback, and outputs the reproduced digital data stored in the memory circuit during playback A digital signal input/output circuit that reads and outputs data, and switches its operation based on control data, generates an error detection and correction code for input digital data stored in the memory circuit during recording, and generates an error detection and correction code for the input digital data stored in the memory circuit. an error detection and correction circuit that outputs to the memory circuit, detects and corrects errors in the reproduced data stored in the memory circuit during reproduction to generate the reproduced digital data, and outputs the reproduced digital data to the memory circuit; a recording signal generation circuit that switches an operation based on control data and converts the input digital data and the error detection and correction code stored in the memory circuit into a recording signal during recording, and outputs the recording signal; a reproduction signal processing circuit that switches the operation, demodulates the reproduction signal during reproduction, and outputs the reproduction data to the memory circuit; the memory circuit divides the storage area into three or more areas; Each of the divided areas is sequentially and cyclically assigned to the digital signal input/output circuit, the error detection and correction circuit, and the recording signal generation circuit at the cycle, and during playback, the reproduced signal processing circuit, the error detection and correction circuit, and the recording signal generation circuit Each of the divided areas is sequentially and cyclically assigned to the digital signal input/output circuit at the above period, and the memory circuit, the digital signal input/output circuit, the error detection and correction circuit, the recording signal generation circuit, and the reproduction signal processing circuit are allocated to the digital signal input/output circuit. The digital signal processing device is characterized in that when the control data switches from the reproduction mode to the recording mode, the reproduction operation switches to the recording operation after a predetermined period has elapsed based on the cycle.