JPH03180057A - Manufacture of semiconductor storage device - Google Patents

Abstract

PURPOSE:To improve the characteristics of a groove-type capacitor cell by a method wherein arsenic in first and second coating films containing the arsenic is diffused in a semiconductor substrate and thereby an impurity diffused layer facing a space surrounded by a groove is formed. CONSTITUTION:An oxide film 16a is formed on the bottom part of a groove 13 by coating of a silanol solution of low viscosity containing arsenic of high concentration, and then an oxide film 16b being continuous to the oxide film on the bottom part is formed on the side wall part of the groove 13 by coating of a silanol solution of high viscosity containing the arsenic of high concentration. Accordingly, a continuous shallow N<+> type diffused layer 17 can be formed uniformly and compactly in a region ranging from the bottom part of the groove 13 to the side wall part thereof. In other words, the arsenic in the oxide film 16 is diffused from the inside of the groove 13 into a P-type well 12 through a thin oxide film 20 by heat treatment, and thereby the shallow N<+> type diffused layer 17 of high concentration facing a space surrounded by the groove 13 is formed. According to this method, the impurity diffused layer 17 is formed in continuation, an effective cell capacity is increased and soft error resistance is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor memory device having a trench type capacitor cell.

[Conventional technology]

A typical prior art technique for manufacturing a semiconductor memory device having a trench type capacitor cell structure is shown in FIG.

That is, a P-type well 2 formed in a P-type semiconductor substrate 1
A groove 3 is formed therein. Then, a silanol-based solution containing arsenic at a high concentration of order 0 is applied to the semiconductor substrate so that a thin oxide film 10 is formed in the groove 3 by high-temperature treatment in an oxygen atmosphere.
to form an oxide film 6 containing a high concentration of arsenic. This state is shown in FIG. 3(1). 4 is a field oxide film, 5 is a CVD (Chemical
This is an oxide film formed by the vapor deposition method.

From the state shown in FIG. 3(1), arsenic in the oxide film 6 is diffused into the inner wall of the groove 3 through the oxide film 10 by high temperature treatment, thereby forming an N-type scattering layer 7. Then, phosphorus-containing polycrystalline silicon 9 is buried to a full depth through capacitor insulating film 8 to form a groove-type capacitor electrode. In this way, the cell capacitor portion of the dynamic memory device is formed. This state is shown in FIG. 3(2).

[Problem to be solved by the invention]

In the prior art as described above, when forming the oxide film 6 containing a high concentration of arsenic, a gap as shown by reference numeral 11 is created in the portion between the bottom and the side wall of the groove 3. As a result, the inside of the groove 3 cannot be coated uniformly without any gaps, and as a result, an N° type scattering occurs between the bottom of the groove 3 and the side wall, as shown by reference numeral i2 in FIG. 2 (2). Seven layers will be separated. This has resulted in a significant negative impact on the basic characteristics of the cell, such as an effective reduction in cell capacity and a deterioration in soft error resistance.

An object of the present invention is to provide a method for manufacturing a semiconductor memory device that can solve the above-mentioned technical problems and improve the characteristics of a trench type cavanck cell.

[Means to solve the problem]

The method for manufacturing a semiconductor memory device according to claim (1) includes the steps of: forming a groove in a semiconductor substrate; and applying a first silanol solution containing arsenic onto the semiconductor substrate to form arsenic at the bottom of the groove. a second silanol solution containing arsenic and having a higher viscosity than the first silanol solution on the semiconductor substrate; forming a second coating film containing arsenic on the sidewall; and diffusing arsenic in the first and second coating films containing arsenic from the inner surface of the groove into the semiconductor substrate; This method includes the step of forming an impurity diffusion layer facing the space surrounded by.

The method for manufacturing a semiconductor memory device according to claim (2) includes the steps of: forming a groove in a semiconductor substrate; applying a silanol solution containing arsenic onto the semiconductor substrate; and applying the semiconductor substrate in an oxygen atmosphere. a step of heat-treating; a step of reapplying a silanol-based solution containing arsenic onto the semiconductor substrate to form a coating film containing arsenic that continues from the bottom of the groove to the sidewalls; and a step of coating the inner surface of the groove. This method includes the steps of: diffusing arsenic in the arsenic-containing coating film into the semiconductor substrate, and forming an impurity diffusion layer facing the space surrounded by the groove.

[Effect]

According to the method of manufacturing a semiconductor memory device of claim (1), first, a first silanol solution having a relatively low viscosity is applied to the semiconductor substrate, and the first coating containing arsenic is applied to the bottom of the groove. A coating is formed. Then, a second silanol solution having a relatively high viscosity is applied to form a second coating film continuous with the first coating film on the side wall of the groove. In this way, a continuous arsenic-containing coating film is formed from the bottom of the trench to the sidewalls, so if high temperature treatment is performed afterwards, arsenic in the coating film will diffuse into the semiconductor substrate from the inside surface of the trench. As a result, an impurity diffusion layer facing the space surrounded by the groove is continuously formed.

This makes it possible to increase the effective cell capacity and improve soft error resistance at the same time.

According to the method for manufacturing a semiconductor memory device according to claim (2), the bottom and sidewall portions of the trenches are coated in the coating film formed by first applying a silanol solution and heat-treating it in an oxygen atmosphere. By applying the silanol solution a second time, the silanol solution can be applied to the gap formed between the silanol solution and the silanol solution. In this way, the coating film containing arsenic can be continuously formed in the region extending from the bottom of the groove to the side wall, and it is possible to obtain the same effect as the method of claim (1) above. can.

〔Example〕

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention in order of steps. This semiconductor memory device has a trench type capacitor cell, and FIG. 1 shows a process for manufacturing this trench type capacitor cell.

First, as shown in FIG. 1 (1), LOGO3 (Loc
After a field oxide film 14 is formed by a method (alxdation of 5 silicon), a part of the P-type well 12 is selectively etched by anisotropic etching using the CVD oxide film 15 as a mask to a depth of 3 to 5 μm.
A groove 13 of about 100 mL is formed with a field oxide film 14 sandwiched therebetween. Subsequently, the bottom and side walls of the groove 13 are cleaned with a mixed solution of ammonia and hydrogen peroxide. Then, a low-viscosity first silanol solution containing a high concentration of arsenic and using ethanol as the main solvent is applied dropwise to the entire surface of the semiconductor substrate 11, and the semiconductor substrate 11 is rotated at a rotation speed of 5000 to 6000 times/min.
Rotate 1. This rotation of the semiconductor substrate 11 causes the first silanol solution to spread uniformly over the surface of the semiconductor substrate 11. Thereafter, by performing low-temperature heat treatment, an oxide film 16a containing a high concentration of arsenic is formed on the remaining portion of the groove 13 except for the side wall portion, as shown in FIG.
) The state shown is as shown. This oxide film 16a is the first coating film. The reason why the oxide film 16a is not formed on the side walls of the groove 13 is because the first silanol solution applied has a low viscosity.

Figure 1 (+1 from the state shown in the figure to 500 in an oxygen atmosphere)
Heat treatment is performed at about ~800°C. As a result, a thin oxide film 20 with a thickness of about 20 to 50 mm is formed on the inner surface of the groove 13.
is formed. Next, a second silanol solution containing a high concentration of arsenic, using ethanol as the main solvent, and having a higher viscosity than the first silanol solution is applied dropwise to the entire surface of the semiconductor substrate 11, and then this semiconductor substrate 11 to 2000
The second silanol solution is uniformly spread over the semiconductor substrate 11 by rotating at a rotation speed of ~5000 times/min.

The second silanol solution having high viscosity also adheres to the side walls of the grooves 13. From this state, 100-300°C
By performing heat treatment to a certain degree, an oxide film 16b, which is a second coating film, is formed on the side wall of the groove 13 as shown in FIG. An oxide film 16 is formed.

From the state shown in FIG. 1(2), heat treatment is performed at approximately 1000-1050°C in a mixed gas atmosphere of nitrogen and oxygen, and as a result of this heat treatment, the arsenic in the oxide film 16 is removed through the thin oxide film 20. It diffuses into the P-type well 12 from the inner surface of the groove 13. As a result, a shallow N-type scattering layer 17 with high concentration (approximately 3×10” to 8×10” cm −3 ) facing the space surrounded by the groove 13 is formed. This N0 type diffusion 1
517 is formed so that the oxide film 16 is formed seamlessly on the inner wall surface of the groove 13, so that it surrounds the space within the groove 13 without any gap.

Next, a capacitor insulating film 18 is formed. A polycrystalline silicon film 19 containing phosphorus is then formed by low pressure CVD, and patterned using photolithography and dry etching. The polycrystalline silicon film 19 subjected to this patterning functions as a groove-type capacitor electrode. This state is shown in FIG. 1(3).

As described above, in this embodiment, the oxide film 16a is first formed at the bottom of the groove 13 by applying a low viscosity silanol solution containing a high concentration of arsenic, and then the oxide film 16a is formed at the bottom of the groove 13. By applying the silanol-based solution, an oxide film 16b that is continuous with the oxide film at the bottom is formed on the side wall of the trench 13, and as a result, a shallow N°-shaped continuous region from the bottom to the side wall of the trench 13 is formed. The diffusion 1i17 can be formed uniformly without gaps. As a result, there is no effective reduction in cell capacitance, and the capacitance tc-t when writing the signal rH, and the capacitance C1□ when writing the signal "L"
The value of the capacitance ratio C, i/C□, can be set to 90% or more. Furthermore, the resistance to soft errors caused by α rays is improved, and as a result, the basic characteristics of the cell are improved, and a semiconductor memory device with good storage characteristics can be realized. Furthermore, the effect of suppressing leakage current between adjacent trench capacitors can also be achieved.

FIG. 2 is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to another embodiment of the present invention in order of steps. In FIG. 2, parts corresponding to those shown in FIG. 1 described above are given the same reference numerals. In this embodiment, the grooves 13 are formed by anisotropic selective etching, and the grooves 13 are etched into the semiconductor substrate 11 in a cleaned state by a etching process of 500~. Heat treatment is performed at a temperature of about 800"C to form a film thickness of 20 to 50λ on the inner surface of the groove 13.
A relatively thin oxide film 20 is formed. Next, a silanol-based solution containing a high concentration of arsenic and using ethanol as a main solvent is applied dropwise to the entire surface of the semiconductor substrate 11, and then the semiconductor substrate 11 is rotated at a rotation speed of 2000 to 5000 times/min to remove the silanol-based solution. The solution is spread over the surface of the substrate 11. When heat treatment is performed at a temperature of about 500 to 800'C in an oxygen atmosphere, the state shown in FIG. 2(1) is obtained in which an oxide film 16 containing a high concentration of arsenic is formed on the surface.

In this state, as indicated by reference numeral 111, the portion inside the groove 13 is oxidized l! There is a gap at 16. That is, the state is equivalent to the state shown in FIG. 3(1) described above.

Fig. 2 0) From the state shown in the diagram, we again consider the silanol system containing a high concentration of arsenic and using ethanol as the main solvent. After applying the liquid No. 8 dropwise over the entire surface of the semiconductor substrate 11, the semiconductor substrate 11 is rotated at a rotation speed of 2000 to 5000 times/minute to spread the silanol solution uniformly over the surface of the semiconductor substrate 11. By this second application of the silanol-based solution, the silanol-based solution can also be applied to the gap indicated by reference numeral 11, and a continuous oxide film 16 can be formed on the bottom and sidewalls of the groove 13. This state is shown in Figure 2 (
2).

The subsequent processing is the same as in the first embodiment described above,
As shown in FIG. 2(3), a semiconductor memory device having a trench capacitor including a capacitance VA edge film 18 and a polycrystalline silicon film I9 serving as a trench capacitor electrode is constructed.

In this embodiment as well, the same effect as in the first embodiment described above can be obtained, and the capacitance 1 cmt- when writing the signal rH, and the capacitance IC, □ and ρ when writing the signal "L". C,,,/
The value of C and □ can be 85% or more.

[Effects of the Invention] As described above, according to the method for manufacturing a semiconductor memory device of the present invention, a coating film containing arsenic can be formed without gaps in the region extending from the bottom to the sidewalls of the trench for forming the trench capacitor. Therefore, the impurity diffusion layer formed by the diffusion of arsenic from the coating film and facing the space surrounded by the groove is continuously formed. As a result, effective cell capacity is increased and soft error resistance is also improved. Furthermore, since the impurity diffusion layer is continuously formed, leakage current between adjacent capacitors can be suppressed.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a method for manufacturing a semiconductor memory device according to an embodiment of the present invention in the order of steps, FIG. 2 is a sectional view showing another embodiment of the invention, and FIG. 3 is a sectional view showing a conventional technique. It is. DESCRIPTION OF SYMBOLS 11... Semiconductor substrate, 13... Groove, 16... Oxide film, 16 a-... Oxidation # (first covering y1 film), 16b
- @ film (second coating film), 17... N° type scattering layer impurity IJrA layer), 18... capacitive insulating film, 19.
...Polycrystalline silicon film 1st Figure 9 8 Figure 8

Claims (2)

[Claims] (1) Forming a groove in a semiconductor substrate; and applying a first silanol solution containing arsenic onto the semiconductor substrate to form a first coating film containing arsenic at the bottom of the groove. applying a second silanol-based solution containing arsenic and having a higher viscosity than the first silanol-based solution onto the semiconductor substrate, and applying a second coating containing arsenic to the sidewalls of the groove. forming a film; and diffusing arsenic in the first and second coating films containing arsenic from the inner surface of the groove into the semiconductor substrate to form an impurity diffusion layer facing the space surrounded by the groove. A method of manufacturing a semiconductor memory device, comprising the step of: (2) a step of forming a groove in a semiconductor substrate; a step of applying a silanol-based solution containing arsenic onto the semiconductor substrate; a step of heat-treating the semiconductor substrate in an oxygen atmosphere; reapplying the solution onto the semiconductor substrate to form a coating film containing arsenic that continues from the bottom of the groove to the sidewalls; and a step of coating the coating film containing arsenic from the inner surface of the groove. A method for manufacturing a semiconductor memory device, comprising the step of diffusing arsenic into a semiconductor substrate and forming an impurity diffusion layer facing a space surrounded by the trench.