JPS63119561A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To suppress the leakage current between neighboring groove-shaped capacitors, by uniformly forming shallow N-type diffused layers on both inner wall parts and both bottom parts of the first groove part and the second groove part. CONSTITUTION:A field oxide film 5 is formed on a part of a P<-> layer 2, which is formed on a P-type semiconductor substrate 1. Then a first groove part 3 and a second groove part 4 are formed at the neighboring positions. Thereafter a silanol solution, in which high concentration arsenic is included and ethanol is a main solvent, is dropped and applied on the entire surface. Thereafter, the substrate is turned. Then, heat treatment is performed, and both inner wall parts and both bottom parts of the first groove part 3 and the second groove part 4 are covered with oxide films including high concentration arsenic. Thereafter, arsenic ions are implanted only in both inner wall parts of the first groove part 3 and the second groove part 4. Then heat treatment is performed in a mixed gas atmosphere of nitrogen and oxygen. The arsenic is diffused into both bottom parts of the grooves from the oxide films 14. Thus shallow N-type diffused layers 9 having the uniform diffusion depth are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a trench type capacitor cell of an MO8 type memory device.

2. Description of the Related Art Conventionally, a method for forming a trench type capacitor cell of an MO8 type memory device has a structure as shown in the step-by-step sectional views of FIGS. 2a and 2b.

In Figures 2a and b, 1 is a P-type semiconductor substrate, 2 is a P-
3 is the first trench, 4 is the second trench, 5 is the field oxide film, 6 is the CVD oxide film, 7 is the ion beam, 8 is the scattered beam, 9 is N÷diffusion layer, 10 is the capacitor oxide film ,
11 is a polycrystalline silicon film containing phosphorus, 12 is a first cell capacitor section, and 13 is a second cell capacitor section. That is, the process shown in FIG.
After forming the first groove 3 and the adjacent second groove 4 in the layer 2, arsenic ions are implanted using the CVD oxide film 6 as a mask, and heat treatment is performed to form the first groove 3 and the second groove 4. This is a step of forming N+ diffusion layers 9 on both inner walls and both bottoms of 4. FIG. 2 shows that after removing the CVD oxide film 6 by etching, a polycrystalline silicon film 11 containing phosphorus is buried through the capacitor oxide film 10 to form adjacent first cell capacitor parts 12 and second cell capacitor parts in a dynamic memory device. A cell capacitor section 13 is formed.

Problems to be Solved by the Invention In such a conventional configuration, the ion beam 7 of arsenic ions is elastically scattered by the inner circular walls of the grooves 3 and 4, and the scattered beam 8 is scattered at both bottoms of the grooves 3 and 4. Injected in large quantities.

Therefore, the N
In the distribution of the diffusion layer 9, as shown in each figure in FIG. 2, the diffusion depth is significantly different between the inner wall portion of the groove portion 3 and the groove portion 4 and the bottom portions of the groove portion 3 and the groove portion 4. That is, in the vicinity of both bottoms, the impurity concentration of the N+ diffusion layer is abnormally high compared to the inner wall of the circle (therefore, the diffusion depth is also abnormally deep compared to the inner wall of the circle, and the adjacent trench type Capacitor (first
There was a problem in that leakage current between the second cell capacitor 12 and the second cell capacitor 13) could not be suppressed.

The present invention has been made to solve these problems, and it is an object of the present invention to provide a method for manufacturing a semiconductor device that can suppress leakage current between adjacent trench capacitors.

Means for Solving the Problem In order to solve this problem, the present invention forms a deep groove in a semiconductor substrate of one conductivity type, and then applies a silanol-based solution containing a high concentration of arsenic to the semiconductor substrate of one conductivity type. A step of coating the inner wall and bottom of the groove with an oxide film containing a high concentration of arsenic, which is thin on the inner wall of the groove and thick on the bottom of the groove, by applying the film onto a semiconductor substrate and subjecting it to heat treatment. , Arsenic is implanted with high energy into the inner wall of the groove through the oxide film with the ion beam tilted at a predetermined angle with respect to the inner wall of the groove, and then arsenic is removed from the oxide film by heat treatment. The method of manufacturing a semiconductor device includes the step of diffusing into the bottom of the trench to form a shallow high concentration N-type diffusion layer on the inner wall and bottom of the trench.

Function: In the present invention, an oxide film containing a high concentration of arsenic can be formed at the bottom of the groove, which is thicker than the inner wall of the groove.
At the time of arsenic ion implantation, it is possible to suppress the scattered beam that is elastically scattered on the inner wall of the groove from being implanted into the bottom of the groove. On the other hand, since there is an oxide film containing high concentration of arsenic at the bottom of the trench, if the heat treatment conditions are optimized, the impurity concentration and diffusion depth of the N-type diffusion layer at the inner wall and bottom of the trench can be improved. can be made equal. That is, the shallow N-type diffusion layer at the inner wall of the groove is formed by arsenic ion implantation, and the shallow N-type diffusion layer at the bottom of the groove is formed by arsenic diffusion from an oxide film containing a high concentration of arsenic. can. Therefore, leakage current between adjacent trench capacitors can also be suppressed.

Example Hereinafter, an embodiment of the present invention will be described with reference to FIG. 1a.

The explanation will be given based on the step-by-step sectional view of b.

First, in FIG. 1a, P
- After forming field oxide film 5 on a part of layer 2, P-
A part of the layer 2 is selectively etched to a depth of 3 to 6 μm by anisotropic etching using the CVD oxide film 6 as a mask.
A first groove part 3 and a second groove part 4 of about m length are formed adjacent to each other, and then a silanol solution containing a high concentration of arsenic and using ethanol as a main solvent is applied dropwise to the entire surface. The substrate is rotated at a rotation speed of 6000 to 500 times/min, and then heat treated at a temperature of about 100 to 300'C.
300 to 50 on the inner wall of the first groove 3 and the second groove 4
Approximately 0A, 1oo at both bottoms.

The inner walls and both bottoms of the first groove 3 and the second groove 4 are coated with a highly concentrated arsenic-containing oxide film 14 having a thickness of about 1,500 Å. Next, in Figure 1, the ion beam is
The acceleration energy is about 100 Kev, with the inner walls of the groove 3 and the second groove 4 inclined by about 10 inches.
Injection amount I
by sequentially rotating the first groove 3 and the second groove 4, arsenic ions are injected only into the inner wall of the circle through the oxide film 14 containing a high concentration of arsenic on both the inner walls of the first groove 3 and the second groove 4, Next, heat treatment is performed at a temperature of about 1000°C in a mixed gas atmosphere where the ratio of nitrogen and oxygen is 3=1.
Oxide film 1 containing high concentration arsenic on both bottoms of the groove portion
4, arsenic is diffused into both bottoms of the groove to form a shallow N-type diffusion layer 9 (with uniform diffusion depth) on the inner wall and bottom of the groove.
After forming an impurity concentration of about 1×1019 to I×10” cm and a diffusion depth of about 1000 to 2000 A,
The oxide film 14 is removed by etching with a hydrofluoric acid solution, and then a capacitor oxide film 10 with a thickness of about 100 to 200 A is formed on the entire surface other than the field oxide film 5 by thermal oxidation. A crystalline silicon film 11 is formed by low pressure CVD, and the phosphorus-containing polycrystalline silicon film other than the first cell capacitor section 12 and second cell capacitor section 13 is selectively removed to form the capacitor oxide film 10 and the phosphorus-containing polycrystalline silicon film. A capacitor electrode made of crystalline silicon film 11 is formed.

Effects of the Invention As described above, according to the present invention, it is possible to uniformly form a shallow N-type diffusion layer on the inner walls and both bottoms of the adjacent first groove portion and second groove portion, and to form a shallow N-type diffusion layer between the adjacent groove-type capacitors. The effect of suppressing leakage current can be obtained, a semiconductor device with desired characteristics can be provided, and the yield can be improved.

[Brief explanation of the drawing]

FIGS. 1a and 1b are cross-sectional views showing an embodiment of the present invention in the order of steps;
FIG. 2 is a process-order sectional view showing a conventional example. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... P- layer, 3... First groove, 4... Second groove, 5... ...Field oxide film, 6...
CVD oxide film, 7...Ion beam, 8...
...Scattered beam, 9...N+ layer, 10...
... Capacitor oxide film, 11 ... Polycrystalline silicon film containing phosphorus, 12 ... First cell capacitor part, 13 ... Second cell capacitor part, 14
...An oxide film containing a high concentration of arsenic. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1 Figure 2

Claims (1)

[Claims] After forming a deep groove in a semiconductor substrate of one conductivity type, a silanol solution containing a high concentration of arsenic is applied onto the semiconductor substrate of one conductivity type, and heat treatment is performed to form a thin groove on the inner wall of the groove. A step of coating the inner wall and bottom of the groove with a thick oxide film containing arsenic at a high concentration at the bottom of the groove, and performing the oxidation while tilting the ion beam at a predetermined angle with respect to the inner wall of the groove. Arsenic ions are implanted with high energy into the inner wall of the trench through the film, and then arsenic is diffused from the oxide film to the bottom of the trench by heat treatment to form a shallow high concentration N-type diffusion layer in the trench. 1. A method of manufacturing a semiconductor device, comprising the step of forming a uniform depth on the inner wall and bottom of the semiconductor device.