JPS6343356A - Semiconductor storage device and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase the capacitance of a capacitor, to improve the holding capacity of a memory and to reduce the generation of a soft-error by a method wherein a shallow side trench is formed around a deep main trench, buried with SiO2 and used as an isolation layer between a Tr and the main tranch, and a diffusion layer is shaped on the side wall of the main tranch and employed as a cell plate. CONSTITUTION:An SiO2 film 2, an SiN film 3 and a PSG film 4 are formed onto a P-type Si substrate 1, and an opening 5 is shaped to expose the substrate 1. An SiN film 6 is formed onto the film 4 and the substrate 1, and an SiN side wall remainder 6a is shaped on an upper surface. An SiO2 film 7 is formed onto the SiN side wall remainder 6a, and an upper surface is removed throgh etching to shape an SiO2 side wall remainder 7a. The SiN side wall remainder 6a is removed through etching. A side trench 8 and a main trench 9 are formed through etching, using the film 4 and the side wall remainder 7a as masks, and SiO2 films 11a, 11b are shaped through thermal oxidation. The film 11a is taken off, B is diffused to form a P<+> diffusion layer 12, and an insulating layer 14 and a poly Si layer 13 are shaped to bury the main trench 9. The SiN films 3, 14 on the surface are taken away. An MOSTr 21 is formed onto the surface, and a poly Si layer 15 connecting the layer 13 and a drain region 16 is shaped.

Description

[Detailed description of the invention] DR of substrate cell play I-type trench capacitor structure
When forming the AM capacitor part, a shallow side groove is formed close to the periphery of the deep main groove, and the inside of this side groove is filled with SiO.
It is filled with a 2-layer n2 film to serve as an isolation layer between the transistor and the
A diffusion layer is formed on the wall surface of the deep main groove, and this is used as a cell plate, and the present invention relates to a structure and a manufacturing method thereof.

Since almost the entire depth of the groove can be used as a cell plate, the capacitance of the capacitor is increased, the memory retention capacity is improved, and soft errors are less likely to occur.

[Fields of use for graduation]

The present invention is based on DRAM (Dynamic Rando).
The present invention relates to the structure of an MO3 type DRAM having a substrate cell plate type trench capacitor structure and its manufacturing method.

DRAMs with large capacities of I Mbit and 4 Mbit are already being put into practical use, and development toward even larger capacities is underway.

The memory cell configuration of these Daisha IDRAMs is one transistor/one capacitor (ITI), which is the most compact configuration.
C) type is used.

Figure 2 shows IT1. FIG. 2 is an equivalent circuit diagram of a C-type DRAM memory cell.

In this figure, 21 is a switching transistor whose gate electrode is connected to the word line 16, its source to the bit line 20, and its drain to the capacitor 22.

By turning this transistor 21 ON and OFF to connect the capacitor 22 and the bit line 20, or by color-fringing them, the amount of charge accumulated in the capacitor 22 is detected as a change in the potential of the bit line 20. read out.

With the reduction in memory cell size due to higher integration, the area of the capacitor part is also decreasing, but the decrease in the amount of memory charge due to the reduction in the area of the capacitor part causes problems with resistance to alpha rays and deterioration of the sensitivity of the sense amplifier.

Conventionally, in order to solve this problem, a groove (trench) is formed in the semiconductor substrate as a method of forming a large storage capacity portion despite the reduction of the memory cell area. A method of forming a capacitor is known.

According to this RAM, if the depth of the groove is increased,
Although it is possible to increase the abrasive capacity by that much, various problems arise by digging deeply into the substrate. That is, the grooves are formed by anisotropic etching, but forming deep straight grooves is difficult because of the problem of directional uniformity of etching ions and the problem of reflection of ions on the groove sidewalls. Therefore, the present invention seeks to provide a method of forming a capacitance by making maximum use of a groove of limited depth.

[Conventional technology]

FIG. 3 is a schematic cross-sectional view of a memory cell of a conventional DRAM.

In this figure, Si has a high resistance P-type epitaxial layer i32 on the surface of a low resistance P''+Si+Si substrate to a thickness of about 1.
It is formed to have a thickness of 5 μm. The groove 33 is formed between the Si substrate Si (when there is no particular need to distinguish between the epitaxial layer 32 and the S
The inside of the i-substrate Si is filled with a doped polysilicon layer 3S, which is collectively referred to as a Si-based silicon layer 3S.

The capacitor 22 is composed of the Si substrate Si of P~ and the four polysilicon layers 35 on the Sing film 34.

The polysilicon layer 35 is connected to the drain 18 of one N' diffusion layer of the transistor 21 by the polysilicon layer 15. The gate 16 of the transistor 21 is formed on a gate oxide film and also serves as a word line. An AI bit line 20 is connected to the source 17 of the other N diffusion layer of the transistor 21 via a contact hole, and extends in a direction perpendicular to the word line 16.

16B is the word line of the adjacent memory cell, and this word line 1
It has a three-dimensional structure in which the capacitor 22 is formed almost under the capacitor 6B. Furthermore, since one cell plate (electrode) of the capacitor 22 is of a substrate cell plate type using a Si substrate, the structure has a structure in which there is little leakage between the grooves.

However, in this structure, the full depth of the groove 33 does not contribute as a cell plate of the capacitor;
Since it is essentially limited to a portion formed on the low-resistance P'' Si substrate, the capacitance of the capacitor becomes smaller, which is also disadvantageous in terms of soft errors.

[Problem that the invention seeks to solve]

In a conventional DRAM with a substrate cell plate type trench capacitor structure, only a part of the depth of the trench is used for the cell plate of the capacitor, which is not sufficient as a method for increasing the capacitance of the capacitor.

[Means for solving problems]

The solution to the above problem is to provide a MOS transistor (21) provided on the surface of a silicon (Si) substrate (1) and a capacitor (22) formed on the surface of the Si substrate (1) near this transistor. In the semiconductor memory device, the capacitor (22) has a silicon oxide film (SiOx film), (11b
) an impurity diffusion layer (12) formed on the inner wall of a deep trench (9) that is surrounded by a shallow side trench (8) filled with The polysilicon (13) is electrically connected to the drain region (16) forming a part of the MOS transistor (21). A semiconductor memory device characterized by a three-layer structure comprising a silicon oxide film (2), a silicon nitride (SiN) film (3), and a phosphosilicate glass (PSG) film (4) on the surface of a silicon substrate (1). After forming the films in this order, there is a step of forming an opening (5) in the three-layer film, and forming a SiN film sidewall remainder (6a) on the sidewall of the opening (5).
is formed, and furthermore, Si is formed on the remaining SiN film sidewall (6a).
A step of providing an O□ film sidewall residue (7a) and forming a double sidewall residue, and then removing the SiN film sidewall residue (6a) and removing the remaining SiO□ film sidewall residue (7a) and the three-layer film. Using as a mask, anisotropic etching is performed on the Si substrate (1), a groove (9) is formed in the center of the opening (5), and the SiO2 film n2 film is etched around the groove (9). Remains of side wall (7a)
Below is a projection (10) that is the remaining part of the Si substrate (1).
), and furthermore, the original Si around this protrusion (10)
There is a step of forming a side groove (8) below where the N film sidewall residue (6a) was, and this Si substrate (1) is oxidized to form a SiO2 film (11a) on the surface of the Si substrate (1). At the same time as the formation, there is a step of filling the side groove (8) with a SiO2 film (11b), removing the surface oxide film other than the SiO□ film (11b), and diffusing impurities into the side walls and bottom of the groove (9). The step of forming a layer (12) and the step of forming an insulating film (
14) and then fill the inside of the groove (9) with polysilicon (
This is achieved by a method of manufacturing a semiconductor memory device including the filling step 13).

[Effect]

Substrate cell plate type trench capacitor tlA structure D
When forming the capacitor part of RAM, the deep main z1
), a shallow side trench is formed whose inside is filled with a SiO2 film, and this is used as an insulating layer between the capacitor and the transistor, and then a diffusion layer is formed on the wall of the deep main trench, This structure uses this as a cell plate, which allows almost the entire depth of the groove to be used as a cell plate, so the capacitance of the capacitor increases even with the same depth of the groove, improving memory retention capacity. A soft error may occur.

〔Example〕

FIGS. 1(a) to (j) are cross-sectional schematic diagrams for explaining the process of forming a DRAM memory cell according to the present invention. FIG. Shows the adhered state.

A SiO2 film 02 film 2 with a thickness of about 300 layers is formed on a P-type Si substrate 1 by thermal oxidation. Subsequently, about 500 silicon nitride films (SiN films) 3 are deposited thereon by the CVD method. Further, a phosphosilicate glass (PSG) film 4 is formed thereon to a thickness of about 1 μm by CVD.

Next, using a photoresist formed by a normal photo process as a mask, the three layers of the insulating film, P
Openings 5 for forming capacitor grooves are formed in the SG film 4, SiN film 3, and SiO2 film N2 film 2 by RIE anisotropic etching to expose the Si substrate 1.

Anisotropic etching: gas: CI+h, pressure crab 0.2To
rr, electric crab 0. It is carried out under the condition of I W/cm2.

Subsequently, approximately 1000 SiN films 6 were applied to this surface by CVD.
Adhesion is formed using method D.

FIG. 1(b) shows a state in which the SiO2 film and the Oz film are deposited again after the SiN sidewalls are formed.

By performing anisotropic etching and removing approximately 1,000 portions of the upwardly facing surface of the SiN film 6, a remaining SiN sidewall 6a is formed inside the sidewall of the opening 5. The anisotropic etching at this time is gas: CHF3, pressure crab 0.2 Torrs, electric crab 0. It is carried out under the condition of I W/cm2.

Next, SiO□II! 7 was deposited by about 1,000 people using the CVD method.

FIG. 1(c) shows a state in which double sidewall rows are formed in the opening.

By performing anisotropic etching and removing approximately 1,000 portions of the upward facing surface of the SiO2 film n2 film 7, SiO2
S i the side wall 'IU 7a! J side wall "A6a" to form a double side wall row in the opening 5.

The anisotropic etching at this time was also performed using gas: C) Ih, pressure crab 0.2 Torr, electric crab 0. IW/crr
This is done under 12 conditions.

FIG. 1(d) shows a state in which the SiN side wall tucking has been removed.

The remaining SiN sidewall 6a is removed by etching with phosphoric acid.

As a result, after removing the SiN side wall residue 6a, approximately d=
Ring-shaped Si substrate 1 with a narrow width of about 1000 people
An exposed surface is obtained.

At this time, some side etching occurs in the SiN film 3.

Figure 1(e) shows the PSG after trench etching.
The state in which the remaining sidewalls of the SiO2 film O7 and the SiO2 film have been removed is not shown.

Using the PSG film 4 and the remaining sidewalls 7a of the SiO2 film 02 as masks, Rrcl and directional etching are performed on the Si substrate 1 to form a trench. In the opening 5, Si
Where the substrate 1 is widely exposed, a deep main groove 9 is formed with a depth of approximately 4 to 5 μm.
Form to a depth of m. At the same time, the remaining SiN side wall 6a
A shallow side groove 8 is formed in the narrow exposed portion created by removing the grooves, and a protrusion 10 made of a thin Si substrate 1 is formed between both grooves.

The reason why the side groove 8 becomes shallow is because of the three-layer film (PSG film 4, SiN
The thickness t of the mask formed by the film 3, the S t Oz film 2) and the SiO2 film n2 sidewall remaining 7a is approximately 1.08 μm, whereas the width d of the exposed portion of the Si substrate I is approximately 0.1 μm. This is because fewer ions can pass through the narrow canyon of the mask and contribute to etching.

The depth of the gutter 8 therefore varies depending on the width of the canyon of the mask. That is, it can be adjusted by adjusting the thickness of the SiN film 3.

The conditions for anisotropic etching are: gas: CF3Br, pressure crab: 0.4 Torr, electric crab: lW/am''.

Then, the PSG film 4 and the remaining SiO□ sidewall 7a are removed by etching with hydrofluoric acid.

FIG. 1(f) shows the state in which the surface has been thermally oxidized.

Main 71' is thermally oxidized in an oxidizing atmosphere at a temperature of 1000°C.
A SiO□ film 11a having a thickness of about 3000 is formed on the inner wall of ri9.

By this thermal oxidation, the side trench 8 is filled with the SiO□ film 11b.

FIG. 1(g) shows a state in which a boron diffusion layer is formed on the inner wall of the main groove.

The surface of the Si substrate 1 is etched with hydrofluoric acid to form a SiO2 film.
The z film 11a is removed.

Next, by diffusing boron (B), a P diffusion layer is formed on the inner wall surface of the main groove 9 where Si is exposed.

Diffusion is carried out at a temperature of 900°C after applying the B-containing siloxane resin.
Diffusion at ℃, followed by etching and removal of the siloxane resin with hydrofluoric acid.

Another method for this diffusion is to deposit a boron phosphosilicate glass (BPSG) film with a thickness of about 3,000 ml using the CVD method.
After forming a human thickness, it is diffused at a temperature of 900℃, and then BP is applied.
A method of removing the SG film by etching with hydrofluoric acid may also be used.

FIG. 1(h) shows a state in which an insulating film is deposited on the surface and then a polysilicon layer is deposited to fill the main groove.

Approximately 250 SiN films are deposited as the insulating film 14 using the CVD method. Next, a polysilicon layer (polySi layer) 13 doped with an N-type impurity (for example, phosphorus) is formed into a film P by a CVD method.
The main groove 9 is completely filled with a thickness of approximately 1.5 μm.

Next, the poly-Si layer 13 is etched back until the SiN film is exposed to remove excess poly-Si and flatten the surface. Etch back gas: CF4+0□, pressure crab I
This is done by plasma etching under conditions of 5W/cm'' Torr%.

FIG. 1(i) shows a state in which the SiN film on the surface of the Si substrate has been removed.

The SiN film 3 and the SiN film 14 on the surface of the Si substrate 1 are removed by etching with phosphoric acid.

FIG. 1(j) shows a state in which the gate, drain and source of a MOS transistor, a poly-SiN connection between the cell plate and the drain, and a bit line are formed.

As shown in this figure, the structure other than the capacitor 22 is the same as that of the conventional example shown in FIG. 3, and therefore the formation process is also the same.

The outline of this process is as follows.

After forming the N″ region of the drain connection region, the poly-Si layer 13 of one cell plate of the capacitor 22 and the N″
A poly-Si layer 15 is formed to connect the regions, and CV
A DSiO□ layer is deposited, a gate oxide film of a predetermined thickness is formed, and a polycide film (MoSiO2 film z on polySt) is formed on this.
Form the electrode of the gate 16 of This gate 16 also serves as a word line, and a word line 16B of an adjacent memory cell is also formed at the same time.

N is self-aligned with this gate 16 and poly-Si layer 15.
A type impurity is ion-implanted and then activated to form a source 17 and a drain 18 of the N diffusion layer.

After coating the CV DSiO□ film, a contact window is opened to form an A1 bit line 20.

In this way, a DRAM having a substrate cell plate type trench capacitor structure according to the present invention can be obtained.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the DRAM
By creating a shallow trench around the lead as a trench for the capacitor, and filling this with a 540g film to create an insulating slope, almost the entire trench wall surface can be used as a cell plate.
The capacity of the capacitor is increased, memory retention capacity is improved, and soft errors are less likely to occur.

[Brief explanation of the drawing]

FIGS. 1(a) to (j) are schematic cross-sectional diagrams for explaining the process of forming a DRAM memory cell in the present invention. FIG.
Equivalent circuit diagram of a TIC type DRAM memory cell. FIG. 3 is a schematic cross-sectional view of a DRAM memory cell in a conventional example. In this figure, 1 is a Si substrate (P type), 2 is an SiO2 film, 3 is an SiN film, 4 is a PSG film, 5 is an opening, 6 is a SiN film, 6a is a SiN sidewall, the sidewall is an SiO□ film, and 7a is a SiO□ film. SiO□ side wall remaining, 8 is a side groove, 9 is a main groove, 10 is a protrusion, 11a and 11b are SiO2 film Oz film, 12 is a diffusion layer, 13 is a polysilicon layer (poly-Si layer), 14 is an insulating film (
15 is a polysilicon layer (poly-Si layer), 16 is a gate (
16B is the word line of the adjacent memory cell, 17 is the source, 18 is the drain 19 is the SiO□ film, 20 is the bit line, 21 is the transistor, 22 is the capacitor,议

Claims (1)

[Claims] [1] A MOS transistor (21) provided on the surface of a silicon (Si) substrate (1), and a capacitor (22) formed on the surface of the Si substrate (1) near this transistor. In the semiconductor storage device comprising the capacitor (22), the inside thereof is covered with a silicon oxide film (SiO_2 film) (11b).
An impurity diffusion layer (12) formed on the inner wall of a deep trench (9) that is surrounded by a shallow side trench (8) filled with and is characterized in that the polysilicon (13) is electrically connected to a drain region (16) forming a part of the MOS transistor (21). Semiconductor storage device. [2] Silicon oxide (SiO_2) film (2) and silicon nitride (SiN) on the surface of the silicon (Si) substrate (1)
After forming a three-layer film consisting of a film (3) and a phosphosilicate glass (PSG) film (4) in this order, providing an opening (5) in the three-layer film; and a step of forming an opening (5) on the side wall of the opening (5). On top of that, the remaining SiN film sidewall (6a)
is formed, and furthermore, Si is formed on the remaining SiN film sidewall (6a).
A step of providing an O_2 film sidewall residue (7a) and forming a double sidewall residue, and then removing the SiN film sidewall residue (6a) and masking the remaining SiO_2 film sidewall residue (7a) and the three-layer film. Anisotropic etching is performed on the Si substrate (1) to form a groove (9) in the center of the opening (5), and the remaining SiO_2 film sidewall (7a) around the groove (9) is etched. ) is a protrusion (10) which is the remaining part of the Si substrate (1).
is formed, and furthermore, the original SiN around this protrusion (10) is
At the same time, a side groove (8) is formed below where the film side wall residue (6a) was, and this Si substrate (1) is oxidized to form a SiO_2 film (11a) on the surface of the Si substrate (1). Gutter (8
) with the SiO_2 film (11b), and
The surface oxide film other than the O_2 film (11b) is removed, and the groove (9
) to form a diffusion layer (12) by diffusing impurities on the side walls and bottom of the groove (9), and forming an insulating film (1) on the surface of the Si substrate (1) including the inside of the groove (9).
14) and then fill the inside of the groove (9) with polysilicon (
13) A method for manufacturing a semiconductor memory device, comprising the step of filling.