JPH03178154A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH03178154A JPH03178154A JP1317306A JP31730689A JPH03178154A JP H03178154 A JPH03178154 A JP H03178154A JP 1317306 A JP1317306 A JP 1317306A JP 31730689 A JP31730689 A JP 31730689A JP H03178154 A JPH03178154 A JP H03178154A
- Authority
- JP
- Japan
- Prior art keywords
- cap
- thermally conductive
- cooling pipe
- conductive grease
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000001816 cooling Methods 0.000 claims abstract description 45
- 239000004519 grease Substances 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 229910000679 solder Inorganic materials 0.000 abstract description 11
- 230000002093 peripheral effect Effects 0.000 abstract description 5
- 230000000694 effects Effects 0.000 description 6
- 239000003507 refrigerant Substances 0.000 description 6
- 229910003460 diamond Inorganic materials 0.000 description 5
- 239000010432 diamond Substances 0.000 description 5
- 239000000843 powder Substances 0.000 description 5
- 229910001128 Sn alloy Inorganic materials 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 229910000978 Pb alloy Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000011231 conductive filler Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052863 mullite Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路装置に関し、特に気密封止（
ハーメチック・シール）構造を有する半導体集積回路装
置の冷却に適用して効果のある技術に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a hermetically sealed (
The present invention relates to a technique that is effective when applied to cooling a semiconductor integrated circuit device having a hermetic seal structure.
半導体集積回路装置の気密封止構造の一つに、ＣＣＢバ
ンプを介してパッケージ基板に実装された半導体チップ
をキャップで気密封止した、いわゆるチップキャリヤ（
Ｃｈｉｐ Ｃａｒｒｉｅｒ）が知られている。このチッ
プキャリヤは、前記パッケージ基板の下面に設けたＣＣ
Ｂバンプを介してモジュール基板に実装されるようにな
っている（特開昭６２−２４９４２９号公報、特開昭６
３−３１０１３９号公報など〉。One of the hermetically sealed structures for semiconductor integrated circuit devices is a so-called chip carrier (chip carrier) in which a semiconductor chip mounted on a package substrate via CCB bumps is hermetically sealed with a cap.
Chip Carrier) is known. This chip carrier is a CC provided on the bottom surface of the package substrate.
It is mounted on the module board via the B bump (Japanese Patent Application Laid-Open No. 62-249429, Japanese Patent Application Laid-open No. 62-249429,
3-310139 etc.>.
近年、上記チップキャリヤは、集積回路の高密度化に伴
ってチップあたりの消費電力が著しく増大しており、そ
のため回路動作時にチップから発生する熱を如何に効率
よく外部に放出するかがチップの動作信頼性を確保する
上で重要な課題となっている。In recent years, the power consumption per chip of the above-mentioned chip carriers has increased significantly due to the increase in the density of integrated circuits, and therefore, it is important to efficiently dissipate the heat generated from the chip during circuit operation to the outside. This is an important issue in ensuring operational reliability.
そこで、上記チップキャリヤにおいては、チップの背面
とキャップの下面とを半田で接合することによって、チ
ップから発生する熱をこの半田を通じてキャップに逃が
すようにしており、さらに、チップキャリヤをモジュー
ル基板に実装する際には、前記キャップの上面に熱伝導
グリースを介して冷却管を重ね合せ、この冷却管内を流
れる冷媒によってキャップを冷却するようにしている。Therefore, in the above-mentioned chip carrier, the back surface of the chip and the bottom surface of the cap are joined with solder so that the heat generated from the chip is released to the cap through the solder.Furthermore, the chip carrier is mounted on the module board. When doing so, a cooling pipe is superimposed on the upper surface of the cap via thermally conductive grease, and the cap is cooled by the refrigerant flowing inside the cooling pipe.
なお、このようなチップキャリヤの冷却構造については
、特開昭５５−１７８８８５号公報に記載されている。Incidentally, such a cooling structure for a chip carrier is described in Japanese Patent Laid-Open No. 178885/1985.
〔発明が解決しようとする課題〕
ところが、熱伝導グリースを介してキャップの上面に冷
却管を重合する前記チップキャリヤの冷却構造において
は、キャップの温度が上昇した際に熱伝導グリースの粘
度が低下するため、その−部がキャップの外壁を伝って
パッケージ基板の下面に流れ込む結果、熱伝導グリース
中に含まれる導電性フィラーを介してＣＣＢバンプ同士
が短絡するという問題があった。[Problems to be Solved by the Invention] However, in the cooling structure of the chip carrier in which a cooling pipe is superimposed on the upper surface of the cap via thermally conductive grease, the viscosity of the thermally conductive grease decreases when the temperature of the cap increases. As a result, the negative portion flows along the outer wall of the cap and onto the lower surface of the package substrate, causing a problem in that the CCB bumps are short-circuited via the conductive filler contained in the thermally conductive grease.
本発明の目的は、上述した問題点を改善した半導体集積
回路装置の冷却技術を提供することにある。An object of the present invention is to provide a cooling technique for a semiconductor integrated circuit device that improves the above-mentioned problems.
本発明の他の目的は、上記目的を達成するとともに、半
導体集積回路装置の冷却効率を向上させることのできる
技術を提供することにある。Another object of the present invention is to provide a technique that can achieve the above object and improve the cooling efficiency of a semiconductor integrated circuit device.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、次のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
本願の一発明は、ＣＣＢバンプを介してパッケージ基板
の主面に実装された半導体チップをキャップで気密封止
してなるパッケージをモジュール基板の主面に実装し、
前記キャップの上面に設けた凹溝内に熱伝導グリースを
充填するとともに、前記キャップの上面に冷却管を重合
した半導体集積回路装置である。One invention of the present application includes mounting a package on the main surface of a module substrate, in which a semiconductor chip mounted on the main surface of a package substrate via CCB bumps is hermetically sealed with a cap,
In the semiconductor integrated circuit device, a concave groove provided on the top surface of the cap is filled with thermally conductive grease, and a cooling pipe is superimposed on the top surface of the cap.
上記した手段によれば、キャップの上面に設けた凹溝内
に熱伝導グリースを充填することにより、キャップの温
度が上昇した際における熱伝導グリースの流出が抑制さ
れる。According to the above means, by filling the groove provided in the upper surface of the cap with thermally conductive grease, the outflow of the thermally conductive grease when the temperature of the cap rises is suppressed.
〔実施例１〕
第１図に示すように、本実施例１０半導体集積回路装置
は、モジュール基板１の主面に実装されたチップキャリ
ヤ２の上に冷却管３を重ね合わせた構造を有している。[Example 1] As shown in FIG. 1, the semiconductor integrated circuit device of Example 10 has a structure in which a cooling pipe 3 is superimposed on a chip carrier 2 mounted on the main surface of a module substrate 1. ing.
図示はしないが、モジュール基板ｌの主面には、複数の
チップキャリヤ２が所定の間隔を置いて実装されている
。Although not shown, a plurality of chip carriers 2 are mounted on the main surface of the module board 1 at predetermined intervals.
チップキャリヤ２は、ＣＣＢバンプ４を介してパッケー
ジ基板５の電極６上にフェイスダウン・ボンディングし
た半導体チップ７をキャップ８で気密封止したパッケー
ジ構造を備えている。このキャップ８は、封止用半田９
を介してパッケージ基板５の主面に接合されている。The chip carrier 2 has a package structure in which a semiconductor chip 7 is face-down bonded onto an electrode 6 of a package substrate 5 via a CCB bump 4 and hermetically sealed with a cap 8. This cap 8 is soldered with sealing solder 9
It is bonded to the main surface of the package substrate 5 via.
半導体チップ７の背面（上面）は、伝熱用半田１０を介
してキャップ８の下面に固着されている。The back surface (upper surface) of the semiconductor chip 7 is fixed to the lower surface of the cap 8 via heat transfer solder 10.
従って、半導体チップ７から発生した熱は、伝熱用半田
１０を通じてキャップ８に伝達され、さらに冷却管３に
伝達される。この冷却管３の内部には、所定の間隔を置
いて冷媒流路１１が設けられており、それぞれの冷媒流
路ｌｌ内には、水などの冷媒Ｃが流れるようになってい
る。Therefore, the heat generated from the semiconductor chip 7 is transferred to the cap 8 through the heat transfer solder 10 and further transferred to the cooling pipe 3. Inside the cooling pipe 3, refrigerant channels 11 are provided at predetermined intervals, and a refrigerant C such as water flows in each refrigerant channel ll.
パッケージ基板５の下面の電極６には、前記ＣＣＢバン
プ４よりも径の大きいＣＣＢバンプ１２が接合されてお
り、チップキャリヤ２は、このＣＣＢバンプ１２を介し
てモジュール基板１の電極６に接続されている。ＣＣＢ
バンプ１２は、パッケージ基板５内に設けられたＷ（タ
ングステン〉などの内部配線１３を通じてＣＣＢバンプ
４、さらには半導体チップ７と電気的に接続されている
。A CCB bump 12 having a larger diameter than the CCB bump 4 is bonded to the electrode 6 on the lower surface of the package substrate 5, and the chip carrier 2 is connected to the electrode 6 of the module substrate 1 via this CCB bump 12. ing. C.C.B.
The bumps 12 are electrically connected to the CCB bumps 4 and further to the semiconductor chip 7 through internal wiring 13 made of W (tungsten) or the like provided in the package substrate 5 .
なお、前記パッケージ基板５は、ムライトなどのセラミ
ック材料で構成されており、キャップ８は、例えば窒化
アルミニウム（ＡｆＮ）で構成されている。ＣＣＢバン
プ４は、例えば２重量％程度のＳｎを含有するＰ ｂ
／ Ｓ ｎ合金（融点＝３２０〜３３０℃程度）で構成
されており、ＣＣＢバンプ１２は、例えば３０重量％程
度のＳｎを含有するＰ ｂ ／ Ｓ ｎ合金（融点＝２
５０〜２６０℃程度）で構成されている。封止用半田９
および伝熱用半田ＩＯは、例えばｌＯ重量％程度のＳｎ
を含有するＰ ｂ ／ Ｓ ｎ合金（Ｍ点−２９０〜３
００℃程度）で構成されている。冷却管３は、セラミッ
クや金属のような熱伝導率の高い材料で構成されている
。The package substrate 5 is made of a ceramic material such as mullite, and the cap 8 is made of aluminum nitride (AfN), for example. The CCB bump 4 is made of, for example, Pb containing about 2% by weight of Sn.
/Sn alloy (melting point = about 320 to 330°C), and the CCB bump 12 is made of, for example, a Pb/Sn alloy (melting point = 2) containing about 30% by weight of Sn.
(approximately 50 to 260°C). Sealing solder 9
For example, the heat transfer solder IO contains about 10% by weight of Sn.
Pb/Sn alloy containing (M point -290~3
00℃). The cooling pipe 3 is made of a material with high thermal conductivity such as ceramic or metal.
本実施例１のチップキャリヤ２は、キャップ８の上面中
央部に凹溝１４が設けられている。また、この凹溝１４
内には、熱伝導グリース１５が隙間なく充填されている
。そのため、半導体チップ７から発生した熱は、伝熱用
半田１０を通じてキャップ８に伝達された後、主として
凹溝１４内の熱伝導グリース１５を通じて冷却管３に伝
達される。In the chip carrier 2 of the first embodiment, a groove 14 is provided in the center of the upper surface of the cap 8. In addition, this groove 14
The inside is filled with thermally conductive grease 15 without any gaps. Therefore, the heat generated from the semiconductor chip 7 is transferred to the cap 8 through the heat transfer solder 10 and then transferred to the cooling pipe 3 mainly through the heat transfer grease 15 in the groove 14.
また、キャップ８に伝達された熱の一部は、キャップ８
と冷却管３との接触面（キャップ８の上面周縁部）を通
じて冷却管３に伝達される。Also, part of the heat transferred to the cap 8 is transferred to the cap 8.
It is transmitted to the cooling pipe 3 through the contact surface (the upper peripheral edge of the cap 8) with the cooling pipe 3.
上記熱伝導グリース１５には、ダイヤモンド粉末からな
る熱伝導媒体（図示せず）が含有されている。このダイ
ヤモンド粉末が含有されることにより、熱伝導グリース
１５は、その熱伝導率が大きくなるとともに、粘性も高
くなる。The thermally conductive grease 15 contains a thermally conductive medium (not shown) made of diamond powder. By containing this diamond powder, the thermal conductive grease 15 has a high thermal conductivity and a high viscosity.
一方、キャップ８の上面周縁部、すなわちキャップ８が
冷却管３と接触する面には、Ａｕのメタライズ層１６が
設けられている。Ａｕは、軟質の金属であるため、キャ
ップ８上に冷却管３を重ね合わせた後、冷却管３の上面
に適度の圧力を印加することにより、メタライズ層１６
の表面が僅かに変形してキャップ８と冷却管３との接触
面の密着性が向上する。On the other hand, an Au metallized layer 16 is provided on the upper peripheral edge of the cap 8, that is, on the surface where the cap 8 contacts the cooling pipe 3. Since Au is a soft metal, after superimposing the cooling pipe 3 on the cap 8, by applying an appropriate pressure to the upper surface of the cooling pipe 3, the metallized layer 16 is formed.
The surface of the cap 8 is slightly deformed, and the adhesion of the contact surface between the cap 8 and the cooling pipe 3 is improved.
以上のように構成された本実施例１の半導体集積回路装
置においては、下記のような効果を得ることができる。In the semiconductor integrated circuit device of the first embodiment configured as described above, the following effects can be obtained.
〔１）、モジュール基板１の主面に実装されたチップキ
ャリヤ２のキャップ８上に冷却管３を重ね合わせた半導
体集積回路装置において、上記キャップ８の上面に凹溝
１４を設け、その内部に熱伝導グリース１５を充填した
ことにより、キャップ８の温度上昇に伴って熱膨張する
熱伝導グリース１５がキャップ８の外壁を伝ってパッケ
ージ基板５の下面に流れ込むのを抑制することができる
ので、ＣＣＢバンプ１２同士の短絡を防止することがで
きる。[1) In a semiconductor integrated circuit device in which a cooling pipe 3 is superimposed on a cap 8 of a chip carrier 2 mounted on the main surface of a module substrate 1, a groove 14 is provided on the upper surface of the cap 8, and a groove 14 is provided inside the cap 8. By filling the thermally conductive grease 15, it is possible to suppress the thermally conductive grease 15, which thermally expands as the temperature of the cap 8 rises, from flowing along the outer wall of the cap 8 to the lower surface of the package substrate 5. Short circuits between the bumps 12 can be prevented.
（２）、熱伝導グリース１５にダイヤモンド粉末を含有
させたことにより、熱伝導グリース１５の粘性が高くな
り、キャップ８の温度上昇に伴う熱伝導グリース１５の
粘性低下が抑制されるので、上記（１）の効果をより確
実に得ることができる。(2) By including diamond powder in the thermally conductive grease 15, the viscosity of the thermally conductive grease 15 becomes high, and a decrease in the viscosity of the thermally conductive grease 15 due to a rise in the temperature of the cap 8 is suppressed. The effect of 1) can be obtained more reliably.
（３）、キャップ８の上面周縁部にＡｕのメタライズ層
１６を形成し、キャップ８と冷却管３との接触面の密着
性を向上させたことにより、上記（１）の効果をより確
実に得ることができる。(3) By forming an Au metallized layer 16 on the periphery of the upper surface of the cap 8 and improving the adhesion of the contact surface between the cap 8 and the cooling pipe 3, the effect of (1) above can be more reliably achieved. Obtainable.
（４）、熱伝導グリース１５にダイヤモンド粉末を含有
させてその熱伝導率を大きくしたことにより、凹溝１４
内の熱伝導グリース１５を通じて冷却管３に伝達される
熱量が増大するので、半導体集積回路装置の冷却効率が
向上する。(4) By incorporating diamond powder into the thermally conductive grease 15 to increase its thermal conductivity, the grooves 14
Since the amount of heat transferred to the cooling pipe 3 through the thermally conductive grease 15 inside increases, the cooling efficiency of the semiconductor integrated circuit device is improved.
（５）、キャップ８の上面周縁部にＡｕのメタライズ層
１６を形成し、キャップ８と冷却管３との接触面の密着
性を向上させたことにより、この接触面を通じて冷却管
３に伝達される熱量が増大するので、半導体集積回路装
置の冷却効率が向上する。(5) By forming an Au metallized layer 16 on the peripheral edge of the upper surface of the cap 8 to improve the adhesion of the contact surface between the cap 8 and the cooling pipe 3, the amount of light transmitted to the cooling pipe 3 through this contact surface is Since the amount of heat generated increases, the cooling efficiency of the semiconductor integrated circuit device improves.
〔実施例２〕
本実施例２の半導体集積回路装置は、前記実施例１゛と
同じくモジュール基板１の主面に実装されたチップキャ
リヤ２のキャップ８上に冷却管３を重ね合わせた構造を
有している。図示はしないが、モジュール基板１の主面
には、複数のチップキャリヤ２が所定の間隔を置いて実
装されている。[Embodiment 2] The semiconductor integrated circuit device of this embodiment 2 has a structure in which the cooling pipe 3 is superimposed on the cap 8 of the chip carrier 2 mounted on the main surface of the module substrate 1, as in the embodiment 1. have. Although not shown, a plurality of chip carriers 2 are mounted on the main surface of the module substrate 1 at predetermined intervals.
第２図に示すように、本実施例２のチップキャリヤ２に
おいては、キャップ８の上面中央部に設けられた凹ａ１
４内に熱伝導グリース１５を充填するとともに、この凹
溝１４内に、上記熱伝導グリース１５がキャップ８の横
方向に沿って熱膨張することのできるような隙間１７を
設けている。As shown in FIG. 2, in the chip carrier 2 of the second embodiment, a concave a1 provided at the center of the upper surface of the cap 8
4 is filled with thermally conductive grease 15, and a gap 17 is provided in this groove 14 so that the thermally conductive grease 15 can thermally expand along the lateral direction of the cap 8.
前記実施例１のように、凹溝１４内に熱伝導グリース１
５を隙間なく充填した場合には、熱伝導グリース１５が
冷却管３を持ち上げるように熱膨張するので、これによ
って生じたキャップ８と冷却管３の隙間を通じて熱伝導
グリース１５が凹溝１４外に流出する虞れがあった。こ
れに対して、凹溝１４内に前記隙間１７を設けた本実施
例２においては、熱伝導グリース１５がキャップ８の横
方向に沿って熱膨張するため、冷却管３が持ち上げられ
る虞れはない。従って、熱伝導グリース１５が凹溝１４
外に流出してパッケージ基板５の下面に流れ込むのを確
実に防止することができるので、ＣＣＢバンプ１２同士
の短絡をより確実に防止することができる。As in the first embodiment, thermally conductive grease 1 is placed in the groove 14.
5 is filled without any gaps, the thermally conductive grease 15 thermally expands to lift the cooling pipe 3, and the thermally conductive grease 15 flows out of the groove 14 through the gap created by this between the cap 8 and the cooling pipe 3. There was a risk of leakage. On the other hand, in the second embodiment in which the gap 17 is provided in the groove 14, the thermally conductive grease 15 thermally expands along the lateral direction of the cap 8, so there is no possibility that the cooling pipe 3 will be lifted. do not have. Therefore, the thermally conductive grease 15
Since it is possible to reliably prevent the liquid from flowing out and flowing into the lower surface of the package substrate 5, it is possible to more reliably prevent short circuits between the CCB bumps 12.
また、第２図に示すように、本実施例２のチップキャリ
ヤ２においては、冷却管３の下面に脚部１８が設けられ
ており、この脚部１８の底面とキャップ８の周縁部とが
互いに接触するようになっている。Further, as shown in FIG. 2, in the chip carrier 2 of the second embodiment, a leg portion 18 is provided on the lower surface of the cooling tube 3, and the bottom surface of this leg portion 18 and the peripheral edge of the cap 8 are connected. are coming into contact with each other.
上記脚部１８の底面は、その凸部と凹部との段差が、例
えば１０μｍ程度以下となるように平坦化されており、
キャップ８と冷却管３との接触面の密着性が極めて良好
となっている。これにより、冷却管３とキャップ８との
接触面を通じて冷却管３に伝達される熱量が前記実施例
１の場合よりも増大するので、半導体集積回路装置の冷
却効率をさらに向上させることができる。The bottom surface of the leg portion 18 is flattened so that the difference in level between the convex portion and the concave portion is, for example, about 10 μm or less,
The adhesion of the contact surface between the cap 8 and the cooling pipe 3 is extremely good. As a result, the amount of heat transferred to the cooling pipe 3 through the contact surface between the cooling pipe 3 and the cap 8 is increased compared to the case of the first embodiment, so that the cooling efficiency of the semiconductor integrated circuit device can be further improved.
なお、本実施例２の半導体集積回路装置は、上述した点
を除いては前記実施例１と同一の構成となっているため
、実施例１と同一部分の説明は省略する。Note that the semiconductor integrated circuit device of the second embodiment has the same configuration as the first embodiment except for the above-mentioned points, so a description of the same parts as the first embodiment will be omitted.
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は、前記実施例１．２に限
定されるものではなく、その要旨を逸脱しない範囲で種
々変更可能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to Examples 1 and 2, and can be modified in various ways without departing from the gist thereof. It goes without saying that there is.
前記実施例１では、ダイヤモンド粉末からなる熱伝導媒
体を含有させることによって、熱伝導グリースの熱伝導
率および粘性を高くしたが、例えばカーボン粉末などの
熱伝導媒体を含有させることによっても、熱伝導グリー
スの熱伝導率を高くすることができる。In Example 1, the thermal conductivity and viscosity of the thermally conductive grease were increased by including a thermally conductive medium made of diamond powder. The thermal conductivity of grease can be increased.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記の通りである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
（１）、ＣＣＢバンプを介してパッケージ基板の主面に
実装された半導体チップをキャップで気密封止してなる
パッケージをモジュール基板の主面に実装し、前記キャ
ップの上面に設けた凹溝内に熱伝導グリースを充填する
とともに、前記キャップの上面に冷却管を重合した本発
明の半導体集積回路装置によれば、キャップの温度が上
昇した際に熱伝導グリースがキャップの外壁を伝ってパ
ッケージ基板の下面に流れ込むのを抑制することができ
るので、パッケージ基板の下面に設けられたＣＣＢバン
プ同士の短絡を防止することができる。(1) A package consisting of a semiconductor chip mounted on the main surface of the package substrate via CCB bumps and hermetically sealed with a cap is mounted on the main surface of the module substrate, and the groove formed on the top surface of the cap is placed inside the package. According to the semiconductor integrated circuit device of the present invention, in which the cap is filled with thermally conductive grease and a cooling pipe is superimposed on the upper surface of the cap, when the temperature of the cap rises, the thermally conductive grease flows along the outer wall of the cap to the package substrate. Since it is possible to prevent the CCB bumps from flowing into the lower surface of the package substrate, it is possible to prevent short circuits between the CCB bumps provided on the lower surface of the package substrate.
（２）、上記した本発明の半導体集積回路装置において
、キャップの上面に設けた凹溝内に、熱伝導グリースが
キャップの横方向に沿って熱膨張することのできるよう
な隙間を設けることにより、熱伝導グリースが凹溝外に
流出してパッケージ基板の下面に流れ込むのを確実に防
止することができるので、ＣＣＢバンプ同士の短絡をよ
り確実に防止することができる。(2) In the semiconductor integrated circuit device of the present invention described above, by providing a gap in the groove provided on the top surface of the cap so that the thermally conductive grease can thermally expand along the lateral direction of the cap. Since it is possible to reliably prevent the thermally conductive grease from flowing out of the groove and into the lower surface of the package substrate, it is possible to more reliably prevent short circuits between the CCB bumps.
第１図は、本発明の一実施例である半導体集積回路装置
の要部断面図、
第２図は、本発明の他の実施例である半導体集積回路装
置の要部断面図である。
１・・・モジュール基板、２・・・チップキャリヤ、３
・・・冷却管、４，１２・・・ＣＣＢバンプ、５・・・
パッケージ基板、６・・・電極、７・・・半導体チップ
、８・・・キャップ、９・・・封止用半田、ｌＯ・・・
伝熱用半田、１１・・・冷媒流路、１３・・・内部配線
、１４・・・凹溝、１５・・・熱伝導グリース、１６・
・・メタライズ層、１７・・・隙間、１８・・・脚部、
Ｃ・・・冷媒。FIG. 1 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention. 1...Module board, 2...Chip carrier, 3
...Cooling pipe, 4,12...CCB bump, 5...
Package substrate, 6... Electrode, 7... Semiconductor chip, 8... Cap, 9... Sealing solder, lO...
Heat transfer solder, 11... Refrigerant channel, 13... Internal wiring, 14... Concave groove, 15... Thermal conductive grease, 16.
...Metalized layer, 17...Gap, 18...Legs,
C... Refrigerant.
Claims (1)
された半導体チップをキャップで気密封止してなるパッ
ケージを備え、前記パッケージをモジュール基板の主面
に実装するとともに、前記キャップの上面に冷却管を重
合してなる半導体集積回路装置であって、前記キャップ
の上面に凹溝を設け、前記凹溝内に熱伝導グリースを充
填したことを特徴とする半導体集積回路装置。 ２、前記凹溝内に、前記熱伝導グリースがキャップの横
方向に沿って熱膨張することのできるような隙間を設け
たことを特徴とする請求項１記載の半導体集積回路装置
。 ３、前記熱伝導グリースは、熱伝導媒体を含有している
ことを特徴とする請求項１記載の半導体集積回路装置。 ４、前記キャップと冷却管との接触面にＡｕのメタライ
ズ層を設けたことを特徴とする請求項１記載の半導体集
積回路装置。 ５、前記キャップと冷却管との接触面に平坦化処理を施
したことを特徴とする請求項１記載の半導体集積回路装
置。[Claims] 1. A package including a semiconductor chip mounted on the main surface of a package substrate via a CCB bump and hermetically sealed with a cap, the package being mounted on the main surface of a module substrate, A semiconductor integrated circuit device comprising a cooling pipe superimposed on the top surface of the cap, characterized in that a groove is provided in the top surface of the cap, and the groove is filled with thermally conductive grease. . 2. The semiconductor integrated circuit device according to claim 1, wherein a gap is provided in the groove so that the thermally conductive grease can thermally expand along the lateral direction of the cap. 3. The semiconductor integrated circuit device according to claim 1, wherein the thermally conductive grease contains a thermally conductive medium. 4. The semiconductor integrated circuit device according to claim 1, further comprising an Au metallized layer provided on a contact surface between the cap and the cooling pipe. 5. The semiconductor integrated circuit device according to claim 1, wherein a contact surface between the cap and the cooling pipe is flattened.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1317306A JPH03178154A (en) | 1989-12-06 | 1989-12-06 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1317306A JPH03178154A (en) | 1989-12-06 | 1989-12-06 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03178154A true JPH03178154A (en) | 1991-08-02 |
Family
ID=18086742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1317306A Pending JPH03178154A (en) | 1989-12-06 | 1989-12-06 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03178154A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0717440A3 (en) * | 1994-12-15 | 1997-11-26 | Hitachi, Ltd. | Cooling device of multi-chip module |
| WO2006087770A1 (en) * | 2005-02-15 | 2006-08-24 | Fujitsu Limited | Package unit |
| JP2008004745A (en) * | 2006-06-22 | 2008-01-10 | Denso Corp | Electronic apparatus |
| JP2011071550A (en) * | 2010-12-21 | 2011-04-07 | Denso Corp | Electronic apparatus |
-
1989
- 1989-12-06 JP JP1317306A patent/JPH03178154A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0717440A3 (en) * | 1994-12-15 | 1997-11-26 | Hitachi, Ltd. | Cooling device of multi-chip module |
| US5751062A (en) * | 1994-12-15 | 1998-05-12 | Hitachi, Ltd. | Cooling device of multi-chip module |
| WO2006087770A1 (en) * | 2005-02-15 | 2006-08-24 | Fujitsu Limited | Package unit |
| JPWO2006087770A1 (en) * | 2005-02-15 | 2008-07-03 | 富士通株式会社 | Package unit |
| US7800218B2 (en) | 2005-02-15 | 2010-09-21 | Fujitsu Limited | Package unit |
| JP4589960B2 (en) * | 2005-02-15 | 2010-12-01 | 富士通株式会社 | Package unit |
| JP2008004745A (en) * | 2006-06-22 | 2008-01-10 | Denso Corp | Electronic apparatus |
| JP4710735B2 (en) * | 2006-06-22 | 2011-06-29 | 株式会社デンソー | Manufacturing method of electronic device |
| JP2011071550A (en) * | 2010-12-21 | 2011-04-07 | Denso Corp | Electronic apparatus |
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