JPH03175727A - High voltage signal input circuit - Google Patents

Abstract

PURPOSE:To use only one MOS transistor with high dielectric strength by transmitting the output signal of an inverter to the gate of a MOS transistor, and supplying a low voltage source to the gate via a resistor. CONSTITUTION:When a high voltage input signal IN is stabilized at a low level, the source and the drain of the MOS transistor MH1 are set at the low levels, and the gate of it is set at a high level. When the high voltage input signal IN rises from the low level and exceeds the threshold of the inverter IV1, the MOS transistor MH1 is cut off, and the potential of the source goes to the one inproportional to the rise of the high voltage input signal IN. Since the resistance of the MOS transistor MH1 is low when the high voltage input signal IN is set at the low level, the transmission time of the signal can be remarkably shortened against the rise of it.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a high-voltage signal input circuit, and particularly to a circuit that transmits a high-voltage output signal of a circuit that operates on a high-voltage power supply to an internal circuit that operates on a low-voltage power supply. It relates to a high voltage signal input circuit.

[Conventional technology]

Conventionally, this type of high-voltage signal input circuit uses a high-voltage MOS transistor M, as shown in FIG. 3 as a first example.
The high-voltage inverter IV5, which is equipped with H2 and MH3 and operates on a high-voltage power supply (voltage Vo), receives an external high-voltage input signal IN, and outputs this from a high-voltage MOS transistor MT (equipped with a 4° MH5 and a low-voltage inverter). The signal is received by a low-voltage inverter IV6 that operates on a voltage power source (voltage VL), converts it into a low-voltage level signal, and transmits it to an internal circuit that operates on a low-voltage power source.

This circuit uses a high withstand voltage MO, which requires a large amount of area.
Since four S transistors are required, the chip area becomes large.

In addition, as a second example, in order to reduce the chip area, as shown in FIG.
2. ML3, a low voltage inverter IV7 that operates on a low voltage power supply, and a diode D3. A circuit has also been used in which a high voltage input signal IN from the outside is clamped between a ground potential and a low voltage power supply potential using a resistor D4 and a resistor R2, and is input to an internal circuit.

In this circuit, the value of the resistor R2 must be several hundred ohms, which increases the signal transmission time.

[Problem to be solved by the invention]

The conventional high-voltage signal input circuit described above has the drawback that the first example uses a large number of high-voltage MOS transistors, which increases the chip area and is not suitable for integrated circuits. R2 and diode D3. Since the configuration is such that the high voltage input signal IN is clamped with D4, a large amount of clamp current flows, and there is a risk that the circuit elements will be destroyed due to heat generation, and special heat dissipation treatment is required. Another drawback is that power consumption increases. Furthermore, if the value of the resistor R2 is increased in order to reduce the clamp current, there is a drawback that the signal transmission time becomes longer.

An object of the present invention is to provide a high voltage signal input circuit that can prevent damage to circuit elements, reduce power consumption, and shorten signal transmission time without increasing chip area. be.

[Means to solve the problem]

The high-voltage signal input circuit of the present invention includes a MOS transistor that has a high withstand voltage that can be operated with a high-voltage power supply and inputs a high-voltage signal from its drain, a source and a ground terminal of this MOS transistor, and a supply terminal of a low-voltage power supply. two diodes connected between the MOS transistors and clamping the source level of the MOS transistor to the ground potential or the voltage level of the low voltage power supply depending on the level of the high voltage signal; an inverter whose end is connected to the source of the MOS transistor and supplies an output signal to an internal circuit that operates on the low voltage power supply; and a resistor connected between the supply terminal of the low voltage power supply and the gate of the MOS transistor. and a non-inverting amplifier that operates on the low voltage power supply and transmits the output signal of the inverter to the gate of the MOS transistor.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment includes a MOS transistor MHI which has a high withstand voltage that can be operated with a high voltage power supply and inputs a high voltage input signal IN from its drain, and a source and ground terminal of this MOS transistor MHI and a low voltage power supply (voltage VL). The MOS transistor MH1 is connected between the supply terminal of
Two diodes DI, D2 clamp the source level to the ground potential or the voltage level of the low voltage power supply depending on the level of the high voltage input signal IN, and the input terminal of the MOS transistor MHI which operates from the low voltage power supply. an inverter IVI connected to the source and supplies an output signal to an internal circuit that operates on a low-voltage power supply; a resistor R1 connected between the supply terminal of the low-voltage power supply and the gate of the MOS transistor MHI; Inverter IV2. operates to form a non-inverting amplifier that transmits the output signal of inverter IV1 to the gate of MOS transistor MHI. IV3.

Next, the operation of this embodiment will be explained.

First, when the high voltage input signal IN is stable at a low level, the source and drain of the MOS transistor MHI are both at a low level, and the gate is at a high level.

As the high voltage input signal IN rises from a low level, the source potential also rises, and when it exceeds the threshold of inverter IVI, the low level potential is applied to the gate of transistor =6=MHI through inverter IV2゜rV3. join. M OS +- transistor M
HI is cut off and the potential at the source is no longer proportional to the rise of the high voltage input signal IN.

At this time, if the MOS transistor MHI is completely cut off, the source potential will not drop when the high voltage input signal IN falls from high level to low level, so the gate is connected to the low voltage power supply (voltage VL) by resistor R1. It is connected to the supply terminal to control the gate potential, and the MOS transistor M
The resistance of HI is made to be less than several hundred ohms.

The diodes D], , D2 function to release current through the high resistance MOS transistor MHI when the high voltage input signal N is at a high level.

The value of the resistor R1 is approximately the same as the on-resistance of the N-channel transistor of the inverter IV3, and the threshold voltage of the high-voltage MOS transistor MH is equal to the voltage Vl of the low-voltage power supply.
, about 115.

Therefore, when the high voltage input signal IN is at a low level, the MOS
Since the resistance of transistor MHI is small, the signal transmission time is significantly shortened for the rising edge.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

This embodiment is based on the inverter IV3 in the first embodiment.
and resistor R1 are combined to form one inverter IV4, thereby reducing the number of MOS transistors.

〔Effect of the invention〕

As explained above, the present invention provides a high withstand voltage MOS connected between the input terminal of the inverter and the input terminal of the high voltage input signal.
1- Connect a transistor, connect a clamping diode between the input terminal of the inverter and the ground terminal and the supply terminal of the low voltage power supply, transmit the output signal of the inverter to the gate of the MOS transistor, and connect a resistor to this gate. By supplying a low-voltage power supply through the circuit, only one high-voltage MOS transistor is required, so the chip area can be reduced, and the resistance value of this MOS transistor can be controlled, so the circuit element size can be reduced. This has the effect of preventing destruction, reducing power consumption, and shortening signal transmission time.

[Brief explanation of drawings]

1 and 2 are circuit diagrams showing the first and second embodiments of the present invention, respectively, and FIGS. 3 and 4 are circuit diagrams showing the first and second examples of the conventional high voltage signal input circuit, respectively. FIG. D1-D4...Diode, IVI-IV7...Inverter, MHI-MH5, MLI-ML3...MO
S) - transistor, R1, R2...resistance.

Claims (1)

[Claims] This MOS transistor has a high withstand voltage that can be operated with a high voltage power supply and inputs a high voltage signal from the drain.
connected between the source of the S transistor and a ground terminal and a supply terminal of the low voltage power supply, respectively, and clamps the level of the source of the MOS transistor to the ground potential or the voltage level of the low voltage power supply according to the level of the high voltage signal. an inverter that operates on the low-voltage power supply and whose input end is connected to the source of the MOS transistor to supply an output signal to an internal circuit that operates on the low-voltage power supply; and a supply terminal of the low-voltage power supply. and a resistor connected between the gate of the MOS transistor and a non-inverting amplifier that operates on the low voltage power supply and transmits the output signal of the inverter to the gate of the MOS transistor. Signal input circuit.