JPH03174517A - Production of liquid crystal display with thin film transistor - Google Patents

Production of liquid crystal display with thin film transistor

Info

Publication number
JPH03174517A
JPH03174517A JP1315811A JP31581189A JPH03174517A JP H03174517 A JPH03174517 A JP H03174517A JP 1315811 A JP1315811 A JP 1315811A JP 31581189 A JP31581189 A JP 31581189A JP H03174517 A JPH03174517 A JP H03174517A
Authority
JP
Japan
Prior art keywords
film
patterned
insulating film
display pixel
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1315811A
Other languages
Japanese (ja)
Other versions
JP2881868B2 (en
Inventor
Keizo Kobayashi
敬三 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP31581189A priority Critical patent/JP2881868B2/en
Publication of JPH03174517A publication Critical patent/JPH03174517A/en
Application granted granted Critical
Publication of JP2881868B2 publication Critical patent/JP2881868B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To prevent the occurrence of defects due to a short circuit by successively forming a gate insulating film, a first semiconductor film and a patterned etching stopper, further forming a second semiconductor film having low resistance and patterning the second and first semiconductor films. CONSTITUTION:A display pixel electrode 8 is formed on a glass substrate 1 and patterned, an SiO2 film is grown as an interlaminar insulating film 10 and Cr is formed and patterned to form gate metal wiring 2. A gate insulating film 3, a semiconductor Si film 4 and a silicon nitride film are successively formed and the silicon nitride film is patterned to form an etching stopper 5. An n<+>Si film 6 is grown, the films 6, 4 are patterned, a through hole 11 is pierced in the films 10, 3 on the electrode 8 and a source-drain metal 7 is formed. The film 6 is etched up to the etching stopper 5 under self-matching to pierce a channel opening 9 and a thin film transistor is completed. The occurrence of defects due to a short circuit between drain wiring and display pixel is prevented in a lithographing stage.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は薄膜トランジスタ(TPT)液晶ディスプレイ
(LCD)の製造方法に関し、特に短絡による欠陥が無
く、歩留りの良いTFTLCDを得るための製造方法に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a thin film transistor (TPT) liquid crystal display (LCD), and particularly relates to a manufacturing method for obtaining a TFTLCD that is free from defects due to short circuits and has a high yield.

〔従来の技術〕[Conventional technology]

従来、この種のTFTLCDにおけるボトムゲート型T
FT及び表示ピクセル部の製造方法の概略工程は第3図
(a)〜(f)に示すようになっていた。すなわち、ま
ず、ガラス基板工上にゲート金属配線2を形成する(第
3図(a))。その上にゲート絶縁膜3、半導体Si膜
4およびエツチングストッパ5を設ける(第3図(b)
)。次にn”si膜6を形成し半導体Si膜4と共にパ
ターニングする(第3図(C)〉。次にソース・ドレイ
ン金属7を形成する(第3図(d))。次に表示ピクセ
ル電極8を形成(第3図(e))し、最後にチャネルエ
ツチング開口部9を設けてTPTを完成する(第3図(
f)〉。
Conventionally, bottom gate type T in this type of TFTLCD
The schematic steps of the method for manufacturing the FT and display pixel section are shown in FIGS. 3(a) to 3(f). That is, first, a gate metal wiring 2 is formed on a glass substrate (FIG. 3(a)). A gate insulating film 3, a semiconductor Si film 4 and an etching stopper 5 are provided thereon (FIG. 3(b)).
). Next, an n'' Si film 6 is formed and patterned together with the semiconductor Si film 4 (FIG. 3(C)).Next, a source/drain metal 7 is formed (FIG. 3(d)).Next, the display pixel electrode 8 (Fig. 3(e)), and finally provide a channel etching opening 9 to complete the TPT (Fig. 3(e)).
f)〉.

第4図はこのようにして製作したTFTLCDの一画素
分を示す平面図であり、21はゲート配線、22はドレ
イン配線、23はTFT部、24は表示ピクセル部であ
る。
FIG. 4 is a plan view showing one pixel of the TFTLCD manufactured in this manner, in which 21 is a gate wiring, 22 is a drain wiring, 23 is a TFT section, and 24 is a display pixel section.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

第3図に示した従来のTFTLCDの製造方法ではゲー
ト配線はゲート絶縁膜で全面に渡り層間分離されている
ので、第4図でのゲート配線−表示ピクセル部間及びゲ
ート配線−トレイン配線間の短絡不良は無い。しかし、
ドレイン配線−表示ピクセル部間は層間膜が無いため、
リングラフィ工程でのゴミ等によるパターン不良を発生
し、欠陥不良を招くという欠点がある。例えば、ドレイ
ン配線と一つの表示ピクセル部の短絡は点欠陥となり、
一つの表示ピクセル部を介した隣接する2本のドレイン
配線の短絡は線欠陥となる。
In the conventional TFTLCD manufacturing method shown in FIG. 3, the gate wiring is separated between layers over the entire surface by a gate insulating film. There are no short circuit defects. but,
Since there is no interlayer film between the drain wiring and the display pixel part,
There is a drawback that pattern defects occur due to dust and the like during the phosphorography process, leading to defects. For example, a short circuit between the drain wiring and one display pixel becomes a point defect.
A short circuit between two adjacent drain wires via one display pixel portion becomes a line defect.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のTFTLCDの製造方法は、ガラス基板上に表
示ピクセル電極を設ける工程と、その上に層間絶縁膜と
パターニングしたゲート配線を設ける工程と、その上に
ゲート絶縁膜、第1の半導体膜およびパターニングした
エツチングストッパを設ける工程と、その上に第2の低
抵抗の半導体膜を設け前記第1の半導体膜と共にパター
ニングする工程と、前記表示ピクセル電極上にスルーホ
ールを開口しソース・ドレイン電極を設ける工程とを含
むことを特徴とする。なお、前記層間絶縁膜とゲート絶
縁膜は、同じ組成の膜であっても良い。
The method for manufacturing a TFTLCD of the present invention includes a step of providing a display pixel electrode on a glass substrate, a step of providing an interlayer insulating film and a patterned gate wiring thereon, and a step of providing a gate insulating film, a first semiconductor film and a patterned gate wiring thereon. A step of providing a patterned etching stopper, a step of providing a second low resistance semiconductor film thereon and patterning it together with the first semiconductor film, and opening a through hole on the display pixel electrode to form a source/drain electrode. It is characterized by including the step of providing. Note that the interlayer insulating film and the gate insulating film may have the same composition.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)〜(f)は本発明の第1の実施例を示すT
FTLCDの製造方法を示す縦断面図である。最初に表
示ピクセル電極8をI T D (IndiumTin
 0xide)にてガラス基板1上に形成しパターニン
グする(第1図(a))。次に層間絶縁膜10としてS
 i 02膜を成長し、引き続きcrを形成しパターニ
ングしてゲート金属配線2を形成する(第1図(b))
。次にゲート絶縁膜3と半導体Si膜4及びシリコン窒
化膜を形成し、シリコン窒化膜をパターニングしてエツ
チングストッパ5を形成する(第1図(C))。次にn
”Si膜6を成長し半導体Si膜4と共にパターニング
する(第1図(d))。次に表示ピクセル電極上にスル
ーホール11を開口しソース・ドレイン金属7を形成す
る(第1図(e〉)。最後に自己整合でn”Si膜6を
エツチングストッパ5までエツチングしチャネルエツチ
ング開口9を設けてTPTを完成する〈第1図(f))
FIGS. 1(a) to (f) show the first embodiment of the present invention.
FIG. 3 is a longitudinal cross-sectional view showing a method for manufacturing an FTLCD. First, the display pixel electrode 8 is made of ITD (Indium Tin).
oxide) on the glass substrate 1 and patterned (FIG. 1(a)). Next, as the interlayer insulating film 10, S
The i02 film is grown, and then a CR is formed and patterned to form the gate metal wiring 2 (FIG. 1(b)).
. Next, a gate insulating film 3, a semiconductor Si film 4, and a silicon nitride film are formed, and the silicon nitride film is patterned to form an etching stopper 5 (FIG. 1(C)). Then n
"The Si film 6 is grown and patterned together with the semiconductor Si film 4 (FIG. 1(d)). Next, through holes 11 are opened on the display pixel electrodes and source/drain metals 7 are formed (FIG. 1(e) ).Finally, the n''Si film 6 is self-aligned and etched to the etching stopper 5 to form a channel etching opening 9 to complete the TPT (Fig. 1(f)).
.

なお、表示ピクセル電極へのスルーホールの開口はゲー
ト配線へのスルーホールの開口と同工程で行なえるので
リングラフィの回数は従来方法と同じである。
Note that since the opening of the through hole to the display pixel electrode can be performed in the same process as the opening of the through hole to the gate wiring, the number of phosphorography operations is the same as in the conventional method.

第2図(a)〜(f>は本発明の第2の実施例を示すT
FTLCDの縦断面図である。本実施例では表示ピクセ
ル電極8上に成膜する層間絶縁膜としてゲート絶縁膜と
同組成層間絶縁[10’を用いる0例えばゲート絶縁膜
としてプラズマ気相成長法で200OAのシリコン窒化
膜を用いる際、層間絶縁膜10′にも同条件で200O
Aとシリコン窒化膜を成長する。この実施例では表示ピ
クセル電極8上のスルーホール11の開口は同組成の膜
の、エツチングなのでオーバーエッチが少く、開口形状
の制御が容易で段部での断線不良を低減できる利点があ
る。
FIGS. 2(a) to (f) show the second embodiment of the present invention.
FIG. 3 is a longitudinal cross-sectional view of the FTLCD. In this embodiment, an interlayer insulating film having the same composition as the gate insulating film [10'] is used as the interlayer insulating film formed on the display pixel electrode 8. For example, when a silicon nitride film of 200 OA is used as the gate insulating film by plasma vapor deposition. , 200O under the same conditions for the interlayer insulating film 10'.
A and a silicon nitride film are grown. In this embodiment, the openings of the through holes 11 on the display pixel electrodes 8 are formed by etching a film of the same composition, so that there is little overetching, and the opening shape can be easily controlled, which has the advantage of reducing disconnection defects at step portions.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明ではゲート配線、表示ピクセ
ル電極、ソース・ドレインとその配線とがそれぞれ層間
絶縁膜により層間分離されている。従って従来方法の欠
点であるリソグラフィ工程でのドレイン配線−表示ピク
セル間での短絡による欠陥不良が無い。又、ガラス基板
上に接してその上に表示ピクセル電極を形成してから、
ゲート配線及びソース・ドレイン部とその配線との形成
を行うので、TPTに関しては従来法と全たく同じく製
造出来、自由度がある。TFT′Pf性の安定性、信頼
性も従来法と同程度に保障できる。
As described above, in the present invention, the gate wiring, display pixel electrode, source/drain, and their wiring are separated from each other by an interlayer insulating film. Therefore, there is no defect caused by a short circuit between the drain wiring and the display pixel during the lithography process, which is a drawback of the conventional method. Also, after forming display pixel electrodes on and in contact with the glass substrate,
Since the gate wiring, source/drain portions, and their wiring are formed, the TPT can be manufactured in exactly the same manner as the conventional method, and there is a degree of freedom. The stability and reliability of TFT'Pf properties can be guaranteed to the same extent as the conventional method.

更に、一般に表示ピクセル電極のITO膜は通常100
0A前後と薄いため段部で断線しやすい。従ってガラス
基板の素子面上にパターニングを行う本発明では段部で
の断線不良が無いという効果がある。
Furthermore, the ITO film of the display pixel electrode is generally 100%
Because it is thin and around 0A, it is easy to break at the step. Therefore, the present invention in which patterning is performed on the element surface of a glass substrate has the advantage that there is no disconnection failure at the stepped portion.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(f)は本発明のTFTLCD図(a)
〜(f)は従来の製造方法の一例を示す縦断面図、第4
図は模式的なTFTLCDの平面図である。 1・・・ガラス基板、2・・・ゲート金属配線、3・・
・ゲート絶縁膜、4・・・半導体Si膜、5・・・エツ
チングストッパ 6・・・n”Si膜、7・・・ソース
ドレイン金属、8・・・表示ピクセル電極、9・・・チ
ャネルエツチング開口、10・・・層間絶縁膜、10’
・・・ゲート絶縁膜と同じ組成の層間絶縁膜、11・・
・スルーホール。
Figures 1 (a) to (f) are TFTLCD diagrams (a) of the present invention.
~(f) is a vertical cross-sectional view showing an example of a conventional manufacturing method, No. 4
The figure is a schematic plan view of a TFTLCD. 1...Glass substrate, 2...Gate metal wiring, 3...
・Gate insulating film, 4... Semiconductor Si film, 5... Etching stopper 6... n'' Si film, 7... Source/drain metal, 8... Display pixel electrode, 9... Channel etching Opening, 10...Interlayer insulating film, 10'
...Interlayer insulating film with the same composition as the gate insulating film, 11...
・Through hole.

Claims (1)

【特許請求の範囲】 1、ガラス基板上に表示ピクセル電極を設ける工程と、
その上に層間絶縁膜とパターニングしたゲート配線を設
ける工程と、その上にゲート絶縁膜、第1の半導体膜お
よびパターニングしたエッチングストッパを設ける工程
と、その上に第2の低抵抗の半導体膜を設け前記第1の
半導体膜と共にパターニングする工程と、前記表示ピク
セル電極上にスルーホールを開口しソース・ドレイン電
極を設ける工程とを含むことを特徴とする薄膜トランジ
スタ液晶ディスプレイの製造方法。 2、前記層間絶縁膜とゲート絶縁膜が同じ組成の膜であ
ることを特徴とする請求項1記載の薄膜トランジスタ液
晶ディスプレイの製造方法。
[Claims] 1. Providing a display pixel electrode on a glass substrate;
A step of providing an interlayer insulating film and a patterned gate wiring thereon, a step of providing a gate insulating film, a first semiconductor film, and a patterned etching stopper thereon, and a step of providing a second low-resistance semiconductor film thereon. A method for manufacturing a thin film transistor liquid crystal display, comprising the steps of forming and patterning the first semiconductor film together with the first semiconductor film, and forming a source/drain electrode by opening a through hole on the display pixel electrode. 2. The method of manufacturing a thin film transistor liquid crystal display according to claim 1, wherein the interlayer insulating film and the gate insulating film have the same composition.
JP31581189A 1989-12-04 1989-12-04 Method for manufacturing thin film transistor liquid crystal display Expired - Lifetime JP2881868B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31581189A JP2881868B2 (en) 1989-12-04 1989-12-04 Method for manufacturing thin film transistor liquid crystal display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31581189A JP2881868B2 (en) 1989-12-04 1989-12-04 Method for manufacturing thin film transistor liquid crystal display

Publications (2)

Publication Number Publication Date
JPH03174517A true JPH03174517A (en) 1991-07-29
JP2881868B2 JP2881868B2 (en) 1999-04-12

Family

ID=18069839

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31581189A Expired - Lifetime JP2881868B2 (en) 1989-12-04 1989-12-04 Method for manufacturing thin film transistor liquid crystal display

Country Status (1)

Country Link
JP (1) JP2881868B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100266189B1 (en) * 1996-06-21 2000-09-15 가네꼬 히사시 Amlcd panel and wiring designing method therefor
US6429456B1 (en) 1997-04-23 2002-08-06 Nec Corporation Thin-film transistor elements and methods of making same
KR100351440B1 (en) * 1999-12-31 2002-09-09 엘지.필립스 엘시디 주식회사 X-Ray Detecting Device and Fabricating Method Thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100266189B1 (en) * 1996-06-21 2000-09-15 가네꼬 히사시 Amlcd panel and wiring designing method therefor
US6429456B1 (en) 1997-04-23 2002-08-06 Nec Corporation Thin-film transistor elements and methods of making same
US6566174B1 (en) 1997-04-23 2003-05-20 Nec Corporation Thin-film transistor elements and methods of making same
KR100351440B1 (en) * 1999-12-31 2002-09-09 엘지.필립스 엘시디 주식회사 X-Ray Detecting Device and Fabricating Method Thereof

Also Published As

Publication number Publication date
JP2881868B2 (en) 1999-04-12

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