JPH03167626A - Selection circuit - Google Patents

Selection circuit

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Publication number
JPH03167626A
JPH03167626A JP30877389A JP30877389A JPH03167626A JP H03167626 A JPH03167626 A JP H03167626A JP 30877389 A JP30877389 A JP 30877389A JP 30877389 A JP30877389 A JP 30877389A JP H03167626 A JPH03167626 A JP H03167626A
Authority
JP
Japan
Prior art keywords
circuit
input signal
outputs
output
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30877389A
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Japanese (ja)
Inventor
Shigeo Sekiyama
関山　繁雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
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Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP30877389A priority Critical patent/JPH03167626A/en
Publication of JPH03167626A publication Critical patent/JPH03167626A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To miniaturize the scale of a selection circuit by selecting an input signal based on an AND secured between the output of a comparator which outputs an H level when the input signal is larger than the lower limit set value of a selecting range and the output of a comparator which outputs an H level when the input signal is smaller than the higher limit set value. CONSTITUTION:A comparator 1 outputs an H level when an input signal is equal to or larger than the lower limit set value A1 of a selecting range. Meanwhile a comparator 2 outputs an H level when the input signal is equal to or smaller than the higher limit set value A2 of the selecting range. The outputs of both comparators 1 and 2 are inputted to an AND circuit 3 and an input signal is selected within a set range. Thus the scale of a selection circuit can be miniaturized with no change even when a selecting range is large.

Description

【発明の詳細な説明】 〔概　要］ 入力信号が、第１の設定値Ａ１より大きいか等しく、第
２の設定値Ａ２より小さいか等しい時出力信号を出力す
る選択回路に関し、 同じビット数の入力信号の中よりある範囲の数を選択す
る場合、選択する範囲が変化しても回路規模は変化せず
、選択する範囲が広い時回路規模が従来の選択回路より
小さく出来る選択回路の提供を目的とし、 入力信号が入力し、第１の設定値Ａ１と比較し、大きい
か等しい時Ｈレベルを出力する第１の比較器と、 該入力信号が入力し、第２の設定値Ａ２と比較し、小さ
いか等しい時Ｈレベルを出力する第２の比較器と、 該第１．第２の比較器の出力の論理積をとり結果を出力
する論理積回路よりなる構成とする。[Detailed Description of the Invention] [Summary] Regarding a selection circuit that outputs an output signal when an input signal is greater than or equal to a first setting value A1 and smaller than or equal to a second setting value A2, To provide a selection circuit that, when selecting a number in a certain range from input signals, does not change the circuit size even if the selection range changes, and can make the circuit size smaller than conventional selection circuits when the selection range is wide. A first comparator which receives an input signal, compares it with a first set value A1, and outputs an H level when the input signal is greater or equal; and a first comparator which receives an input signal and compares it with a second set value A2. and a second comparator that outputs an H level when the first and second comparators are smaller than or equal to each other; The configuration includes an AND circuit that performs an AND operation on the outputs of the second comparator and outputs the result.

［産業上の利用分野］ 本発明は、伝送装置の、例えば１９３ビットよりなるフ
レームより、１０番目と５０番目の間の信号を選択する
場合等に使用する、入力信号が、第１の設定値Ａ１より
大きいか等しく、第２の設定値Ａ２より小さいか等しい
時出力信号を出力する選択回路の改良に関する。[Industrial Field of Application] The present invention provides an input signal used when selecting a signal between the 10th and 50th from a frame consisting of 193 bits of a transmission device, for example. The present invention relates to an improvement in a selection circuit that outputs an output signal when it is greater than or equal to A1 and less than or equal to a second set value A2.

〔従来の技術〕[Conventional technology]

第７図は従来例の１０〜５０迄の間の数を選択する選択
回路のブロック図である。FIG. 7 is a block diagram of a conventional selection circuit for selecting a number between 10 and 50.

従来の１０〜５０迄の間の数を選択する選択回路では、
第７図に示す如く、１０の選択器５０より、５０の選択
器５１迄の都合４１個の選択器を持ち、夫々の出力をオ
ア回路５２に入力して出力するようにしている。In the conventional selection circuit that selects a number between 10 and 50,
As shown in FIG. 7, there are a total of 41 selectors, from 10 selectors 50 to 50 selectors 51, and their respective outputs are input to an OR circuit 52 and output.

例えば、５０の場合の２進数の信号は“００１１００１
０”の８ビットとなるので、５０の選択器５１のアンド
回路６０には上位４ビットを入力し、且つＭＳＢ及び２
つめの入力は反転して入力させ、アンド回路６１には下
位４ビットを入力し、且つ上位及び２つめ及びＬＳＢの
入力は反転して入力するようにしておく。For example, the binary signal for 50 is “0011001
Since there are 8 bits of 0'', the upper 4 bits are input to the AND circuit 60 of the selector 51 of 50, and the MSB and 2
The third input is inverted and inputted, the lower 4 bits are inputted to the AND circuit 61, and the upper, second and LSB inputs are inverted and inputted.

すると、入力信号が５０の時は、アンド回路６２より１
を出力する。Then, when the input signal is 50, the AND circuit 62 outputs 1
Output.

又１０の場合の２進数の信号は“”００００１０ｌＯ”
の８ビットとなるので、１００選択器５０のアンド回路
６３には上位４ビットを入力し、且つ４ビット共反転し
て入力させ、アンド回路６４には下位４ビットを入力し
、且つ上位より２つめ及びＬＳＢの入力は反転して入力
するようにしておく。Also, the binary signal for 10 is “”000010lO”
Therefore, the upper 4 bits are inputted to the AND circuit 63 of the 100 selector 50, and the 4 bits are inverted and inputted, the lower 4 bits are inputted to the AND circuit 64, and the upper 2 bits are inputted. The claw and LSB inputs are inverted and input.

すると、入力信号がＩＯの時は、アンド回路６５よりｌ
を出力する。Then, when the input signal is IO, the AND circuit 65
Output.

従って、１０〜５０迄を選択しようとすると、アンド回
路３個よりなる選択器を都合４１個と、４ｌ個の信号を
入力するオア回路５２を設ければ選択することが出来る
。Therefore, if you want to select from 10 to 50, you can do so by providing a total of 41 selectors each consisting of three AND circuits and an OR circuit 52 that receives 41 signals.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、従来の選択回路は、同しビット数の入力
信号の中よりある範囲の数を選択する場合、選択する範
囲の数に略比例して回路規模が増大し、選択する範囲が
広い時回路規模が非常に大きくなる問題点がある。However, in conventional selection circuits, when selecting a certain range of numbers from input signals with the same number of bits, the circuit size increases approximately in proportion to the number of selected ranges, and when the selection range is wide, the circuit size increases. The problem is that the scale is very large.

本発明は、同じビット数の入力信号の中よりある範囲の
数を選択する場合、選択する範囲が変化しても回路規模
は変化せず、選択する範囲が広い時回路規模が従来の選
択回路より小さく出来る選択回路の提供を目的としてい
る。In the present invention, when selecting a number in a certain range from input signals having the same number of bits, the circuit size does not change even if the selected range changes, and when the selection range is wide, the circuit size is smaller than that of the conventional selection circuit. The purpose is to provide a selection circuit that can be made smaller.

〔課題を解決するための手段〕[Means to solve the problem]

第１図は本発明の原理ブロック図である。 FIG. 1 is a block diagram of the principle of the present invention.

第１図に示す如く、選択回路を、入力信号が入力し、第
１の設定値Ａｔと比較し、大きいか等しい時Ｈレベルを
出力する第１の比較器１と、該入力信号が入力し、第２
の設定値Ａ２と比較し、小さいか等しい時Ｈレベルを出
力する第２の比較器２と、 該第１，第２の比較器１．　　２の出力の論理積をとり
結果を出力する論理積回路３より構戒する。As shown in FIG. 1, the selection circuit includes a first comparator 1 which receives an input signal, compares it with a first set value At, and outputs an H level when the input signal is greater than or equal to the first set value At. , second
A second comparator 2 which compares with a set value A2 and outputs an H level when it is smaller or equal; and the first and second comparators 1. 2, and outputs the result from the AND circuit 3.

〔作　用〕[For production]

本発明の選択回路は、入力信号が、選択する範囲の下限
の設定値Ａｌに等しいか大きい時Ｈレヘルを出力する第
１の比較器ｌと、入力信号が、選択する範囲の上限の設
定値Ａ２に等しいか小さい時Ｈレベルを出力する第２の
比較器２と、論理積回路３にて構或され、第１，第２の
比較器１．　　２は、入力信号と設定値を比較するもの
であるので、入力信号のビット数が同じなら、選択する
範囲を変化する為に設定値を変えても回路規模は変化し
ない。The selection circuit of the present invention includes a first comparator l that outputs H level when the input signal is equal to or greater than the lower limit setting value Al of the selection range; It consists of a second comparator 2 that outputs an H level when it is equal to or smaller than A2, and an AND circuit 3, and the first and second comparators 1. 2 compares the input signal and the set value, so if the number of bits of the input signal is the same, the circuit scale will not change even if the set value is changed to change the selection range.

よって、選択する範囲が広くなると、従来の選択回路に
比し回路規模は相対的に小さくなる。Therefore, when the selection range becomes wider, the circuit scale becomes relatively smaller than the conventional selection circuit.

〔実施例〕〔Example〕

第２図は本発明の実施例の４ビット入力信号の場合の選
択回路のブロック図、第３図は第２図の単位回路の各部
の値を示す図、第４図は１例の第２図の選択回路への入
力信号とアンド回路の出力を示す図、第５図は本発明の
実施例の８ビント入力信号の場合の選択回路のブロック
図、第６図はｌ例の第５図の選択回路への入力信号と比
較器の出力を示す図である。FIG. 2 is a block diagram of a selection circuit in the case of a 4-bit input signal according to an embodiment of the present invention, FIG. 3 is a diagram showing the values of each part of the unit circuit in FIG. 2, and FIG. 5 is a block diagram of the selection circuit in the case of an 8-bit input signal according to the embodiment of the present invention, and FIG. 6 is a diagram showing the input signal to the selection circuit and the output of the AND circuit. FIG. 2 is a diagram showing an input signal to a selection circuit and an output of a comparator.

第２図の比較器１は、入力信号が設定値Ａ１より大きい
か等しい時１を出力する４ビット比較器１−１とオア回
路３２より構或され、比較器２は、入力信号が設定値Ａ
２より小さいか等しい時１を出力する４ビット比較器２
−１とオア回路３３より構威され、オア回路３２．３３
の出力はアンド回路３に入力し、入力信号が設定値Ａ１
〜Ａ２の範囲にある時アンド回路３より１を出力するも
のである。The comparator 1 in FIG. 2 is composed of a 4-bit comparator 1-1 that outputs 1 when the input signal is greater than or equal to the set value A1, and an OR circuit 32. A
4-bit comparator 2 that outputs 1 when less than or equal to 2
-1 and OR circuit 33, OR circuit 32.33
The output of is input to AND circuit 3, and the input signal is the set value A1
-A2, the AND circuit 3 outputs 1.

以下細部につき説明する。The details will be explained below.

４ビット比較器１−１．２−１は、第２図に示す如く、
４ビントの入力信号Ｂ３．Ｂ２，Ｂｌ，ＢＯの各ビット
と、４ビットの設定値Ａ１３，Ａ１２，Ａｌ　ｌ，ＡＩ
０，４ビットの設定値Ａ２３，Ａ２　２，Ａ’２　１，
Ａ２　０の各ビットを比較する夫々４つの単位回路と、
アンド回路２０〜２３及びオア回路３０、アンド回路２
４〜２７及びオア回路３１よりなっている。The 4-bit comparator 1-1.2-1 is as shown in FIG.
4-bint input signal B3. B2, Bl, BO bits and 4-bit setting values A13, A12, Al l, AI
0, 4-bit setting value A23, A2 2, A'2 1,
four unit circuits each comparing each bit of A20;
AND circuits 20 to 23, OR circuit 30, AND circuit 2
4 to 27 and an OR circuit 31.

この単位回路はアンド回路１０．１１とノア回路１２よ
りなっており、入力信号と設定値の各値に対する、アン
ド回路１０．１１の出力，ノア回路ｌ２の出力を示すと
、第３図に示す如くなり、設定値と入力信号が等しい時
はアンド回路１０１ｌの出力は夫々０、ノア回路ｌ２の
出力はｌとなり、設定値がＩで入力信号がＯの時は、ア
ンド回路１０の出力は０，アンド回路ｌ１の出力は１，
ノア回路１２の出力は０、設定値が０で入力信号が１の
時は、アンド回路１０の出力は１，アンド回路１１の出
力はＯ．ノア回路ｌ２の出力も０となる。This unit circuit consists of an AND circuit 10.11 and a NOR circuit 12, and the output of the AND circuit 10.11 and the output of the NOR circuit l2 for each input signal and set value are shown in Figure 3. When the set value and the input signal are equal, the output of the AND circuit 101l is 0, the output of the NOR circuit l2 is 1, and when the set value is I and the input signal is O, the output of the AND circuit 10 is 0. , the output of the AND circuit l1 is 1,
The output of the NOR circuit 12 is 0. When the set value is 0 and the input signal is 1, the output of the AND circuit 10 is 1, and the output of the AND circuit 11 is O. The output of the NOR circuit l2 also becomes 0.

そこで、設定値Ａ１３，Ａ１２，Ａｌ　ｌ，ＡＩＯを３
である“０１０１″とし、入力信号か２，３．４の場合
のアンド回路２０，２１，２２．２３の出力及び、設定
値Ａ２３，Ａ２２，Ａ２１Ａ２０を１３である“１１０
１”とし、入力信号か１２，１３．１４の場合のアンド
回路２４，２５．２６．２７の出力を求めると、第４図
（Ａ）（Ｂ）に示す如くなる。Therefore, set values A13, A12, Al l, AIO are set to 3.
The outputs of the AND circuits 20, 21, 22.23 and the set values A23, A22, A21A20 when the input signal is 2, 3.4 are set to "110" which is 13.
1'' and the outputs of the AND circuits 24, 25, 26, and 27 when the input signals are 12, 13, and 14 are as shown in FIGS. 4(A) and 4(B).

従って４ビット比較器１−１では、入力信号が設定値に
等しい時はアンド回路２３の出力はｌ、入力信号が設定
値より大きい時はオア回路３０の出力は１となり、比較
器１のオア回路３２の出力は入力信号が設定値に等しい
か大きい時１になる。Therefore, in the 4-bit comparator 1-1, when the input signal is equal to the set value, the output of the AND circuit 23 is 1; when the input signal is greater than the set value, the output of the OR circuit 30 is 1; The output of circuit 32 will be 1 when the input signal is equal to or greater than the set value.

又４ビ・冫ト比較器２−１では、入力信号が設定値に等
しい時はアンド回路２７の出力は１、入力信号が設定値
より小さい時はオア回路３１の出力は１となり、比較器
２のオア回路３３の出力は入力信号が設定値に等しいか
小さい時ｌになる。In addition, in the 4-bit digital comparator 2-1, when the input signal is equal to the set value, the output of the AND circuit 27 is 1, and when the input signal is smaller than the set value, the output of the OR circuit 31 is 1, and the comparator The output of the 2 OR circuit 33 becomes 1 when the input signal is equal to or smaller than the set value.

よって、アンド回路３の出力は、入力信号が３と１３の
間にあれば出力はｌとなる。Therefore, the output of the AND circuit 3 is 1 if the input signal is between 3 and 13.

次に、入力信号が８ビットの場合につき第５図を用い説
明する。Next, the case where the input signal is 8 bits will be explained using FIG.

この場合は、第５図に示す如く、先に説明した、入力信
号が設定値に等しいか大きい時１を出力する４ビット比
較器を、ＬＳＢより４ビット迄の１−１と、５ビットよ
り８ピント迄の４の２個用い、又入力信号が設定値に等
しいか小さい時１を出力する４ビット比較器を、ＬＳＢ
より４ビット迄の２−１と、５ビットより８ビット迄の
５の２個用い、４ビット比較器１−１．４の入力信号が
設定値ＡＩに等しい時１を出力する端子と、入力信号が
設定値ＡＩより大きい時１を出力する端子を夫々第５図
に示す如くアンド回路４０，４１オア回路４４の入力に
接続し、又４ビット比較器２−１．５の入力信号が設定
値Ａ２に等しい時１を出力する端子と、入力信号が設定
値Ａ２より小さい時１を出力する端子を夫々第５図に示
す如くアンド回路４２．４３，オア回路４５の入力に接
続する。In this case, as shown in Fig. 5, the 4-bit comparator that outputs 1 when the input signal is equal to or greater than the set value, as described above, is connected to 1-1 from the LSB to 4 bits, and from 5 bits to The LSB uses two 4-bit comparators up to 8 pins, and a 4-bit comparator that outputs 1 when the input signal is equal to or smaller than the set value.
Using two terminals, 2-1 for up to 4 bits and 5 for up to 8 bits, a terminal outputs 1 when the input signal of 4-bit comparator 1-1.4 is equal to the set value AI, and an input terminal. The terminals that output 1 when the signal is greater than the set value AI are connected to the inputs of the AND circuits 40 and 41 and the OR circuit 44, respectively, as shown in FIG. 5, and the input signal of the 4-bit comparator 2-1.5 is set. A terminal that outputs 1 when the input signal is equal to the value A2 and a terminal that outputs 1 when the input signal is smaller than the set value A2 are connected to the inputs of AND circuits 42 and 43 and OR circuit 45, respectively, as shown in FIG.

そして、オア回路４４．４５の出力をアンド回路３に入
力し、アンド回路３より、入力信号が設定値ＡｌとＡ２
の範囲の間にあれば１を出力するようにする。Then, the outputs of the OR circuits 44 and 45 are input to the AND circuit 3, and the input signals from the AND circuit 3 are the set values Al and A2.
If it is between the ranges, output 1.

第５図の場合で、設定値Ａ１７〜ＡＩＯを、１０の“０
０００１０１０”とし、入力信号Ｂ７〜ＢＯが９，１０
．１１の場合の比較器４．１−１のＡＩ＜Ｂ，Ａ１＝Ｂ
の端子の出力を求めると、第６図（Ａ）に示す如くなり
、オア回路４４の出力は、入力信号が９の時は０、１０
．１１の時はｌとなる。In the case of Fig. 5, set values A17 to AIO are set to 10 “0”.
0001010", and the input signals B7 to BO are 9,10
．． Comparator 4.1-1 AI<B, A1=B in case 11
When the output of the terminal is determined, it becomes as shown in FIG. 6(A), and the output of the OR circuit 44 is 0 when the input signal is 9,
．． When it is 11, it becomes l.

又設定値Ａ２７〜Ａ２０を、５０の゛００ｌ１００１０
’“とし、入力信号８７〜ＢＯが４９．５０．５１の場
合の比較器５．２−１のＡ２＞Ｂ，Ａ２＝Ｂの端子の出
力を求めると、第６図（Ｂ）に示す如くなり、オア回路
４５の出力は、入力信号が５１の時は０、５０．４９の
時は１となる。Also, change the setting values A27 to A20 to 50゛00l10010
''', and when the input signals 87 to BO are 49.50.51, the output of the terminal of comparator 5.2-1 where A2>B and A2=B is determined, as shown in Fig. 6 (B). The output of the OR circuit 45 is 0 when the input signal is 51, and 1 when the input signal is 50.49.

従って、入力信号が１０〜５０の間であればアンド回路
３の出力はｌとなる。Therefore, if the input signal is between 10 and 50, the output of the AND circuit 3 will be l.

即ち、第２図，第５図に示す如く、入力信号のビット数
が同じであれば、選択範囲が広くとも回路規模は変化し
ない。That is, as shown in FIGS. 2 and 5, if the number of input signal bits is the same, the circuit scale will not change even if the selection range is wide.

又第５図の選択回路と第７図の従来例の選択回路の回路
規模を比較すると、選択範囲が２４程度で等しくなり、
これ以上では、本発明の選択回路の回路規模は小さくな
り、選択範囲が広くなる程相対的に益々本発明の選択回
路の回路規模は小さくなる。Furthermore, when comparing the circuit scales of the selection circuit shown in FIG. 5 and the conventional selection circuit shown in FIG.
Above this, the circuit scale of the selection circuit of the present invention becomes small, and as the selection range becomes wider, the circuit scale of the selection circuit of the present invention becomes relatively smaller.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明せる如く本発明によれば、ビット数が同
じ入力信号の中より、ある範囲の数を選択する場合、選
択範囲が変化しても回路規模が変化せず、選択範囲が広
くなると従来の選択回路より益々回路規模を小さく出来
る効果がある。As explained in detail above, according to the present invention, when selecting a number within a certain range from among input signals having the same number of bits, the circuit scale does not change even if the selection range changes, and when the selection range becomes wider. This has the effect of making the circuit scale smaller than the conventional selection circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の原理ブロック図、 第２図は本発明の実施例の４ビット入力信号の場合の選
択回路のブロック図、 第３図は第２図の単位回路の各部の値を示す図、第４図
はｌ例の第２図の選択回路への入力信号とアンド回路の
出力を示す図、 第５図は本発明の実施例の８ビット入力信号の場合の選
択回路のブロック図、 第６図はｌ例の第５図の選択回路への入力信号と比較器
の出力を示す図、 第７図は従来例の１０〜５０迄の間の数を選択する選択
回路のブロック図である。 図において、 １，２は比較器、 １−１．２−１．４．５は４ビット比較器、３，１０．
１１．２０〜２７．４０〜４３．６０〜６５はアンド回
路、 ３０〜３３．４４．４！），５２はオア回路、５０．５
１は選択器を示す。 本発明の原理ブロック図 第　１　図 第２園の単位回錯のル卸の値を示す図 第　３　図 比 較 器 １ 側 比 較 否Ｓ ２ Ｉ貝１１ １伊１の第２図の選ｙ．同路への入力信号とアジト回路
の出力亙示ナ図第　４　図 ネ洟明引役鯨絶例の８ピント入力信号の場合の忍状回路
のプロソク図第　　５　　図Figure 1 is a block diagram of the principle of the present invention. Figure 2 is a block diagram of a selection circuit in the case of a 4-bit input signal according to an embodiment of the present invention. Figure 3 shows the values of each part of the unit circuit in Figure 2. 4 is a diagram showing the input signal to the selection circuit of FIG. 2 and the output of the AND circuit in an example, and FIG. 5 is a block diagram of the selection circuit in the case of an 8-bit input signal according to the embodiment of the present invention. , Fig. 6 is a diagram showing the input signal to the selection circuit of Fig. 5 and the output of the comparator in an example, and Fig. 7 is a block diagram of a selection circuit for selecting a number between 10 and 50 in the conventional example. It is. In the figure, 1 and 2 are comparators, 1-1.2-1.4.5 are 4-bit comparators, 3, 10.
11.20~27.40~43.60~65 are AND circuits, 30~33.44.4! ), 52 is an OR circuit, 50.5
1 indicates a selector. A block diagram of the principle of the present invention. FIG. 1. FIG. 2. A diagram showing the value of the unit circuit of the garden. FIG. 3. Figure 4 shows the input signal to the same circuit and the output of the hideout circuit.

Claims (1)

【特許請求の範囲】 入力信号が、第１の設定値Ａ１より大きいか等しく、第
２の設定値Ａ２より小さいか等しい時出力信号を出力す
る選択回路において、 入力信号が入力し、該第１の設定値Ａ１と比較し、大き
いか等しい時Ｈレベルを出力する第１の比較器（１）と
、 該入力信号が入力し、該第２の設定値Ａ２と比較し、小
さいか等しい時Ｈレベルを出力する第２の比較器（２）
と、 該第１、第２の比較器（１、２）の出力の論理積をとり
結果を出力する論理積回路（３）よりなることを特徴と
する選択回路。[Claims] In a selection circuit that outputs an output signal when an input signal is greater than or equal to a first setting value A1 and less than or equal to a second setting value A2, a first comparator (1) which outputs an H level when the input signal is inputted, compares it with a set value A1, and outputs an H level when the input signal is greater than or equal to the second set value A2; Second comparator (2) outputting the level
A selection circuit comprising: an AND circuit (3) that performs an AND operation on the outputs of the first and second comparators (1, 2) and outputs the result.
JP30877389A 1989-11-28 1989-11-28 Selection circuit Pending JPH03167626A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30877389A JPH03167626A (en) 1989-11-28 1989-11-28 Selection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30877389A JPH03167626A (en) 1989-11-28 1989-11-28 Selection circuit

Publications (1)

Publication Number Publication Date
JPH03167626A true JPH03167626A (en) 1991-07-19

Family

ID=17985130

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30877389A Pending JPH03167626A (en) 1989-11-28 1989-11-28 Selection circuit

Country Status (1)

Country Link
JP (1) JPH03167626A (en)

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