JPH03166615A - Initialization factor analyzing circuit - Google Patents

Abstract

PURPOSE:To constitute the circuit so that it is unnecessary to execute reloading to a memory in the case partial reset is enough by constituting the circuit so that in the case reset is applied to a device, its reset factor can be discriminated by a host software. CONSTITUTION:A power-on reset detection bit e2, a factor A reset detection bit a2, a factor B reset detection bit b2, and a factor C reset detection bit c2 are inputted to an encoder 30. The encoder 30 encoders states of this power-on reset detection bit e2 and the factor A - C reset detection bits a2 - c2 to the number of bits of the necessary minimum and outputs them to a data bus 40. Accordingly, reset detection information encoded by the encoder 30 can be transferred to a software in a form which can identify its factor. In such a way, in the case partial reset is enough, the memory can be cleared except a specific part, therefore, it is unnecessary to execute reloading to the memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an initialization factor analysis circuit for transmitting reset information to higher-level software.

[Conventional technology]

Conventionally, there is a reset information transmission circuit that transmits reset information to higher-level software. Further, some of these reset information transmission circuits transmit reset information when there are a plurality of reset factors. In such a reset information transmission circuit, the presence or absence of a reset is transmitted to the higher-level software by, for example, performing a logical product of reset signals for each factor.

[Problem to be solved by the invention]

In the conventional reset information transmission circuit described above, only the presence or absence of a reset is transmitted to the higher-level software, ignoring the cause of the reset. Therefore, even if a reset is detected, the higher-level software cannot identify its cause. Furthermore, even in the case of a reset that would normally only require a partial memory clear, there is a drawback in that the entire memory must be cleared once and then the necessary data must be reloaded.

An object of the present invention is to eliminate such drawbacks and provide an initialization factor analysis circuit that can analyze the factors of a reset signal.

[Means to solve the problem]

The present invention is an initialization factor analysis circuit that transmits reset detection information to higher-level software when a device has multiple reset factors, and the present invention comprises a holding means for holding a reset signal for each factor, and a holding means for holding a reset signal for each of the holding means. and a conversion means for encoding reset detection information indicated by the state and transmitting it to the higher-level software, and when the device is reset, the reset cause can be identified by the higher-level software.

In the initialization factor analysis circuit of the present invention described above, it is preferable that the holding means is a flip-flop and the converting means is an encoder.

Further, in the above-mentioned initialization factor analysis circuit of the present invention, which includes a flip-flop and an encoder, it is preferable to include a register that holds a signal instructing clearing of reset detection information and resets each flip-flop.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The initialization factor analysis circuit shown in FIG. 1 includes flip-flops 11 to 14, a register 20, an encoder 30, and a data bus 40.

Such an initialization factor analysis circuit transmits reset information to higher-level software when there are multiple reset factors in the device. That is, this initialization factor analysis circuit uses a power-on reset signal e, and reset signals b. Input xc,.

Flip-flop 11 is a flip-flop for storing a power-on reset signal. Furi・Flop Flop 1
A power-on reset signal e1 is input to the terminal S of the power-on reset signal e1. The flip-flop l1 then outputs the power-on reset detection bit e2 to the encoder 30.

The flip-flop 12 is a flip-flop that stores lyse/destruct factor A. The terminal S of the flip-flop 12 receives a reset signal a. is input. The flip-flop 12 then outputs the cause A reset detection bit a, to the encoder 30.

Flip-flop l3 is a reset factor B storage flip-flop. The terminal S of the fritub 13 has
A reset signal b+ due to factor B is input. and,
Flip-flop 13 has cause B reset detection bit b
2 is output to the encoder 30.

The flip-flop 14 is a reset factor C storage flip-flop. Furi Nfu Furo Fuku 14
A reset signal C due to a factor C is manually input to the terminal S of the . Then, the flip-flop l4 outputs the cause C reset detection bit C2 to the encoder 30.

Register 20 is a reset clear instruction register. A reset clear instruction signal d is input to the register 20. Then, the register 20 sends the reset factor detection bit clear signal d2 to the flip-flops 11 to 14.
output to terminal R of each.

The encoder 30 encodes the reset detection information for each factor and outputs the encoded reset detection information to the data bus 40 . That is, the encoder 30 generates reset detection information based on the power-on reset detection bit e2+factor A reset detection bit al+factor B reset detection bit b2, and factor C reset detection bit C2.

Next, the operation of this initialization factor analysis circuit will be explained.

When a power-on reset is applied, the power-on reset signal storage flip-flop 11 holds the change in the power-on reset signal e+, and the power-on reset signal e+ is held by the power-on reset signal storage flip-flop 11.
Reset detection bit e2 is set. Also, other factors A-C
Similarly, when a reset is applied, changes in reset signals a, ~c, due to factors A-C are changed to reset factors A-C.
The C storage flip-flops 12 to 14 hold, and the factor A-
C reset detection bit at~C2 is set.

Power-on reset detection bit ex, cause A reset detection bit a2, cause B reset detection bit b2,
The factor C reset detection bit c2 is manually input to the encoder 30. The encoder 30 encodes the states of the power-on reset detection bit e2 and the cause A-C reset detection bits as to c2 into the minimum necessary number of bits, and outputs the code to the data bus 40. Thereby, the reset detection information encoded by the encoder 30 can be transmitted to the software in a form that allows the cause of the reset detection information to be identified.

The reset clear instruction register 20 is used when it is desired to clear reset detection information to higher-level software, such as when processing for a reset ends on the software side.

That is, when the reset clear instruction signal d is input to the reset clear instruction register 20, the reset factor detection bit clear signal d2 is generated. This reset factor detection bit clear signal d2 is applied to the power-on reset signal storage flip-flop 1l and the reset factor A~
It is connected to the reset terminal R of the C storage flip-flops 12-14.

As a result, when the reset clear instruction signal d1 instructs reset clear, the power-on reset detection bit e2 and cause A-C reset detection bits {aX~c2} are all cleared, and the reset detection information on the data path 40 is also cleared. be done.

In this way, the reset factor storage circuit of this embodiment is
A flip-flop that holds reset signals for each factor,
It includes an encoder that encodes reset detection information for each factor and outputs it to the data path, and a register that holds a signal that indicates reset information. When the device is reset, the cause of the reset can be identified by the host software.

〔Effect of the invention〕

As explained above, the present invention utilizes a flip-flop that holds a reset signal for each factor and encodes reset detection information for each factor in transmitting information to upper-level software when a device has multiple reset factors. It is equipped with an encoder that outputs to the data path and a register that holds a signal that instructs to clear the reset information, so that when the device is reset, the cause of the reset can be identified by the higher-level software. In cases where a partial reset such as a reset by a monitoring timer in the event of a runaway is sufficient, the memory can be cleared except for a specific portion, which has the effect of eliminating the need to reload the memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1l... Power-on reset signal storage flip-flop 12... Reset factor A storage flip-flop 3, 14, 20, 30, 40. Register/encoder/data path for pre/reset clear instruction

Claims (3)

[Claims] (1) An initialization factor analysis circuit that transmits reset detection information to higher-level software when there are multiple reset factors in the device, comprising a holding means for holding a reset signal for each factor, and a holding state of each of the holding means. and converting means for encoding reset detection information indicated by and transmitting it to the upper software, and when the device is reset, the reset cause can be identified by the upper software. . (2) The initialization factor analysis circuit according to claim 1, wherein the holding means is a flip-flop and the converting means is an encoder. (3) The initialization factor analysis circuit according to claim 2, further comprising a register that holds a signal instructing clearing of the reset detection information and resets each flip-flop.