JPH0316321A - Data error correction system - Google Patents

Abstract

PURPOSE:To save the number of components by controlling the serial/parallel conversion timing so that plural decoding means are synchronized with each other based on a ward synchronizing signal obtained from the decoding means. CONSTITUTION:When a conversion timing of a serial parallel conversion circuit 53 is not a correct timing, a synchronizing signal is not outputted from one decoding circuit or over among n-set of decoding circuits 54-1-54-n. The synchronizing state of all the decoding circuits is detected from the n-set of synchronizing signals by an AND gate 60 and an initial value of a counting circuit 56 is loaded at each prescribed interval with a time setting counting circuit 57, a synchronizing state latch F/F 59 and an AND gate 58 to check the synchronizing state at proper time intervals to set the serial/parallel conversion timing to synchronize the n-set of all the decoding circuits. Thus, the quick speed processing is attained with a simple circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data error correction method applied to a digital communication system and used for the purpose of improving communication quality.

[Prior Art] This type of error correction circuit has conventionally been used. It is generally used for digital communications, especially data communication lines, in order to support the high-speed data communications of recent years. It has been conventional practice to achieve the objective by operating multiple low-speed error correction circuits in parallel (see specification of Japanese Patent Application No. 60-282033).
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[Problems to be Solved by the Invention] However, conventional error correction circuits have a large number of parts and a complicated circuit structure. Having a large number of parts poses a problem in terms of reliability, and a simple circuit with a small number of parts is desired.

[Means for Solving the Problems] The data error correction method according to the present invention is such that the error correction code circuit on the transmitting side converts serial input data into parallel data.
a serial-to-parallel conversion means; a plurality of code means for adding error correction codes to each of the plurality of low-speed data obtained from the serial-to-parallel conversion means; and 1. converting the output obtained from each of these coding means into a high-speed serial signal. The error correction decoding circuit on the receiving side includes second serial-to-parallel converting means for converting the received and demodulated high-speed data into a plurality of parallel data. a plurality of decoding means for receiving a plurality of low-speed data obtained from the serial-parallel conversion means, detecting code errors in each data and correcting each; and word synchronization signals obtained from each of these decoding means. , a control means for controlling the serial-to-parallel conversion timing of the second serial-to-parallel conversion means in order to synchronize the plurality of decoding means, and error detection and correction obtained from the decoding means respectively. The present invention is characterized in that it includes a second parallel-to-serial converter that receives low-speed data and converts them into high-speed serial signals.

[Embodiment] Next, an error correction method of the present invention will be explained with reference to the drawings.

FIG. 2 is a block diagram showing an example of the structure of a data communication system to which the error correction circuit of the present invention is applied. In this figure,
On the transmitting side, a group of low-speed data is converted into high-speed data by a multiplex circuit 1. This high-speed data is encoded for error correction in an error correction code circuit 2, modulated in a modulation circuit 3, and then sent to a transmission path. On the receiving side, the input demodulated by the demodulation circuit 4 is given to the error correction decoding circuit 5, which corrects data errors occurring on the transmission path, and then is distributed to low-speed data by the distribution circuit 6. Sent to general data line.

FIG. 3 shows a block diagram of the configuration of a transmission side error correction code circuit as an embodiment of the error correction circuit of the present invention. In this figure, high-speed human input data 201 is converted into n-column low-speed data groups by an n-stage serial-parallel conversion circuit 21.

Each data group that was converted to low speed is. The signals are input to independent code circuits 22-1 to 22-n, respectively. Each of these code circuits outputs a high-speed human clock 202 from the counting circuit 24.
They receive divided low-speed clocks at the same time and operate synchronously.

In each of the encoding circuits 22-1 to 22-n, normal error correction encoding is performed on input data. The encoded output signal of each encoding circuit is converted into high-speed output data 203 in the parallel-to-serial conversion circuit 23 and output. Counting circuit 25, counting circuit 26 and PL
O27 is. By adding error detection/correction codes to the code circuits 22-1 to 22-n, the code circuits operate as 9-phase lock oscillation circuits in order to generate a clock suitable for a changed data rate.

Figure 4 is. As an example of a conventional error correction circuit,
This is a block diagram showing the configuration of the receiving side error correction decoding circuit disclosed in the specification of No.-282033. In this figure, high-speed input data encoded by the encoding circuit 7 on the transmitting side is demodulated by the demodulation circuit 4 (FIG. 2) and then applied to the shift register 510 as an input signal 501. The data sequentially outputted from here is given to the selector 520, and the input timing of each data is selected. Initially, high-speed data with arbitrarily selected human timing was... Next, in the serial/parallel conversion circuit 530, it is converted into a low-speed data group of n columns, which is the same as the code circuit. These n-column low-speed data groups are . Each of the n decoding circuits 540-1 to 540-n is manually operated. Each decoding circuit detects a code error from each human data using a low-speed clock obtained by dividing a high-speed input clock 502 by n in a counting circuit 560, and performs correction power.

The second problem here is the conversion timing when converting into n columns of low-speed data groups. That is. Since the code circuit generates and adds error detection/correction codes to each of the n columns of low-speed data, these code strings need to be handled as one unit. However, these n
If the decoding circuit performs serial-parallel conversion again after parallel-to-serial conversion of several code strings, there is a considerably high probability that the code string that should be treated as one unit will be corrupted.

This problem is solved as follows.

That is, in each decoding circuit 540-1 to 540-n. The error detection/correction code added by the encoder circuit and the error detection/correction code generated by the decoder circuit in the same manner as the encoder circuit are successively compared to the low-speed data string converted into n columns, and a discrepancy is detected. When the number of codes falls below the set number, a synchronization signal for word synchronization is output.

If you do it like this. If the conversion timing of the serial-parallel conversion circuit 530 is not correct, there will be no synchronization signal from at least one of the n decoding circuits 540-1 to 540-n. These n synchronization signals are used to detect the synchronization state of all decoding circuits by an AND gate 600. A time setting counting circuit 570 for checking the synchronization state at appropriate time intervals. The input of the selector 520 is switched at regular intervals by the synchronous state La Nochi F/F 590 and the counting circuit 580, and operates to set the serial-to-parallel conversion timing such that all n decoding circuits are synchronized. do.

As described above, the output signals of the decoding circuits 540-1 to 540-n, which have been error-detected/corrected for each low-speed data string, are again converted to high-speed output data 503 by the parallel-serial conversion circuit 550 and output. be done. The counting circuit 610, the counting circuit 620, and the PLO 630. Like the error correction circuit, it operates as a phase lock oscillation circuit in order to generate a clock corresponding to the change in data speed caused by the removal of the error detection/correction code by the decoding circuit.

FIG. 1 is a block diagram showing the configuration of a receiving side error correction decoding circuit as an embodiment of the error correction circuit of the present invention. In this figure, high-speed input data encoded by the encoding circuit on the transmitting side is demodulated by the demodulation circuit 4 (FIG. 2). It is applied as an input signal 501 to the serial/parallel conversion circuit wI53. The serial-to-parallel conversion circuit 53 converts the data into n-column low-speed data groups, which are the same as the code circuit. These n columns of low-speed data groups are each processed by n decoding circuits 5.
4-1 to 54-n. Each decoding circuit detects and corrects code errors in the respective input data using a low-speed clock obtained by dividing the high-speed input clock 502 by n in the counting circuit 56. even here. There is a problem with the conversion timing when performing serial-parallel conversion from high-speed data to low-speed data as explained in the example of FIG.

The present invention solves this problem as follows. That is, in each of the decoding circuits 54-1 to 54-n, the error detection/correction code added by the encoding circuit is applied to the low-speed data string converted into n columns, and the decoding circuit applies the same method as that performed by the encoding circuit. The error detection/correction codes generated by the above are successively compared, and when the number of mismatching codes is less than or equal to the set number, a synchronization signal for word synchronization is output.

By doing this, if the conversion timing of the serial-to-parallel conversion circuit 53 is not the correct timing. No synchronizing signal is output from at least one of the n decoding circuits 54-1 to 54-n. These n synchronization signals are processed by an AND gate 60 that detects the synchronization state of all decoding circuits, a time setting counting circuit 57 for checking the synchronization state at appropriate time intervals, and a synchronization state latch F/F 5.
9 and an AND gate 58, the initial value of the counting circuit 56 is loaded at regular intervals, and operates to set the serial/parallel conversion timing such that all n decoding circuits are synchronized.

In this way, the output signals of the decoding circuits 54-1 to 54-n, which have undergone error detection/correction for each low-speed data string, are converted into high-speed output data 503 by the parallel-to-serial conversion circuit 55 again.
It is converted into and output.

As in the example shown in FIG. 4, the counting circuit 61, the counting circuit 62, and the PLO 63 perform phase lock oscillation in order to generate a clock that corresponds to the change in data speed caused by the removal of the error detection/correction code by the decoding circuit. Operates as a circuit.

[Effects of the invention] As is clear from the above explanation. According to the present invention, an existing low-speed, low-power consumption error correction circuit implemented as an LSI is used as in the past. Smaller and simpler circuit than conventional models. Moreover, a high-speed error correction circuit can be obtained with reduced power consumption, and the effect obtained is particularly great when applied to a data communication system in satellite communication.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a receiving side error correction code circuit as an embodiment of the present invention, and FIG. Figure 2 is a block diagram showing a configuration example of a data communication system to which the error correction circuit of the present invention is applied. As an embodiment of the present invention, FIG. 4 is a block diagram showing the configuration of a transmitting side error correction decoding circuit. FIG. 4 is a block diagram showing the configuration of a conventional receiving side error correction decoding circuit. Ru. Reference code: 1...Multiple circuit. 2...Error correction code circuit 5 3...Modulation circuit, 4...Demodulation circuit, 5...
Error correction decoding circuit. 6... Distribution circuit, 21... Series-parallel conversion circuit, 22-1 to 22-n... Sign circuit, 2
3...Parallel-serial conversion circuit. 24-26... Counting circuit, 27.63... PLO (phase locked oscillator), 53
...Series-parallel conversion circuit, 54-1 to 54-n...Decoding circuit, 55...Parallel-serial conversion circuit, 56 to 57.6
1■ 62...Counting circuit. 58...AND gate 1
59...F/F60...AND gate, 201.
...Transmission data, 202...Transmission clock. 203・
...Encoded transmission data, 501...Encoded reception data, 502...Reception clock. 503...
- Decoded received data, 510...shift register. 520...Selector 530...Serial parallel conversion circuit, 540-1 to 540-n...Decoding circuit, 550...
...Parallel-serial conversion circuit, 560, 570, 580, 61
0,620... Counting circuit, 590... F/F, 60
0...AND gate, 630...PLO, Figure 3

Claims (1)

[Claims] 1. The error correction code circuit on the transmitting side includes a first serial-to-parallel conversion means for converting serial input data into parallel data, and a plurality of units for adding error correction codes to each of the plurality of low-speed data obtained from the serial-to-parallel conversion means. encoding means, and a first parallel-to-serial conversion means for converting the output obtained from each of these encoding means into a high-speed serial signal. a second serial-to-parallel conversion means for converting data into a plurality of parallel data; and a second serial-to-parallel conversion means for receiving the plurality of low-speed data obtained from the serial-to-parallel conversion means, detecting decoding errors from each data and correcting each one. and a control means for controlling the serial-to-parallel conversion timing of the second serial-to-parallel conversion means so that the plurality of decoding means are synchronized based on word synchronization signals respectively obtained from these decoding means. and second parallel-to-serial converting means for receiving error detected and corrected low-speed data respectively obtained from the decoding means and converting these into high-speed serial signals. error correction method for data.