JP3203289B2 - Time series synchronization circuit of parallel processing decoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a convolutional code which is coded by parallel processing by n convolutional encoders, is multiplexed and transmitted, is separated into n channels, and is parallelized by n Viterbi decoders. The present invention relates to a time series synchronization circuit of a parallel processing decoder for achieving time series synchronization of a code to be decoded in the case of processing and Viterbi decoding.

[0002]

2. Description of the Related Art In this specification, time-series synchronization refers to a convolutional encoder which decodes the contents of a code pair at the same timing of a code to be decoded after separation by a demultiplexer supplied to a Viterbi decoder for parallel processing. Means to match the content of the code pair at the same timing before being coded and multiplexed in parallel. Also,
The time-series synchronization circuit is a circuit for achieving time-series synchronization.

In order to improve communication quality with digitization of communication lines, an error correction device using a combination of a convolutional code and Viterbi decoding for efficiently performing a maximum likelihood decoding method includes:
Known as a powerful tool. Viterbi decoders are already implemented in hardware. The hardware implementation of the Viterbi decoder has made it difficult to increase the coding rate in terms of the scale of the device.However, a high coding rate is achieved by partially thinning out the low coding rate code sequence at regular intervals and transmitting it. Punctured Viterbi decoding for obtaining a code of a conversion rate has been put to practical use.

As a result, an error correction device using a high coding rate code based on convolutional codes, Viterbi decoding, and puncturing can be relatively easily configured with a small number of peripheral circuits. Furthermore, the quality of decoding at the time of Viterbi decoding,
For example, based on a value based on the number of errors in the decoded code (hereinafter, referred to as a state metric value), the state and synchronization timing of a phase ambiguity removal circuit and dummy data (hereinafter, dummy data is also referred to as a null symbol) insertion circuit are synchronized. , The phase ambiguity correction, which is a problem at the time of decoding, and the adjustment of the null symbol insertion timing to data decimated by puncturing are performed inside the Viterbi decoder or using a simple peripheral circuit. You can do it.

FIG. 7 is a block diagram showing a configuration of a Viterbi decoder. In FIG. 7, reference numeral V1 indicates a Viterbi decoder. The Viterbi decoder V1 includes a phase ambiguity removing circuit 21 including an interface to which a convolutional code is input to remove a phase ambiguity, a null symbol inserting circuit 22 composed of, for example, a FIFO memory for inserting a null symbol into the code from which the phase ambiguity is removed, A Viterbi decoding circuit 23 which receives the output of the null symbol insertion circuit 22 and outputs it in a Viterbi combination, outputs a synchronous state monitor circuit 24 for monitoring the quality of decoding, and receives an out-of-sync signal from the synchronous state monitor circuit 24 to change the synchronous state. And a synchronization control circuit 25 for establishing a synchronization state.

The synchronization state monitor circuit 24 measures a state metric value at the time of decoding in the Viterbi decoding circuit 23, and outputs an out-of-synchronization signal when the state metric value exceeds a predetermined threshold value. Here, if the state metric value is a value proportional to the Hamming distance, generally, when the state metric value exceeds a predetermined threshold, it indicates that the phase of the code to be decoded at the input and the synchronization of the null symbol insertion have been lost. ing.

The out-of-synchronization signal is transmitted to the synchronization control circuit
5 is input. Upon receiving the out-of-sync signal, the synchronization control circuit 25 changes the phase state of the phase ambiguity removal circuit 21 and the data read timing from the FIFO memory constituting the null symbol insertion circuit 22. The Viterbi decoder V1 repeats the above control, determines that the synchronization has been recovered from the out-of-synchronization when the decoding quality information based on the state metric value falls within a threshold value regarded as being in synchronization, and stops transmitting the out-of-synchronization signal. In this way, the Viterbi decoder V1 can automatically detect the loss of synchronization on the receiving side and recover the synchronization.

On the other hand, the maximum data rate of the Viterbi decoder is about several tens Mbps. However, several hundred Mbps
In order to realize high speed, a plurality of Viterbi decoders are used in parallel, and multiplexers 26 and 27 and demultiplexers 28 and 29 are used as shown in FIG. It is conceivable to increase the speed by performing parallel processing.

In the example shown in FIG. 8, the encoded code sequence separated into n channels by the demultiplexer 28 is supplied to each of the convolutional encoders C1 to C6, and is processed in parallel by the convolutional encoders C1 to C6. The convolutional code is multiplexed and transmitted by the multiplexer 26. The convolutional code sent from the multiplexer 26 is separated into n channels by a demultiplexer 29, and the separated convolutional codes are supplied to respective Viterbi decoders V1 to V6 for each channel and decoded, and are multiplexed by a multiplexer 27. Taken out. Here, the convolutional encoders C1 to C6 have the same configuration, and the Viterbi decoders V1 to V6 have the same configuration.

However, when the processing circuits are configured in parallel using the Viterbi decoders V1 to V6, the code at the same timing before being encoded by the convolutional encoders C1 to C6 and multiplexed by the multiplexer is used. And the decoder V at the same timing.
The contents of the pairs of the codes to be decoded input to 1 to V6 match,
That is, they must be time-series synchronized.

[0011]

However, conventionally, there has been no means for achieving time series synchronization.
Next, the problem of time-series synchronization will be described with reference to FIGS. 9 to 17 by taking as an example the case where the number of parallel circuits is 2, that is, two channels.

FIG. 9 shows that the data to be encoded is divided into two parts, the convolutional code having a coding rate of 1/2 is punctured and converted into a coding rate of 3/4, and the output is multiplexed and transmitted. Parallel processing, convolutional encoder C1,
FIG. 10 shows a parallel processing convolutional encoder including C2, and FIG. 10 shows parallel processing for receiving Viterbi decoding of an input decoded code divided into two systems upon receiving a convolutional code, and Viterbi decoders V1 and V2.
And a Viterbi decoder including parallel processing.

In the demultiplexer 30, encoded code sequences A and B separated into two channels (FIG. 11)
(See (a)) are separately supplied to the convolutional encoders C1 and C2, respectively, and are encoded by the convolutional encoders C1 and C2 into two systems (I and Q) based on two generator polynomials. The output of each system output from the convolutional encoder C1 is (IA, QA), and the output of the convolutional encoder C2 is similarly (IB, QB) (FIG. 11B)
reference). Furthermore, these are punctured encoders P1, P
In step 2, specific data is erased and output. FIG.
In FIG. 1 (b), crosses indicate data to be deleted, and codes surrounded by ellipses are punctured encoders P1, P
2 indicates that they are output at the same timing.

In FIG. 11B, the data marked with a cross is deleted or punctured by the punctured encoders P1 and P2, and the punctured encoder P1
1 (IA ', QA') and the outputs (IB ', QB') of the punctured encoder P2 are as shown in FIG. 11 (c). The code sequences output from the punctured encoders P1 and P2 are multiplexed into I and Q by the multiplexer 31 and transmitted. The transmitted code sequence is as shown in FIG.

The multiplexed code sequence transmitted after the parallel processing is converted into two code sequences I and Q by code ｛(IC) before being input to the parallel processing and Viterbi decoders V1 and V2. ', QC'), (ID ', QD
′)} And separated by the demultiplexer 32 and input to the Viterbi decoders V1 and V2, respectively.
), (ID ', QD')} are not determined. In this case, there are two types of development because the data is separated into two channels.

This is as follows when the input is, for example, the serial data I shown in FIG. 11D and the demultiplexer comprises D flip-flops 33 to 36 as shown in FIG. FIG. 13A shows FIG.
FIG. 13D shows serial data corresponding to the serial data. The serial data is captured by a data write clock pulse shown in FIG.
The distribution clock pulse shown in FIG.
The pulse is distributed by the distribution clock pulse shown in FIG.

When the distribution is performed by the distribution clock pulse shown in FIG. 13C (referred to as the point of {demulti 1}), the signals are separated as shown in FIG.
When the distribution is made by the distribution clock pulse shown in FIG. 13D (referred to as {Demulti 2} point), FIG.
It is separated as shown in (f), resulting in two types of development.
Therefore, first, the case where the separation is performed at the point of {demulti 1} indicated by the arrow in FIG. 11D and the case where the separation is performed at the point of {demulti 2} are respectively different.

In the former case, the code sequence shown in FIG. 14A is developed, and in this case, the code sequence is developed in the same manner as the code sequence shown in FIG. Synchronized. In the latter case, the code sequence is expanded to the code sequence shown in FIG. 14B, and the code sequence is expanded to a code sequence different from the code sequence shown in FIG.
Time series synchronization is not established, and in this case, a problem arises that the convolutional code is not correctly decoded. In the above, the case where the number of parallel processes is set to 2 channels has been exemplified. However, if the number of parallel processes is n channels, n kinds of expansion will occur.

This will be further described. FIG. 15 is a block diagram of the null symbol insertion circuit 22 in FIG. 7, and FIG. 16 is a timing chart showing the timing at which a null symbol is inserted into the code sequence in the null symbol insertion circuit 22. The null symbol insertion circuit 22 includes a FIFO buffer 37, a clock generation circuit 38, and a null symbol insertion timing circuit 39. FIG. 16 (a) and (f)
Indicates the code sequence of the lower two rows and the upper two rows of the code sequence in FIG. In this case, the time series synchronization is not established as described above.

First, the code sequences (ID'QD ') and (IC'QC') shown in FIGS. 16A and 16F are shown in FIG.
Viterbi decoder V by symbol clock fc shown in FIG.
2. The data is written to the V1 F1F0 buffer 37 in the order of input. The clock generator 38 multiplies the frequency of the symbol clock fc by 3/2 to obtain the frequency fi (f) shown in FIG.
i = 3fc / 2). Where FIF
When the code sequence input to O37 has a coding rate of 3/4,
In each of the I and Q code sequences, one of the three data has been deleted by puncturing. As a result, when a null symbol is inserted, the frequency of the symbol clock fc is multiplied by 3/2 in order to reproduce the original data (3 data) from the two data.

The null symbol insertion timing circuit 39 receives the input from the clock generation circuit 38 and thins out one clock for every three clocks of the output fi of the clock generator 38, as shown in FIG. A clock is generated, and the FIFO is read by the FIFO read clock.
The code sequence is read from the buffer 37. The code sequence read from the FIFO buffer 37 is as shown in FIG. As is clear from FIG.
In the code sequence read by the F0 read clock, a portion erased by puncturing is in a state of being generated in timing. For example, in the case of the code QA2, the deleted code QA3 is generated. The same applies to other erased portions.

The output read from the FIFO buffer 37 can be rewritten as shown in FIG. This corresponds to the state before the erasure by the punctured encoders P1 and P2 and the data before erasure shown in FIG. I understand. In FIG. 17 (a), the crosses indicate data to be erased and existed before erasing, but were erased by puncturing, and in FIG. 16 (e), this part was expanded and recovered in timing. . FIG.
In (b), the portion recovered in timing contains a code enclosed in a preceding or following circle as a null symbol, but it is a simple symbol that converts it to a null symbol (data that is neither 0 or 1). It is possible to recognize as.

The manner in which null symbols are inserted into the code sequence shown in FIG. 16A in the Viterbi decoder V2 in FIG. 10 has been described above. In the Viterbi decoder V1 in FIG. become. That is, as described above, the symbol clock fc shown in FIG.
The code sequence (IC ′, QC ′) of (f) (corresponding to the input code sequence of the Viterbi decoder V1 in FIG. 10 and the code sequence of the upper two columns in FIG. 14B) is written to the F1F0 buffer 37.

The FIFO buffer 37 of the Viterbi decoder V1
The code sequence (IC ′, QC ′) written in FIG.
(D) FIFO read by F0 read clock
Read from 1F0 buffer 8. However, the read data is as shown in FIG. FIG.
In the code sequence shown in (g), a portion that is not erased by puncturing, for example, a code IB1 portion is expanded in timing and is in a generated state. This is shown in FIG.
It can be seen that even if the data is compared with the data before erasure shown in FIG.

In this case, the synchronization state monitor circuit 24 (see FIG. 7) of the Viterbi decoder V1 detects the loss of synchronization, and the synchronization control circuit 25 (see FIG. 7) of the Viterbi decoder V1.
, The null symbol insertion timing circuit 39 (see FIG. 14) of the Viterbi decoder V1 shifts the F1F0 read clock from the state shown in FIG. 16D by two bits as shown in FIG. 16H. The code sequence output by the shifted F1F0 read clock (FIG. 16 (h)) is as shown in FIG. 16 (i), and if written as shown in FIG. Are generated in a timely manner, and FIG.
It turns out that it substantially matches 1 (b).

The code sequence shown in FIG.
The code sequence shown in FIG. 6E is input to the Viterbi decoding circuit, and the code sequence shown in FIG.
As is clear from the figure, the code sequence shown in (e) has a delay of two clocks at this time. That is, output data after Viterbi decoding by the Viterbi decoders V1 and V2 similarly has a delay of two clocks, and it is understood that time series synchronization is not achieved when multiplexing is performed.

As described above, when the parallel processing is performed by the conventional method, since the time-series synchronization based on the multiplex-demultiplex timing is not ensured, there is a problem that the convolutional code is not correctly decoded. There has been no means for achieving such time-series synchronization. Moreover, in each Viterbi decoder, synchronization regarding the phase and puncture of the input code can be taken independently, but this is in each Viterbi decoder, and it is not possible to recognize time-series synchronization loss. Was.

In general, as a method for solving such a problem, a synchronization pattern insertion circuit is added on the transmission side, synchronization data is inserted into a code sequence and transmitted, and a synchronization pattern is searched on the reception side. Time series synchronization is performed. However, the insertion of such synchronization data in the transmission code sequence lowers the information rate, requires a synchronization pattern insertion circuit, a search circuit, and the like, and causes a problem that the apparatus becomes complicated.

An object of the present invention is to provide a time series synchronization circuit of a parallel processing decoder which can lead to a time series synchronization state when time series synchronization is lost.

[0030]

SUMMARY OF THE INVENTION A time series synchronization circuit of a parallel processing decoder according to the present invention comprises a serial multiplexed and multiplexed code by n convolutional encoders (n is a natural number of 2 or more). A convolutional code sequence is input and n
A time-series synchronization circuit of a parallel processing decoder comprising: a demultiplexer for separating into channels; and n Viterbi decoders for receiving and decoding outputs of the respective channels separated by the demultiplexer, respectively. A logical sum operation circuit that performs a logical sum operation on the out-of-sync signal output from the n Viterbi decoders and supplies a logical sum operation output to a synchronization control circuit of the n Viterbi decoders; A time-series out-of-synchronization detection circuit for detecting that an out-of-synchronization signal has been output from all of the decoders within a predetermined period and generating a shift signal for each detection; and the serial convolution which is sent to the demultiplexer for separation. A timing shift circuit for sequentially changing a first code of n consecutive code sequences in the code sequence based on the shift signal. To.

The time-series out-of-synchronization detection circuit in the time-series synchronization circuit of the parallel processing decoder according to the present invention is a full-synchronization detection circuit that detects that an out-of-synchronization signal has been output from all of the n Viterbi decoders within a predetermined period. An out-of-sync signal detection circuit; and a shift signal generating means for generating a shift signal only when a state in which the output of the all-out-of-sync signal detection circuit is output within the predetermined period continues continuously for a predetermined number of times. Features.

The timing shift circuit in the time series synchronization circuit of the parallel processing decoder according to the present invention includes a shift register which receives a serial convolutional code as input and converts it into n parallel convolutional codes; A selector for selecting an input code sequence of an input terminal based on a shift signal from the out-of-synchronization detection circuit and transmitting the input code sequence to a demultiplexer.

The shift signal generating means in the time series synchronizing circuit of the parallel processing decoder according to the present invention is provided when the state in which the output of the all-out-of-synchronization signal detection circuit is output within the predetermined period continues continuously for a predetermined number of times. A frequency dividing means for generating only an output, and an n-ary counter for counting the output of the frequency dividing means and transmitting the count output as a shift signal.

[0034]

The time series synchronization circuit of the parallel processing decoder according to the present invention comprises:
The out-of-synchronization signals output from the n Viterbi decoders are ORed and supplied to the synchronization control circuits of the n Viterbi decoders to be synchronized. On the other hand, n
The output of the out-of-synchronization signal from all of the Viterbi decoders within a predetermined period is detected by a time-series out-of-synchronization detection circuit, and a shift signal is generated for each detection. The shift signal is supplied to a timing shift circuit, and the first code of consecutive n code sequences in the serial convolutional code sequence to be sent out to the demultiplexer for demultiplexing is sequentially changed based on the shift signal. Is done.
As a result, a shift signal is output until the time-series out-of-synchronization detection circuit detects no time-series out-of-sync, and the first codes of the consecutive n code sequences in the serial convolutional code sequence are sequentially changed. During this time, synchronization is achieved only by the synchronization control circuit, and a time-series synchronization state is rapidly established in cooperation with the change.

In the time series out-of-synchronization detecting circuit in the time series synchronizing circuit of the parallel processing decoder of the present invention, all synchronizations for detecting that the out-of-synchronization signals are output from all of the n Viterbi decoders within a predetermined period. An out-of-sync signal detection circuit, and a shift signal generating means for generating a shift signal only when a state in which the output of the all-out-of-sync signal detection circuit is output within the predetermined period continues continuously for a predetermined number of times. Even when the C / N is reduced due to the condition of the transmission path, the state in which the output of the all-out-of-synchronization signal detection circuit is output within the predetermined period is continuously output for a predetermined number of times. The shift signal will not be output, and the action of taking time series synchronization will be started with a delay,
Malfunction due to a temporary decrease in C / N or the like is prevented.

A shift register for inputting a serial convolutional code to a timing shift circuit in the time series synchronization circuit of the parallel processing decoder of the present invention and converting the serial convolutional code into n parallel convolutional codes and receiving the output of the shift register loses time series synchronization. The provision of the selector for selecting the input code sequence of the input terminal based on the shift signal from the detection circuit and sending it to the demultiplexer enables the timing shift circuit to be constituted by standard functional components.

The shift signal generating means in the time series synchronization circuit of the parallel processing decoder generates an output only when the state in which the output of the all-out-of-synchronization signal detection circuit is output within the predetermined period continues continuously for a predetermined number of times. And outputs the count output as a shift signal.
By providing a binary counter, the shift signal generating means can be constituted by standard functional components.

[0038]

The present invention will be described below with reference to examples. FIG.
FIG. 3 is a block diagram showing a configuration of an embodiment of a time series synchronization circuit of a parallel processing decoder according to the present invention, and illustrates a case where parallel processing is performed by six Viterbi decoders.

The time series synchronization circuit 20 of the parallel processing decoder according to the present embodiment shifts the code sequence supplied to the demultiplexer 2 in synchronization with the clock pulse upon receiving the input serial code sequence, and In order to match the contents of the code pair output from 2 with the contents of the code pair at the same timing before being multiplexed by the demultiplexer of the convolutional code on the parallel processing and convolutional encoder side, the demultiplexer 2 A timing shift circuit 1 for shifting the first code of six consecutive code sequences in a serial convolutional code sequence transmitted for separation, a frequency divider 5 for dividing a clock pulse by 6, and a clock pulse as a write clock pulse Writes output from timing shift circuit 1 and outputs from frequency divider 5 The output of the timing shift circuit 1 as a clock pulse distributor is separated into six channels,
A demultiplexer 2 is provided for transmitting the convolutional code sequence of each channel to the Viterbi decoders V1 to V6 respectively. Here, the clock pulse is set to the same frequency as the clock pulse on the convolutional encoding side.

The time series synchronization circuit 20 of the parallel processing decoder
Further, out-of-synchronization signals a to f are supplied from Viterbi decoders V1 to V6, into which the code sequences of the respective channels of the code sequence separated into six channels by the demultiplexer 2 are individually input, and the output is output. Viterbi decoder V
An OR operation circuit 3 for supplying synchronization control circuits (not shown) 1 to V6 and out-of-synchronization signals a to f output from the respective Viterbi decoders V1 to V6 are supplied to detect time-series out-of-synchronization. A time-series out-of-synchronization detecting circuit 4 that outputs a shift signal to the timing shift circuit 1 every time a series out-of-synchronization is detected is provided. The Viterbi decoded output is multiplexed and transmitted by a multiplexer (not shown) as necessary. Also, each Viterbi decoder V
1 to V6 are configured as shown in FIG.

When a loss of synchronization occurs in at least one of the Viterbi decoders V1 to V6, an out-of-synchronization signal is output from the OR circuit 3 to the synchronization control circuit of all the Viterbi decoders V1 to V6, and all the Viterbi decoding is performed. The synchronization recovery operation is performed in the devices V1 to V6. On the other hand, all Viterbi decoders V
The out-of-synchronization signals a to f from 1 to V6 are monitored by a time-series out-of-synchronization detection circuit 4, and all the out-of-synchronization signals a to f
When f is output, it is determined that time-series synchronization has been lost, and in this embodiment, a 3-bit shift signal is sent to the timing shift circuit 1.

Upon receiving the shift signal, the timing shift circuit 1 shifts the first code of six consecutive code sequences in the serial convolutional code sequence to be sent to the demultiplexer 2 for separation. This shift is applied to all Viterbi decoders V
This is continued until 1 to V6 are in a synchronized state, that is, until all of the out-of-sync signals a to f are not output. When all the out-of-synchronization signals a to f are not output, the contents of the code pair at the same timing output from the demultiplexer 2 are processed in parallel, and the code pair at the same timing before multiplexing on the convolutional encoder side. It is the same as the content. That is, the time series synchronization is established.

FIG. 2 is a block diagram showing a specific configuration example of the time-series out-of-synchronization detection circuit 4. The time-series out-of-synchronization detection circuit 4 receives the output from the gate 6 and the gate 6 that outputs the out-of-synchronization signals a to f output from the respective Viterbi decoders V1 to V6 except for the period set by the timer 7. An out-of-synchronization signal detection circuit 8 for detecting that all of the out-of-synchronization signals a to f are output within a period determined by the timer 9, and an output from the all-out-of-synchronization signal detection circuit 8 For example, a frequency divider 10 that detects that the state output within 5 msec has been continuously output for a predetermined number of times, and an output of the frequency divider 10 and a manual signal are selected based on a manual / automatic switching signal. Selector 11, which outputs the output from the selector 11, a shift signal generating circuit 12 which receives the output of the selector 11 and sends out a 3-bit shift signal (F0 to F2), and inverts the output of the out-of-synchronization signal detecting circuit 8. And an inverter 13.

The gate 6 outputs, for example, out-of-synchronization signals a to
and AND gate circuits 61 to 66 for inputting f and inputting the output from the timer 7 inverted by the inverter 7-1 and closing the output period gate from the timer 7. The timer 7 includes, for example, a preset counter, and starts counting clock pulses at the time of reset or when a shift signal is output and the shift amount is changed, for example, when a value corresponding to about 1.3 msec is preset, and starts counting. The output is generated from the time until the count value reaches the preset value. This is because the time required for the internal synchronization of each Viterbi decoder V1 to V6 at reset or when the shift amount is changed is measured about 1.3 msec. This is to prevent the subsequent stage from being affected by the out-of-synchronization signals a to f at the time of resetting or changing the time series.

Therefore, at the time of reset or when the shift amount is changed and the synchronization is lost, the Viterbi decoders V1 to V6 output the out-of-synchronization signals a to f. The time required (1.
3 msec), the gates of the AND gate circuits 61 to 66 are closed, and the time-series out-of-synchronization signal is prevented from being transmitted from the gate 6.

Next, the all-out-of-synchronization signal detecting circuit 8 is provided with latch circuits 81 to 86 for latching out-of-synchronization signals a to f output from the gate 6 and an AND gate 87 for inputting the latch outputs of the latch circuits 81 to 86, The latch circuit 81-86 is cleared when a period set by the timer 9, for example, 5 msec, elapses. Therefore, the all-out-of-synchronization signal detection circuit 8 detects whether all the out-of-synchronization signals have been output within the time set by the timer 9.

When synchronization is not established, the out-of-synchronization signals a to f are output from the Viterbi decoders V1 to V6. When the out-of-sync signals a to f are output from all the Viterbi decoders V1 to V6 within the period set by the timer 9,
The all-out-of-synchronization signal is output from the all-out-of-synchronization signal detection circuit 8 until the time set by the timer 9 elapses from the generation timing of the last out-of-synchronization signal, that is, until the clearing is performed, and the division by the counter Is supplied to the vessel 10. The operation of the out-of-synchronization signal detection circuit 8 is shown in FIG. In FIG. 3, (a) shows a clear signal output from the timer 9, and (b) to (g) show out-of-sync signals a to f.
And (h) shows the all-out-of-synchronization signal output from the signal detection circuit 8.

Upon receiving the all-out-of-synchronization signal output from the all-out-of-synchronization signal detecting circuit 8, the frequency divider 10 performs a frequency dividing operation. In this embodiment, when the output from the all-out-of-synchronization signal detection circuit 8 is transmitted five times, the output from the frequency divider 10 is supplied to the selector 11, and when the selector 11 is set to automatic, An output from the frequency divider 10 is supplied to a shift signal generation circuit 12 through a selector 11.

Here, the frequency divider 10 comprises an inverter 10-1 for inverting the clear signal from the timer 9, and an inverter 1
A latch circuit 10-2 for latching the output from the all-out-of-synchronization signal detection circuit 8 for the output of 0-1 and the Q output of the latch circuit 10-2 as a clear signal, and the output from the all-out-of-synchronization signal detection circuit 8 It comprises a counter 10-3 for frequency division. The divider 10 is a C / N of a temporary communication line.
This is a protection circuit for preventing the shift amount from being immediately changed by an out-of-synchronization signal output due to a drop or the like. This is because when it is determined that the C / N is unstable when the C / N becomes 6 dB or less,
This is because the frequency division corresponds to C / N 6 dB.

The operation of the frequency divider 10 will be described with reference to FIG. When the all-out-of-synchronization signal is continuously output from the all-out-of-synchronization detecting circuit 8 five or more times as in the period α in FIG. 3H, the counter 10-3 is output as shown in FIG. Is not cleared, the frequency divider 10 performs a frequency division operation,
The divided output is sent from the counter 10-3. Such a state is a state in which the out-of-synchronization has occurred, and the all-out-of-synchronization detection circuit 8 continuously outputs an all-out-of-synchronization signal continuously for an extremely large number of times. When the all-out-of-synchronization detection circuit 8 does not continuously output the out-of-synchronization signal five times or more as in the period β in FIG. 3 (h), the number of times of continuous operation is two in the example of FIG. And in this case, Figure 3
As shown in (i), the counter 10-3 is cleared in synchronization with the next generation of the clear signal from the timer 9. Therefore, the frequency divider 10 does not perform the frequency division operation unless it is continued from the out-of-synchronization detection circuit 8 five times or more. As a result,
By providing the frequency divider 10, even if the C / N or the like temporarily decreases, time series synchronization is not immediately performed, and a malfunction is avoided.

In this embodiment, when the automatic / manual switching signal is switched to the manual side so that manual time series synchronization is also possible, a manual signal is transmitted to the selector 11 via the manual switch, and the shift is performed. Signal (F0-F
2) is also generated.

The shift signal generating circuit 12 comprises a hexadecimal counter, and the shift signal generating circuit 12 counts up a 3-bit binary value by a signal from the selector 11. In this embodiment, since the parallel processing of six divisions is performed,
{0} (000) to {5} (101) are output as shift signals. When power is turned on, it is (000), and every time an output from the selector 11 is input, (000) → (0
01) → (010) → (011) → (100) → (10
1) The count is repeated from (000) to (000). The shift signal shifts the first code of the six consecutive code sequences in the serial convolutional code sequence transmitted to the demultiplexer 2 for separation in the timing shift circuit 1.

The output of the all-out-of-synchronization signal detection circuit 8 is directly and through the inverter 13 to the light emitting diode 18 respectively.
And 19, and the out-of-synchronization signal detection circuit 8
The output of the light emitting diode 18 to which the output is supplied is indicated by the light emission of the light emitting diode 18 indicating that the synchronization has been lost.
The time series synchronization is indicated by the light emission of the light emitting diode 19 to which the output 13 of the out-of-synchronization signal detection circuit 8 is supplied via the.

FIG. 4 is a diagram showing a specific configuration example of the timing shift circuit 1 and the demultiplexer 2. The timing shift circuit 1 includes a shift register 14 and a selector 15, and the demultiplexer 2 includes a shift register 1
6 and a hold register 17. First, the serial code sequence input to the timing shift circuit 1 is converted from serial to parallel by the shift register 14, and the parallel output of the shift register 14 is input to the selector 15.

Output terminals QA to QF of shift register 14
Then, different codes in time series are output bit by bit in synchronization with the clock pulse, and input to the selector 15. The selector 15 sends out the code supplied to one input terminal selected based on the shift signal. The code sequence output from the selector 15 is subjected to serial-parallel conversion by the shift register 16, and the shift register 1
The parallel output 6 is input to the hold register 17 and held, and output in synchronization with the output of the frequency divider 5. That is, the signals are divided into six systems by the demultiplexer 2 and input to the respective Viterbi decoders V1 to V6.

That is, in the timing shift circuit 1,
When the selector 15 is in the initial state (the shift signal is (000)), the selector 15 selects and outputs the input of the input terminal DA, and every time the input is supplied to the shift signal generation circuit 12, that is, the value of the shift signal is (+1). As a result, code sequences shifted one bit at a time are sequentially selected and output, and time series synchronization is achieved. This operation is continued until the output from the all-out-of-synchronization signal detection circuit 8 is no longer transmitted, that is, until time-series synchronization is achieved.

On the other hand, when time series synchronization is not established,
An out-of-sync signal is output from at least one Viterbi decoder. Therefore, an out-of-synchronization signal is output from the OR operation circuit 3 and all the Viterbi decoders V1 to V
The synchronization control circuit 6 is controlled until the phase ambiguity removal circuit and the null symbol insertion circuit of each of the Viterbi decoders V1 to V6 are synchronized, that is, until the output from the OR operation circuit 3 disappears. Thus, time-series synchronization is achieved.

Only when the time series synchronization is achieved, the out-of-synchronization signals a to f output from all the Viterbi decoders V1 to V6 disappear, and the output from the OR operation circuit 3 disappears. FIG. 5 is a synchronous state transition diagram showing a process of establishing synchronization in the Viterbi decoders V1 to V6. Here, a coding rate of 3/4 is assumed. If there are two punctured synchronization states and the timing of null symbol insertion is shown in the example of the code sequence A in FIG. 11A, two states S1 and S2 of A2 timing and A3 timing at the time of decoding are considered. Can be The Viterbi decoders V1 to V6 are normally started from the state S1 by turning on the power or resetting.

When the synchronization state monitor circuit in the Viterbi decoders V1 to V6 detects an out-of-synchronization state and outputs an out-of-synchronization signal, the synchronization control circuit in the Viterbi decoders V1 to V6 sets the null symbol insertion circuit to the state 2 Until the out-of-sync condition is no longer detected.
The states S1, S2, S1,... Are repeated.

In FIG. 1, if the time-series synchronization circuit is constituted only by the OR operation circuit 3, all the Viterbi decoders V1 to V6 make the same synchronous state transition at the same timing. If time-series synchronization is achieved, synchronization is achieved with all Viterbi decoders V1 to V6 in the same state. However, when time series synchronization is not established, two states exist. That is, the timing of inserting a null symbol is not equal. In such a case, the state of a Viterbi decoder synchronized in a certain state is changed by an out-of-sync signal from an unsynchronized Viterbi decoder, and the state transition does not stop. Therefore, the out-of-sync signal is continuously output. Conversely, when time-series synchronization is established, the states of all Viterbi decoders V1 to V6 are the same, and the out-of-synchronization signal disappears, but once the out-of-synchronization occurs due to a reset or the like, the state transition does not stop. .

However, in this embodiment, when a time-series out-of-synchronization is detected, an output is sent from the time-series out-of-synchronization detection circuit 4, and the output from the time-series out-of-synchronization detection circuit 4 causes the timing shift circuit 1 to decode the data. Since the shift amount of the code sent to the multiplexer 2 is changed, the state transition does not stop, the time series synchronization is obtained, and the loss of synchronization is eliminated. The elimination of the synchronization loss is rapidly performed in cooperation with the synchronization operation based on the output of the logical sum operation circuit 3.

The output of the out-of-synchronization signal detection circuit 8 drives the light-emitting diode 18 indicating the out-of-synchronization, and the inverted output of the output of the out-of-synchronization signal detection circuit 8 drives the light emitting diode 19 indicating that no out-of-synchronization occurs. As a result, the out-of-sync signal is monitored,
It becomes possible to detect a time-series synchronization state.

Next, the above operation will be described with reference to the flowchart shown in FIG. First, the Viterbi decoders V1 to V1
V6 is reset when the power is turned on, and at the same time, a reset is performed to set the number of inputs F in the frequency divider 10 to 0,
The frequency divider 10, the timers 7, 9 are reset, and both the light emitting diodes 18, 19 are turned off (Step 1). Next, after the set time of the timer 7 elapses, the timer 9
Starts counting (Step 2). When the set time of the timer 7 elapses, the all-out-of-synchronization signal detection circuit 8 operates, and detection within the set time of the timer 9 is started.

It is detected whether or not the out-of-synchronization signals a to f are output from the gate 6 within the set time of the timer 9. When the set time of the timer 9 elapses, the output is sent out by the all-out-of-sync signal detection circuit 8. If so, the light emitting diode 18 indicating the time-series out of synchronization is driven. The above operation is repeated until the output from the frequency divider 10 receives the output from the all-out-of-sync signal detection circuit 8, that is, until the output is output five times from the all-out-of-sync signal detection circuit 8. When the output is transmitted five times from the all-out-of-synchronization signal detection circuit 8, the output is transmitted from the frequency divider 10, the shift signal is output with a changed value, and then reset to the initial state. This operation is repeated until the all-out-of-sync signal is no longer detected five consecutive times (S
step3, Step4).

When the out-of-synchronization detection signal is not output from the all-out-of-synchronization signal detection circuit 8 after the elapse of the set period of the timer 9, the light-emitting diode 18 indicating the out-of-time synchronization is turned off, and the light emitting diode 19 indicating the time-series synchronization is turned off. It is turned on, and is repeated from Step 2 (Step 5). The time-series synchronization operation is completed as described above, but the all-out-of-synchronization signal detection circuit 8 always monitors the out-of-synchronization signal. Even in the case where it cannot be taken, for example, the action for instantaneously synchronizing the time series is executed, and the time series synchronous state is quickly established.

[0066]

As described above, according to the time series synchronization circuit of the parallel processing decoder of the present invention, the OR operation is performed on the out-of-synchronization signals output from the n Viterbi decoders, and the n Viterbi decoders are operated. , And synchronizes by detecting the output of an out-of-synchronization signal within a predetermined period from all of the n Viterbi decoders, generating a shift signal for each detection, and based on the shift signal. Since the first code of the consecutive n code sequences in the serial convolutional code sequence to be transmitted to the demultiplexer for demultiplexing is sequentially changed, the time-series synchronization detection circuit detects the time-series synchronization. Until no loss is detected, a shift signal is output, and the first code of the consecutive n code sequences in the serial convolutional code sequence is sequentially changed. And only synchronization is taken by the synchronization control circuit, rapid the effect of the time-series synchronized state in cooperation with the change.

The all-synchronization for detecting the output of the out-of-synchronization signal from all of the n Viterbi decoders within a predetermined period to the time-series out-of-synchronization detection circuit in the time series synchronization circuit of the parallel processing decoder of the present invention. A shift signal generating means for generating a shift signal only when the state in which the output of the out-of-sync signal detection circuit and the output of the all-out-of-sync signal detection circuit are output within the predetermined period continues continuously for a predetermined number of times; In the case where the C / N is reduced due to the situation described above,
The shift signal is not output until the output of the all-out-of-synchronization signal detection circuit is output a predetermined number of times. This has the effect of preventing malfunction due to a drop or the like.

A shift register which receives a serial convolutional code as an input to a timing shift circuit in a time series synchronization circuit of a parallel processing decoder of the present invention and converts the serial convolutional code into n parallel convolutional codes, and receives an output of the shift register, loses time series synchronization. A selector for selecting the input code sequence of the input terminal based on the shift signal from the detection circuit and sending the input code sequence to the demultiplexer; And a n-ary counter which counts the output of the frequency dividing means and sends it out as a shift signal, thereby providing a timing shift circuit and a shift signal. Since the generating means can be configured by standard functional components, there is an effect that the configuration is simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a time-series synchronization circuit of a parallel processing decoder according to the present invention.

FIG. 2 is a block diagram showing a specific configuration example of a time-series out-of-synchronization detection circuit in one embodiment of the time-series synchronization circuit of the parallel processing decoder according to the present invention.

FIG. 3 is a timing chart for explaining the operation of one embodiment of the time-series synchronization circuit of the parallel processing decoder according to the present invention.

FIG. 4 is a block diagram showing a specific configuration example of a timing shift circuit and a demultiplexer in an embodiment of the time series synchronization circuit of the parallel processing decoder according to the present invention.

FIG. 5 is a state transition diagram of the Viterbi decoder in one embodiment of the present invention.

FIG. 6 is a flowchart for explaining the operation of one embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a Viterbi decoder.

FIG. 8 is a block diagram showing a configuration when performing parallel processing by a plurality of convolutional encoders and a plurality of Viterbi decoders.

FIG. 9 is a block diagram illustrating a configuration of a convolutional encoder when performing parallel processing.

FIG. 10 is a block diagram illustrating a configuration of a Viterbi decoder when performing parallel processing.

FIG. 11 is a timing chart at which a null symbol is inserted into a code sequence.

FIG. 12 is a block diagram for explaining the development of a code sequence during conventional parallel processing.

FIG. 13 is a timing chart for explaining expansion of a code sequence during conventional parallel processing.

FIG. 14 is a timing chart for explaining a conventional output of a demultiplexer that supplies a code sequence to a parallel processing Viterbi decoder.

FIG. 15 is a block diagram illustrating a configuration of a null symbol insertion circuit of the Viterbi decoder.

FIG. 16 is a timing chart for explaining a conventional timing at which a null symbol is inserted by a null symbol insertion circuit of the parallel processing Viterbi decoder.

FIG. 17 is a timing chart for explaining a conventional timing at which a null symbol is inserted by a null symbol insertion circuit of a Viterbi decoder.

[Explanation of symbols]

 V1 to V6 Viterbi decoders C1 to C6 Convolutional encoder 1 Timing shift circuit 2 Demultiplexer 3 OR operation circuit 4 Time-series out-of-synchronization detection circuit 5 and 10 divider 6 Gate 7 and 9 Timer 8 Total out-of-synchronization signal detection circuit Reference Signs List 11 selector 12 shift signal generating circuit 13 inverter 14 and 16 shift register 15 selector 17 hold register

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Akihiro Horii 1-2-5 Shibuya, Shibuya-ku, Tokyo Inside Kenwood Co., Ltd. (72) Inventor Hide Takechi 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation JP-A-3-173224 (JP, A) JP-A-2-86232 (JP, A) JP-A-2-294121 (JP, A) JP-A-4-373337 (JP) , A) JP-A-60-177746 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 9/00 H03M 13/23 H04L 7/00

Claims (4)

(57) [Claims] 1. A demultiplexer which receives a multiplexed serial convolutional code sequence coded in parallel by n convolutional encoders (n is a natural number of 2 or more) and multiplexes the demultiplexed signal into n channels. A time-series synchronization circuit of a parallel processing decoder including n Viterbi decoders each receiving and decoding the output of each channel separated by the multiplexer, and outputting from the n Viterbi decoders. And a logical sum operation circuit for performing a logical sum operation on the out-of-synchronization signal and supplying a logical sum operation output to a synchronization control circuit of the n Viterbi decoders, and synchronizing within a predetermined period from all of the n Viterbi decoders A time-series out-of-synchronization detection circuit for detecting the output of the out-of-position signal and generating a shift signal for each detection is sent to the demultiplexer for separation. A timing shift circuit for sequentially changing the first code of n consecutive code sequences in the serial convolutional code sequence based on the shift signal. 2. The time-series synchronization circuit of a parallel processing decoder according to claim 1, wherein the time-series out-of-synchronization detection circuit outputs an out-of-synchronization signal within a predetermined period from all of the n Viterbi decoders. And a shift signal generating means for generating a shift signal only when the state in which the output of the all-out-of-sync signal detection circuit is output within the predetermined period continues continuously for a predetermined number of times. A time series synchronization circuit for a parallel processing decoder, comprising: 3. A time series synchronizing circuit for a parallel processing decoder according to claim 1, wherein the timing shift circuit receives a serial convolutional code as input and converts the serial convolutional code into n parallel convolutional codes, and an output of the shift register. And a selector for selecting an input code sequence at an input terminal based on a shift signal from the time-series out-of-synchronization detection circuit and transmitting the input code sequence to a demultiplexer. 4. The time series synchronization circuit of a parallel processing decoder according to claim 2, wherein the shift signal generation means continuously outputs the output of the out-of-synchronization signal detection circuit within said predetermined period for a predetermined number of times. A parallel processing decoder comprising: a frequency dividing means for generating an output only when continued; and an n-ary counter for counting the output of the frequency dividing means and transmitting the counted output as a shift signal. Series synchronization circuit.