JPH0697818A - Synchronous frequency dividing circuit - Google Patents

Abstract

PURPOSE:To improve the reliability of a multiplexer including a synchronous frequency dividing circuit or an optical transmission system, etc., and to speed up the transmission rate by constructing the synchronous frequency dividing circuit which can surely and synchronously reset the communication data with no omission. CONSTITUTION:In a synchronous frequency dividing circuit FDC including the master-slave type flip-flop FF1-FF3 which are substantially set in a series form and also receive the common synchronous reset signals FPI through the master latch reset input terminals Rm of each bit, the signal FPI is inputted to the slave latch reset terminal Rs of the FF3 of the final bit, for example, at the same time, the latch PLT holding the logical level right before the output signal QP of the FF3 while the signal FPI is kept at a high level is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous frequency dividing circuit, and particularly to a technique which is particularly effective when used in a synchronous frequency dividing circuit which constitutes a multiplexer of an optical transmission system.

[0002]

2. Description of the Related Art There is a frequency dividing circuit (frequency dividing counter) consisting of a flip-flop of a predetermined bit in serial form. In addition, there is a so-called synchronous frequency dividing circuit that synchronously resets a flip-flop that constitutes the frequency dividing circuit according to a predetermined synchronous reset signal. Further, there are multiplexers controlled by the synchronous frequency dividing circuit, and there are optical transmission systems equipped with such multiplexers.

The frequency dividing circuit (frequency dividing counter) is described, for example, in "Digital IC Practical Circuit Manual", page 169 by Yojiro Yokoi, published by Radio Technology Co., Ltd. on July 25, 1979.

[0004]

Prior to the present invention, the inventors of the present application have developed a synchronous frequency divider circuit FDC as shown in FIG. 5, and an optical transmission system including the synchronous frequency divider circuit FDC. Developed a multiplexer for the. The synchronous frequency divider circuit FDC includes three master-slave flip-flops FF1 to FF3 that are substantially in serial form,
The non-inverted output signals Q of these flip-flops are the output signals Q of the first to third bits of the synchronous frequency divider FDC.
1 to Q3 are supplied to the multiplexer. Flip-flops FF1 to FF forming the synchronous frequency dividing circuit FDC
3 has a data input terminal D and a corresponding inverting output terminal QB.
(Here, so-called inverted signals and inverted output terminals, etc., which are selectively brought to a low level when they are enabled, are indicated by adding B to the end of their names. The same applies hereinafter), respectively. A predetermined synchronous reset signal FPI is commonly supplied to the master latch reset input terminal Rm. Further, the clock signal CLK corresponding to the data rate of the transmission line after multiplexing is supplied to the clock input terminal C of the flip-flop FF1, and the substantial clock signal CLK is supplied to the clock input terminal C of the flip-flops FF2 and FF3. As, the non-inverted output signals Q of the flip-flops FF1 and FF2 in the preceding stage are respectively supplied.

From these points, the flip-flop FF
The non-inverted output signal Q of 1, that is, the output signal Q1 of the first bit of the synchronous frequency dividing circuit FDC is, as shown in FIG.
In response to the falling edge of the clock signal CLK, the high level is alternately changed to the low level, and the non-inverted output signal Q of the flip-flops FF2 and FF3, that is, the second and third bit output signals Q2 of the synchronous frequency divider FDC and Q3 is the flip-flops FF1 and F of the preceding stage, respectively.
Non-inverted output signal Q of F2, that is, output signals Q1 and Q2
In response to the falling edge of, the high level is alternately changed to the low level. Output signals Q1 to Q3 of the synchronous frequency dividing circuit FDC are supplied to a multiplexer as shown in FIG. 1, and communication data for eight channels is multiplexed according to these output signals Q1 to Q3.

By the way, the synchronous frequency divider circuit FDC of FIG.
Adopts a so-called synchronous reset method using a synchronous reset signal FPI. As shown in FIG. 6, the synchronous reset signal FPI is set to a high level periodically for eight cycles of the clock signal CLK and for a period of one cycle of the clock signal CLK. The non-inverted output signal Q of the flip-flops FF1 to FF3, that is, the output signals Q1 to Q3 of the first to third bits of the synchronous frequency divider FDC are the synchronous reset signals supplied to the master latch reset input terminal Rm. It is selectively reset when the FPI goes high at the falling edge of the corresponding clock signal. Therefore, the non-inverted output signal Q of the flip-flop FF1, that is, the output signal Q1 is the synchronous reset signal FPI.
Is reset in synchronization with the falling edge of the clock signal CLK every time the signal is set to a high level, the non-inverted output signals Q of the flip-flops FF2 and FF3, that is, the output signals Q2 and Q3 are at least the synchronous reset signal FPI.
Within 3 cycles of, the non-inverted output signal Q of the previous flip-flop FF1 or FF2, that is, the output signal Q1 or Q2, that is, the reset signal is reset in synchronization with the falling edge of the clock signal CLK.

However, as the transmission rate of the optical transmission system increases and the frequency of the clock signal CLK increases, the conventional synchronous frequency dividing circuit FDC as described above is used.
It has become clear by the inventors of the present application that the following problems will occur. That is, the synchronous frequency divider F
In DC, the non-inverted output signal Q of the flip-flop FF1 is first supplied while the synchronous reset signal FPI is set to the high level.
That is, the output signal Q1 is reset by receiving the falling edge of the clock signal CLK, and the non-inverted output signal Q of the flip-flop FF2, that is, the output signal Q2 is further received by the falling edge of the output signal Q1. Receiving the falling edge, the non-inverted output signal Q of the flip-flop FF3, that is, the output signal Q3 is sequentially reset. Therefore, for example, as shown in FIG. 7, when the relative time relationship of the synchronous reset signal FPI with respect to the clock signal CLK is slightly advanced, the non-inverted output signal of the flip-flop FF2 depends on the signal transmission delay time of the preceding flip-flop FF1. Q, that is, the falling edge of the output signal Q2 is out of the high level period of the synchronous reset signal FPI, and the reset of the flip-flop FF3 is not normally performed. As a result, the reliability of the optical transmission system is lowered, and if the reliability is to be maintained, the speedup is restricted.

In order to deal with this, the inventors of the present application apply the synchronous reset signal FPI to the slave latch reset input terminal R of the flip-flop FF3 as shown in FIG.
s is also input to improve the reset operation of the flip-flop FF3. However, when this method is adopted, as shown in FIG. 9, since the non-inverted output signal Q of the flip-flop FF3, that is, the output signal Q3 is reset at the rising edge of the synchronous reset signal FPI, a normal multiplexing operation is performed. In the existing multiplexer, the communication data in the shaded area is lost.

An object of the present invention is to provide a synchronous frequency dividing circuit which can surely reset synchronously without losing communication data. Another object of the present invention is to improve the reliability of a multiplexer including a synchronous frequency dividing circuit and thus an optical transmission system and the like, and to accelerate the transmission rate thereof.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a synchronous frequency divider circuit that includes a plurality of master-slave flip-flops that are substantially in serial form and that receive a common synchronous reset signal at the master latch reset input terminal of each bit, for example, the slave of the flip-flop of the last bit An output latch for inputting the synchronous reset signal to the latch reset input terminal and for holding the logic level immediately before the output signal of the last bit flip-flop while the synchronous reset signal is at the high level is provided.

[0012]

According to the above means, the flip-flop of the final bit can be reliably reset by the synchronous reset signal, the synchronous reset operation of the synchronous frequency divider circuit can be stabilized, and while the synchronous reset signal is at the high level, The output signal of the flip-flop of the final bit can be held by the output latch to prevent the loss of communication data.
As a result, it is possible to improve the reliability of the multiplexer including the synchronous frequency dividing circuit, and thus the optical transmission system, and to accelerate the transmission rate.

[0013]

1 is a block diagram of an embodiment of a multiplexer including a synchronous frequency dividing circuit FDC to which the present invention is applied, and FIG. 2 is a signal waveform diagram of the embodiment. Has been done. Based on these figures, the outline of the configuration and operation of the multiplexer of this embodiment will be described first.
The multiplexer of this embodiment is included in the optical transmission system, although not particularly limited. The circuit elements forming each block in FIG. 1 are not particularly limited, but are formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

In FIG. 1, the multiplexer is a so-called 8-bit (N-bit) multiplexer, which multiplexes 8-bit communication data D0 to D7 supplied in parallel from a pre-stage circuit (not shown) as one communication data MD. The multiplexer takes in the communication data D0 to D7 in synchronization with the falling edge of the output signal Q3 of the third bit of the synchronous frequency divider FDC, and outputs the clock signal CLK.
The data input buffer BFI is provided for holding only for a period corresponding to 8 cycles. This data input buffer BFI
The 4-bit output signals corresponding to the communication data D0 to D3 are directly transmitted to the first to fourth input terminals of the data selector SL1, and the remaining 4-bit output signals corresponding to the communication data D4 to D7 are data The data is transmitted to the fifth to eighth input terminals of the data selector SL1 via the latch DL1.

The data latch DL1 is a 4-bit communication data D4 held by the data input buffer BFI.
.About.D7 are fetched in synchronization with the falling edge of the output signal Q3 of the third bit of the synchronous frequency divider FDC, and held for a period corresponding to eight cycles of the clock signal CLK.
The data selector SL1 is a synchronous frequency divider circuit FDC.
When the output signal Q3 of the third bit is set to the low level, the 4-bit communication data D0 to D3 directly transmitted from the data input buffer BFI is selected, and the output signal Q3 of the synchronous frequency dividing circuit FDC is set to the high level. At this time, the remaining 4-bit communication data D4 to D7 transmitted via the data latch DL1 are selected. The 2 bits of the output signal of the data selector SL1 are the same as those of the data selector SL2.
And the remaining 2 bits are transmitted to the first and second input terminals of the data selector SL2 via the data latch DL2.
Is transmitted to the third and fourth input terminals of.

The data latch DL2 is a data selector S.
The 2-bit communication data D2 and D3 or D6 and D7 transmitted via L1 are fetched in synchronization with the falling edge of the output signal Q2 of the second bit of the synchronous frequency divider FDC, and four cycles of the clock signal CLK are taken. Hold only for a period corresponding to. Further, the data selector SL2 receives the 2-bit communication data D0 and D1 or D directly transmitted from the data selector SL1 when the output signal Q2 of the second bit of the synchronous frequency dividing circuit FDC is set to the low level.
4 and D5 are selected, and when the output signal Q2 of the synchronous frequency divider FDC is set to the high level, the data selector SL1
From the remaining 2-bit communication data D2 and D3 or D6 and D7 transmitted via the data latch DL2. One bit of the output signal of the data selector SL2 is directly transmitted to the first input terminal of the data selector SL3, and the remaining one bit is transmitted to the second input terminal of the data selector SL3 via the data latch DL3.

The data latch DL3 is a data selector S.
1-bit communication data D1, D transmitted via L2
3, D5 or D7 is fetched in synchronization with the falling edge of the output signal Q1 of the first bit of the synchronous frequency divider FDC, and held for a period corresponding to two cycles of the clock signal CLK. Further, the data selector SL3 selects the 1-bit communication data D0, D2, D4 or D6 directly transmitted from the data selector SL2 when the output signal Q1 of the first bit of the synchronous frequency divider FDC is set to the low level. When the output signal Q1 of the synchronous frequency divider FDC is set to the high level, the remaining 1-bit communication data D1, D3, D5 or D7 transmitted from the data selector SL2 via the data latch DL3 is selected. The output signal of the data selector SL3 is taken into the data output buffer BFO in synchronization with the rising edge of the clock signal CLK and then transmitted as communication data MD to a subsequent circuit (not shown). As a result, the communication data D0 to D7 are
As shown in FIG. 2, one bit is sequentially selected in accordance with the clock signal CLK and multiplexed as communication data MD having 8 frames of the clock signal CLK as one frame.

In this embodiment, the synchronous frequency divider FD
Although not particularly limited to C, 8 of the clock signal CLK
A synchronous reset signal FPI is supplied, which has a cycle, that is, one frame of the communication data MD as a cycle, and is at a high level only during a period corresponding to one cycle of the clock signal CLK. As will be described later, this synchronous reset signal FPI is used for synchronous reset of the synchronous frequency dividing circuit FDC, whereby frame synchronization between the multiplexed communication data MD and the transmission line is established.

FIG. 3 is a circuit diagram of an embodiment of the synchronous frequency divider circuit FDC included in the multiplexer of FIG.
FIG. 4 shows a signal waveform diagram of the embodiment.
Based on these figures, the synchronous frequency divider FD of this embodiment
The specific configuration and operation of C and its features will be described.

In FIG. 3, the synchronous frequency divider FDC of this embodiment includes 3-bit master-slave flip-flops FF1 to FF3. The clock signal CLK is supplied to the clock input terminal C of the first-bit flip-flop FF1, and the first and second bits of the clock input terminal C of the second- and third-bit flip-flops FF2 and FF3. The non-inverted output signals Q of the flip-flops FF1 and FF2 are respectively supplied. Further, the corresponding inverted output signals QB are respectively supplied to the data input terminals D of the flip-flops FF1 to FF3, and the master latch reset input terminal Rm thereof is commonly supplied with the synchronous reset signal FPI. As described above, the non-inverted output signal Q of the flip-flop FF1 is supplied to the data latch DL3 and the data selector SL3 as the output signal Q1 of the first bit of the synchronous frequency divider FDC, and the non-inverted output signal of the flip-flop FF2. Q is supplied to the data latch DL2 and the data selector SL2 as the output signal Q2 of the second bit of the synchronous frequency divider FDC.

In this embodiment, the synchronous reset signal F
PI is also input to the slave latch reset input terminal Rs of the flip-flop FF3 of the third bit of the synchronous frequency divider FDC, that is, the last bit. Further, the synchronous frequency dividing circuit FDC further has a non-inverted output signal Q of the flip-flop FF3, that is, an internal signal Q at its data input terminal D.
It includes an output latch OLT receiving P and receiving a synchronous reset signal FPI at its inverted clock input terminal CB. The non-inverted output signal Q of this output latch OLT is a synchronous frequency divider circuit F.
The output signal Q3 of the third bit of DC is supplied to the data input buffer BFI, the data latch DL1, and the data selector SL1. Here, the output latch OLT, when the synchronous reset signal FPI input to its inverted clock input terminal CB is at a low level (invalid level),
Flip-flop F supplied to the data input terminal D
The non-inverted output signal Q of F3, that is, the internal signal QP is transmitted as it is, and its non-inverted output signal Q, that is, the output signal Q3.
And Further, when the synchronous reset signal FPI is set to a high level (effective level), a so-called latch state is set, and the logic level immediately before the internal signal QP is maintained until the synchronous reset signal FPI is returned to the low level.

From these points, the flip-flop FF
1 acts as a 1-bit binary counter which is stepped up in accordance with the clock signal CLK, and its non-inverted output signal Q, that is, the output signal Q1 of the first bit of the synchronous frequency divider FDC is as shown in FIG. , Clock signal CLK
Are alternately set to the high level or the low level in synchronization with the falling edge. Similarly, the flip-flop FF2
Acts as a non-inverted output signal Q of the flip-flop FF1, that is, as a 1-bit binary counter stepped according to the output signal Q1, and its non-inverted output signal Q, that is, the output signal Q2 of the second bit of the synchronous frequency divider FDC. Is
It is alternately set to the high level or the low level in synchronization with the falling edge of the output signal Q1.

Further, the flip-flop FF3 acts as a 1-bit binary counter which is stepped up in accordance with the non-inverted output signal Q of the flip-flop FF2, that is, the output signal Q2, and the non-inverted output signal Q of the internal signal QP is output. The signal is alternately set to the high level or the low level in synchronization with the falling edge of the signal Q2. Non-inverted output signal Q of flip-flop FF3, that is, internal signal QP
When the synchronous reset signal FPI is set to the low level, the signal is directly transmitted to the non-inverting output terminal Q by the output latch OLT and becomes the output signal Q3 of the third bit of the synchronous frequency divider FDC. In addition, the synchronous reset signal FPI
Is set to a high level, the logic level immediately before that is held by the output latch OLT, and the synchronous reset signal F
Until the PI is returned to the low level again, the output signal Q
It is output as 3.

On the other hand, the flip-flop FF1 outputs the synchronous reset signal FP to the master latch reset input terminal Rm.
Since I is input, the non-inverted output signal Q, that is, the output signal Q1 of the first bit of the synchronous frequency divider FDC is synchronized with the falling edge of the clock signal CLK when the synchronous reset signal FPI is set to the high level. Then, it is selectively reset to low level. Similarly, the flip-flop FF2 has a master latch reset input terminal Rm.
Since the synchronous reset signal FPI is input to, the non-inverted output signal Q, that is, the output signal Q2 of the second bit of the synchronous frequency dividing circuit FDC, is not applied to the flip-flop FF1 when the synchronous reset signal FPI is at a high level. The inverted output signal Q, that is, the output signal Q1 is selectively reset in synchronization with the falling edge of the output signal Q1, and is set to a low level.

Further, in the flip-flop FF3, since the synchronous reset signal FPI is input to the master latch reset input terminal Rm and the slave latch reset input terminal Rs, its non-inverted output signal Q, that is, the internal signal QP.
Is unconditionally reset to a low level by receiving the high level of the synchronous reset signal FPI regardless of the non-inverted output signal Q of the flip-flop FF2, that is, the output signal Q2. At this time, the logic level immediately before the internal signal QP is held by the output latch OLT when the synchronous reset signal FPI is set to the high level as described above.
Until the synchronous reset signal FPI is returned to the low level again, it is output as the output signal Q3 of the third bit of the synchronous frequency dividing circuit FDC.

Therefore, in the synchronous frequency divider FDC of this embodiment, the flip-flop FF3 can be reliably reset even when the relative time relationship of the synchronous reset signal FPI with respect to the clock signal CLK is slightly advanced. This stabilizes the synchronous reset operation of the synchronous frequency dividing circuit FDC. Also, the flip-flop FF
After resetting 3, the non-inverted output signal Q, that is, the logic level immediately before the internal signal QP is held by the output latch OLT. Therefore, the timing margin of the output signal Q3 of the third bit of the synchronous frequency divider FDC is set. This can be ensured and the loss of communication data in the multiplexer can be prevented. As a result, the synchronous frequency divider F
The reliability of the multiplexer including the DC and further the optical transmission system can be improved and the transmission rate can be increased.

As shown in the above-mentioned embodiment, by applying the present invention to the synchronous frequency dividing circuit which constitutes the multiplexer of the optical transmission system, the following operational effects can be obtained. That is, (1) In a synchronous frequency divider circuit, which is substantially in serial form and comprises a plurality of bits of master-slave flip-flops that receive a common synchronous reset signal to the master latch reset input terminal of each bit, By providing a synchronous reset signal to the slave latch reset input terminal of the flip-flop, and by providing an output latch that holds the logic level immediately before the output signal of the flip-flop of the final bit while the synchronous reset signal is high level, The effect that the flip-flop of the last bit is surely reset by the synchronous reset signal and the synchronous reset operation of the synchronous frequency divider circuit can be stabilized is obtained.

(2) According to the above item (1), while the synchronous reset signal is at the high level, the output signal of the flip-flop of the final bit can be held by the output latch to prevent the loss of communication data. The effect is obtained. (3) According to the above items (1) and (2), it is possible to improve the reliability of the multiplexer including the synchronous frequency dividing circuit and thus the optical transmission system, and to accelerate the transmission rate. To be

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, if the timing margin of the multiplexer is sufficient, the data input buffer BFI can be used as the data latch DL1. The multiplexer can multiplex communication data of an arbitrary number of bits, and its block configuration can take various embodiments.
In FIG. 2, the synchronous reset signal FPI can take an arbitrary cycle on condition that it is an integer n times one frame of the clock signal CLK, that is, N cycles. Further, the combination of the communication data D0 to D7 by the multiplexer and the multiplexing order are not restricted by this embodiment.

In FIG. 3, the synchronous frequency dividing circuit FDC is
Depending on the number of bits of communication data multiplexed by the multiplexer, any number of master-slave flip-flops can be included. Further, the flip-flop in which the synchronous reset signal FPI is input to the slave latch reset input terminal Rs and the output latch OLT is provided in the subsequent stage is a flip-flop according to the signal transmission delay time of the flip-flop which constitutes the synchronous frequency dividing circuit FDC. The bit position and the number can be set arbitrarily. That is, when the signal transmission delay time of the flip-flop of each stage is long, the same treatment is required for the flip-flop FF2 of the second bit, and the synchronous frequency dividing circuit FDC has four steps.
If the flip-flops consist of more than one bit, the same treatment is required for a plurality of flip-flops.
Further, various embodiments can be adopted for the specific configuration of the synchronous frequency dividing circuit FDC, the combination of the clock signal CLK and the synchronous reset signal FPI, the combination of each internal signal, the logical level, and the like.

In the above description, the case where the invention made by the present inventor is mainly applied to the synchronous frequency dividing circuit included in the multiplexer of the optical transmission system which is the background field of application has been described, but the invention is not limited thereto. However, the present invention can also be applied to, for example, a synchronous frequency divider formed as a single unit as a synchronous frequency divider or a similar synchronous frequency divider included in other various transmission systems. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a synchronous frequency divider circuit including at least a plurality of master-slave flip-flops in serial form and a system including such a synchronous frequency divider circuit.

[0032]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a synchronous frequency divider circuit which is substantially in serial form and comprises a plurality of master-slave flip-flops that receive a common synchronous reset signal to the master latch reset input terminals of each bit, for example, the slave of the flip-flop of the last bit While inputting a synchronous reset signal to the latch reset input terminal,
By providing an output latch that holds the logic level immediately before the output signal of the final bit flip-flop while the synchronous reset signal is high level, the final bit flip-flop is reliably reset by the synchronous reset signal While stabilizing the synchronous reset operation of the frequency divider circuit, while the synchronous reset signal is high level,
The output signal of the flip-flop of the final bit can be held by the output latch to prevent the loss of communication data. As a result, it is possible to improve the reliability of the multiplexer including the synchronous frequency dividing circuit, and thus the optical transmission system, and to accelerate the transmission rate.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a multiplexer including a synchronous frequency dividing circuit to which the present invention is applied.

FIG. 2 is a signal waveform diagram showing an embodiment of the multiplexer shown in FIG.

FIG. 3 is a circuit diagram showing an embodiment of a synchronous frequency divider circuit to which the invention is applied.

FIG. 4 is a signal waveform diagram showing an embodiment of the synchronous frequency divider circuit of FIG.

FIG. 5 is a circuit diagram showing an example of a synchronous frequency divider circuit developed by the inventors of the present application prior to the present invention.

6 is a signal waveform diagram during normal operation of the synchronous frequency divider circuit of FIG.

7 is a signal waveform diagram during abnormal operation of the synchronous frequency divider circuit of FIG.

8 is a circuit diagram showing an example of a synchronous frequency divider circuit obtained by improving the synchronous frequency divider circuit of FIG. 5 by the present inventors.

9 is a signal waveform diagram showing an example of the synchronous frequency divider circuit of FIG.

[Explanation of symbols]

FDC ... Synchronous frequency divider circuit, BFI ... Data input buffer, DL1 to DL3 ... Data latch, SL1
-SL3 ... Data selector, BFO ... Data output buffer. FF1 to FF3 ... Master-slave flip-flop, OLT ... Output latch.

Claims (4)

[Claims] 1. A master-slave flip-flop of a plurality of bits, which is in serial form and receives a common synchronous reset signal to the master latch reset input terminal of all bits and a slave latch reset input terminal of a predetermined bit, A synchronous frequency divider circuit, comprising: an output latch that holds an output signal of a master-slave flip-flop for a predetermined period. 2. The output latch transmits the output signal of the master-slave flip-flop of the predetermined bit as it is when the synchronous reset signal is at an invalid level, and when the synchronous reset signal is at an effective level. 2. The synchronous frequency divider circuit according to claim 1, which holds a logic level immediately before an output signal of a master-slave flip-flop of a predetermined bit. 3. The synchronous frequency divider circuit according to claim 1, wherein the master-slave flip-flop of the predetermined bit is a master-slave flip-flop of the final bit. 4. The synchronous frequency divider circuit is included in an N-bit multiplexer of an optical transmission system, and the synchronous reset signal is periodically set to an effective level every N or n × N cycles. The synchronous frequency dividing circuit according to claim 1, 2 or 3, wherein