SU1338099A1 - Cycle synchronization device - Google Patents

Abstract

This invention relates to electret communication and shortens the timing of synchronization. The device contains the shift register 1, the decoder 2, and the El 3. The counter 4, the inverter 5, the blocking 6, and the installation 7 triggers are reintroduced. 2 Il. $ / V / ffjfff T And dtr / xaff {ecmtf (rasg) I (L with with 00 with; with Figure 1

Description

The invention relates to telecommunications and can be used in data transmission systems for frame synchronization in a discrete communication channel.

The purpose of the invention is to reduce the time taken to synchronize.

FIG. 1 shows the structural electrical circuit of the cyclic synchronization device; in fig. 2 - the structure of the service data unit.

The frame alignment device contains a shift register 1, a decoded 2, an AND 3 element, a counter 4, an inverter 5, a locking 6, and an adjusting 7 triggers.

The frame alignment device operates as follows.

The shift register 1 in the absence of frame synchronization receives a sequence of service n-bit data blocks, each of which contains a sequence of m regions of length S bits each (Fig 2), with t bits of the region occupied by the current coordinate (K) of the last bit of this region is relative to the end of the service data block and the remaining St bits are occupied by the phase constant (where j is 1-ha).

The input information, with each clock shift, is checked by decoder 2 configured to receive the phase constant. When the decoder detects the phase constant, the output translates the blocking trigger 6 into state 1 by the output signal and enables the readout of the coordinate K from the 1 register. The coordinates of the region whose phase constant is decrypted are written to the counter 4. With each clock pulse, the unit is subtracted from the contents of counter 4 After K clock cycles, the counter 4 is zeroed out and the inverter 5 generates a single signal at the first input of the element 3 (mouth

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The new trigger 7 at the start of phasing is set to the state at which it gives 1 on the direct output). Thus, at the moment the last bit of the service data block enters the shift register 1, element 3 is triggered and resets the blocking and setting triggers 6 and 7 to O. In this case, a single signal appears at the inverse output of the setting trigger 7, indicating that the end search cycle phase.

Claims (1)

The invention of the frame synchronization device containing sequentially connected shift register and decoder, as well as the AND element, the information input of the shift register being the device input, characterized in that, in order to shorten the timing, the serially connected counter and inverter, blocking and adjusting triggers, while the additional outputs of the shift register are connected to the information inputs of the counter, to the recording input of which is also locked to the signal input A trigger is connected to the output of the decoder, the output of the inverter is connected to the first input of the element, the second and third inputs of which are connected respectively to the outputs of the blocking and installation triggers, the output of the element I is connected to the installation input of the blocking trigger and the signal input of the installation trigger, the installation input and output of which are respectively the input signal of the start of phasing and the output of the device, and the clock input of the shift register is combined with the corresponding input of the counter and is striation input device. Compiled by V. Yavrumov Editor T. Laaearenko Tehred V. Kadar Proofreader V. But ha Order 4147/57 Circulation 638 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 fig 2