SU1515382A2 - Cyclic synchronization device - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to reduce the likelihood of false phasing. The device contains a shift register 1, a decoder 2, an element I 3, a counter 4, an inverter 5, a locking 6, and an adjusting 7 triggers. A delay element 8, a memory block 9, a prohibition trigger 10, a subtraction unit 11, two OR elements 13, 14, and an additional decoder 12, a counter 15, and an I 16 element are introduced into the device. The probability of false phasing is reduced by additional verification and protection current phase coordinate. 2 Il.

Description

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The invention of OTJIOCHTCH is to telecommunications, and can be used in data transmission systems for loop synchronization in a discrete communication channel, and is an improvement of the known device according to the main auth. No. 1338099.

The purpose of the invention is to reduce the likelihood of false phasing.

FIG. 1 shows a block diagram of the proposed frame alignment device; in fig. 2 - the format of the service data unit.

The device contains a shift register 1, a decoder 2, an AND 3 element, a counter 4, an inverter 5, a locking 6 and an adjusting 7 triggers, a delay element 8, a memory block 9, a ban trigger 10, a subtraction block 11, an additional decoder 12, the first 13 and the second 1A elements OR, an additional counter 15 and an additional element AND 16.

The device works as follows.

The shift register 1, in the absence of frame synchronization, receives a sequence of service n-bit data blocks, each of which contains a sequence of m regions with length S bits each (Fig. 2), with t bits of the region occupied by the current coordinate (K j ) of the last bit of this region relative to the end of the service data block, and the remaining St bits are occupied by the phase constant FC (where). The input information, with each clock shift, is checked by decoder 2 configured to receive the phase constant. The decoder 2, after detecting the phase constant, by the output signal transfers the blocking trigger 6 to state 1 and allows the coordinate K to be read from register 1: the area whose phase constant is decrypted and writing it to counter 4 through the additional element 16, at the beginning of the cycle phasing unit the signal from the inverse output of the inhibition trigger 10 is applied to the second input of the additional element AND 16, opening it, and from the direct output, the zero signal is fed to the input of the element 3, closing it.

Coordinate K: also enters the INPUTS of memory block 9 and block 11 you

read The output signal of the decoder 2 allows the subtraction of the current coordinate K; from the contents of memory block 9, arriving at the second input of block 11. In addition, the same signal, via delay element 8, the value of which is determined by the trigger time of subtraction unit 11, resolves Q to fix the result of the subtraction by additional decoders 12. For any result decoding the signal from the output of the first element OR 13 times - solves the recording of the current and 1 formation of the ordinate Kj into the block 9 of the memory. Additional decoder 12, configured to receive (K, - K: g- const, detecting L, the output signal True increases by one the contents

20 of the additional counter 15, and the output of the 1 signal. Incorrectly, the second element OR K sets the contents of the additional counter 15 to O. With each clock pulse, one unit is subtracted from the contents of counter 4, which is updated or confirmed every S clock cycles in counter 4 of the next value of the K coordinate; up to those

30 then, having counted the value of q, the additional counter 15 is triggered and by its output signal sets in 1 trigger 10 prohibitions (q is the number of undistorted coordinates Kj taken further, which determines the probability of writing to counter 4 undistorted coordinates; s) . The signal from the direct output of the prohibition trigger 10 will open the element And 3, and the signal of the inverse output will close the additional element And 16, blocking the counter 4 from the subsequent entries. Thus, the further operation of counter 4 will be protected from possible distortions of the K coordinate. After K cycles, counter 4 will be reset and Inverter 5 will generate a single signal at the input of the And 3 element (the set trigger 7 at the beginning of the phasing is set to 1 on the forward output) those. at the time of entry into

50 shift register 1 of the last bit of the service data block triggers element 3 and resets the blocking 6 and set 7 triggers to O, and a single 55 signal appears at the inverse output of the set trigger 7, indicating that the search for the cyclic phase has ended.

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As a trigger 10 prohibition can be used, for example, the trigger RS-type. Memory unit 9 may be implemented, for example, as a set of D-type triggers with combined write enable inputs and combined set inputs.

As the subtraction unit 11, a t-bit adder can be used, the forward inputs of which are supplied to be reduced, the d. To the inverse inputs to the subtracted. Additional decoder 12 can be implemented, for example, in the form of a serially connected comparison circuit of the type SP-1 (output signal of subtracting unit 11 with constant E) with a key (controlled output signal of delay element 8) and an inverter. The output, the key in the comparison, is the signal True, and the output of the inverter in the case of non-comparison, the signal Invalid.

Thus, the proposed device provides, in Comparison with the known, reduction of the probability of false phasing due to additional verification and protection of the current phase coordinate.

Claims (1)

Invention Formula Frame sync device auth. St. No. 1338099, characterized in that, for the purpose of 3826 reduce the likelihood of false phasing, a delay element, two OR elements, an additional AND element and a serially connected memory block, a subtraction block are added to it, add a decoder, an additional counter and a prohibition trigger, while the delay element input and the control input The subtraction unit is connected to the output of the decoder, the direct output of the inhibit trigger is connected to the fourth input of the And element, the output of the delay element is connected 15 to the control input of the additional decoder, the second output of which is connected to the first inputs of the first and second OR elements, and the first output is connected to the second input of the first OR element, the output of which is connected to the control input of the memory block, whose information inputs and inputs of the read block The subtractions are connected to the informational inputs of the counter, the installation input of the additional counter is connected to the output of the second OR element, the installation input of which and the installation inputs of the inhibit trigger, the counter and the block a memory connected to the adjusting input of the flip-flop SETTING novel developing and recording counter input connected to the output of the decoder via a further AND gate, a second input coupled to 35 inverse ban trigger output 20 thirty