JPH0316240A - Wiring method for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce wiring length and layout area by optimizing assignment of a through region, and evaluating cell line length so as to optimize the number of third through regions. CONSTITUTION:Based on the net, which expresses the connective information of fellow terminals of polycells, and the positions of the terminals, the wiring path, where, for example, the wiring length is minimum, is sought, and the through wiring position on a cell line is given initially. Next, the region, through which the through wiring passes, is portioned out into a first through region, where the signal line inside the cell is used as through wiring, a second through region for through wiring inside the cell, and a third through region, where through wiring is secured by widening the cell interval. And the cell line, where the cell line length has become long by the use of the third through region, is selected, and a net, which includes one or more third through regions, is searched, and through regions are reassigned, and the third through region within the cell line, which has become long by the processing 17, is deleted, and the length of the cell line is shortened. Hereby, wiring length and layout area can be reduced.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention relates to a wiring method for polycell type semiconductor integrated circuits.Prior art polycell type semiconductor integrated circuits generally have uniform high Cell rows can be constructed by arranging rectangular cells.Furthermore, it can be constructed by arranging multiple cell rows and wiring between the rows.However, when connecting terminals that span multiple cell rows, it is possible to construct cell rows. Although it is common to use through wiring that passes through the wiring, Figures 4 (a) to (c) show layout diagrams of through wiring. Penetration hook 31 is the first terminal, 32 is the second terminal, 33 is the center/k, 34 is the first penetration region slope 35 is the second penetration region, and 36 is the third penetration region. As shown in (a), the through wiring 24 is used to connect the first terminal 31 and the second terminal 32 by wiring across the cell rows 2l. Cell 3 as shown in (b)
When using the signal line inside cell 33 (to which terminal-to-terminal connection information, that is, the net is given) as the first penetration region 34, and when using the second penetration region for penetration wiring set in advance inside the cell 33. This can be realized in three ways: by using the cell 35, and by widening the interval between the cells 33 and using the third penetration region 36 as shown in FIG. 4(C).
However, when using the third through area 36, even if the length of the cell row 2l is long, the length of the entire wiring line and the area of the layout diagram (by changing the route of the wiring and the through wiring Figure 5 shows a layout diagram when the number of through wiring is changed. In Figure 5, 2l is a cell row, 22 is a terminal,
Reference numeral 24 indicates a penetrating region. In the case shown in FIG. 5(a), four penetrating regions 24 are used, and in the case shown in FIG. 5(b), two penetrating regions 24 may be used. Figure 5 (a
) has fewer horizontal wires than in Figure 5(b), so it is expected that the height will be lower.Through-wiring 2
If the third through region is used to route 4, the length of the cell row 2l may become longer. There is no difference
Also, depending on the number of third penetration regions, the length of the cell row 2l may vary as shown in Figure 5(C), resulting in a large area. Therefore, only one penetration region is assigned to each net. In other words, an efficient method for allocating the through area 24 is an important issue in wiring problems. 57 is each process, but the procedure for allocating a through area in the conventional wiring method configured as described above will be explained below. Process 5
In step 1, a degree of margin expressing the ease of use of the penetration area is set for each cell row from the lengths of the first penetration region, the second penetration region, and the cell row included in the cell row. When searching for a wiring route and using eight-penetration wiring, the position is searched, and in process 53 it is determined whether or not to allocate a through-hole area based on the margin set in GEL process 5l, and there is enough margin for allocation. If so, a penetration area is allocated in process 54 and the margin of the penetration area is updated in process 55. If there is no margin, another route is searched for in process 56.
If there is an unprocessed net, the process returns to step 52, and if there is no unprocessed net, the process ends.Problems to be Solved by the InventionHowever, with the above structure (as shown in FIG. As the number of wires gradually decreases, sufficient penetration area is not secured for the wiring that is allocated last in the order of allocation.Whether or not the penetration area is allocated depends on the order in which the wiring is done. If you want to use multiple through regions in one cell row taking into consideration L, there may be cases where only one through region can be used.Also, if the number of third through regions used differs from cell row to cell row. However, the present invention takes this point into consideration even though there is a problem of variations in the length of cell rows.Wiring of semiconductor integrated circuits that can realize reduction of wiring length and layout area by optimizing penetration area Means for Solving the Problems The present invention (1) finds a wiring route connecting the terminals based on a net expressing connection information between the terminals of a polycell and the position of the terminal. a through wiring position search means for initially determining the through wiring position on the cell row for the wiring that penetrates on the cell row; a first through region that uses a signal line inside the polycell as a through wiring; Allocate an area through which the through wiring passes from the through wiring position to a second through area for the through wiring prepared in the second through area and a third through area for the through wiring secured by widening the interval between the polycells. penetration area allocation means; cell row selection means for selecting a first cell row whose cell row length is increased by using the third penetration area; a net search means for searching for a first net in which there are two or more penetration regions used in the first net and one or more of the second penetration regions or the third penetration region is included; and reallocating the through areas existing on the first cell row by reducing the number of through areas allocated to the first net on the first cell row. A wiring method for a semiconductor integrated circuit, comprising shortening means for shortening the length of the first cell row by deleting a third through region included in the first cell row. With the above-mentioned structure, it is possible to allocate the penetration areas in the order of necessity regardless of the order in which the penetration wiring is performed, and it is possible to effectively use the penetration areas to reduce the wiring length.Also, it is possible to reduce the wiring length. By evaluating the number of third through regions and optimizing the number of third through regions, it is possible to control the length of the cell row and reduce the layout area. An algorithm for allocating penetration areas in circuit wiring methods is presented.
Figure 2 shows the algorithm for restricting the penetration area and reallocating the penetration area in this embodiment. Figure 3 shows a layout diagram to which this embodiment is applied.
11 to 18 indicate each process, so in Figure 2, 4
Although 1 to 46 indicate each process, in Fig. 3, 21
22 is a cell row, 22 is a terminal, and 23 is a weave 24 is a through area. The procedure for allocating the through area in the wiring method of the semiconductor integrated circuit of this embodiment configured as described above will be explained below. In process 11, ζ Based on the net expressing the connection information between the terminals of the polycell and the position of the terminal, find a wiring route that minimizes the wiring length to connect the terminal, and A through wiring position on a cell row is initially given to a wiring that penetrates on a row. In process 12, ζ is secured by increasing the distance between the first through area where the signal line inside the polycell is used as the through wiring, the second through area for the through wiring prepared in advance inside the polycell, and the interval between the polycells. The area through which the through wiring passes is distributed from the through wiring position given in process 1l to the third through area for the through wiring to be processed.In process 13, it is determined whether the processing of all nets has been completed. If there is a net of
Even if you repeat the process, there will be no unprocessed net. IL Processing 1
Moving on to 4, in process 14, the third penetration area is used to select a cell row with a longer cell line length.Next, in process 15, the cell line selected in process 14 is the same net. There are two or more penetration regions used for
In step 16, the wiring route of the searched net is changed to reduce the number of allocated through areas. Furthermore, by reallocating the penetration area, the third penetration area included in the cell row selected in process 14 is made unused.In process 17, the unused third penetration area is deleted. Figure 3 (a) shows process 16. Shortening the length of the cell row. FIG. 3(b) shows the layout state before applying process 16. 17
The procedure for restricting the penetration area in process 16 is as follows. In process 41, there is a third penetration area in the target cell row selected in process 15. If yes, proceed to process 42; otherwise, proceed to process 44.
Do the following. In process 42, the route is changed so that the third penetration area is not used.l. k In process 43, the third penetration area is made unused.In process 44, the route is changed so that the second penetration area is not used, and in process 45, the second penetration area is made unused.Furthermore, in process 46, the route is changed so that the second penetration area is not used. The third penetration area can be made unused by reassigning the net using the third penetration area included in the target cell row to the second penetration area that became unused in process 45. Process 15, 16 when shortening the length of a cell row. By applying 17 to the longest cell row, the lengths of multiple arranged cell rows can be made the same.
) in (friend cell row 21 R1, R2, R3, R4
The length of cell row 2l is shortened by deleting the third region from R2, which is the longest among them.By shortening the length of the longest cell row of cell row 2l, cell row 21 is
Even if the lengths of the lines are aligned and the layout area is reduced, the wiring routes above and below R2 of the cell row 21 overlap in FIG. However, regarding the same cell row 21, in the through area 24 connected to the same net, the through area 2
By reducing the number of through regions 24 in order from the net with the narrowest interval, the influence on the wiring length is reduced, and the length of the cell rows and layout area can be shortened. Effects As explained above, according to the present invention, it is possible to allocate the penetration regions in the order of necessity regardless of the order in which the penetration wiring is performed, and it is possible to effectively use the penetration regions to reduce the wiring length. Also, by evaluating the cell row length and optimizing the number of third penetration regions, it is possible to control the cell row length and reduce the layout area, which has a large practical effect on L1.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing an algorithm for allocating a penetration area in an embodiment of the present invention. FIG. 2 is a flowchart showing an algorithm for a method of limiting penetration areas in the embodiment. FIG. 3(b) is a layout showing the state before application of the same example. FIG. 4(a) to (c) is a layout showing the state before application of the same example. The layout showing the through area and the third through area is shown in Figure 5(a), (b) is the layout showing the state of the through wiring, and Figure 5(C) is the layout showing the state with variations in cell rows. Figure 6 is a flowchart showing the conventional penetration area allocation algorithm.

Claims (3)

[Claims] (1) In a polycell type semiconductor integrated circuit constructed by arranging a plurality of polycells including logic functions to form a cell row, arranging the cell rows in multiple rows and providing wiring between the rows, the terminals of the polycell A through-hole that initially determines a wiring route that connects the terminals based on a net expressing connection information between the two and the position of the terminal, and initially determines the through-wire position on the cell row for the wiring that passes through the cell row. Securing the wiring position by widening the distance between the wiring position search means, the first through area for using the signal line inside the polycell as a through wiring, the second through area for the through wiring prepared inside the polycell, and the polycell. a through area allocation means that allocates a region through which the through wiring passes from the through wiring position to a third through area for the through wiring to be used; cell row selection means for selecting a longer first cell row; and in the first cell row, there are two or more through regions used for the same net, and among them, the second through region or a net search means for searching for a first net including one or more third through regions; and changing a wiring route of the first net;
the first cell row by reducing the number of penetration regions allocated to the first net on the first cell row and reallocating the penetration regions existing on the first cell row; A wiring method for a semiconductor integrated circuit, comprising: shortening means for shortening the length of the first cell row by deleting a third through region included therein. (2) The wiring method for a semiconductor integrated circuit according to claim 1, wherein the shortening means aligns the lengths of the plurality of arranged cell rows by sequentially shortening the longest cell row. . (3) The semiconductor integrated circuit according to claim 1 or 2, wherein the shortening means reduces the number of through regions connected to the same net starting from a net having the narrowest interval. wiring method.