JP3617366B2 - Semiconductor integrated circuit design method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for designing a semiconductor integrated circuit using a master slice method.
[0002]
[Prior art]
In recent years, in the field of analog semiconductor integrated circuits, high-mix low-volume production has been remarkable, and development and manufacturing time has been required to be shortened. Therefore, the so-called master slice method is adopted, in which the element formation process of transistor elements, resistor elements, and capacitor elements is prepared in advance on a semiconductor substrate, and then only necessary wiring is performed to constitute a semiconductor integrated circuit. Yes. An element formed on a semiconductor substrate in the master slice method is referred to as “underlying element”. A conventional semiconductor integrated circuit design apparatus using the master slice method will be described below with reference to FIG.
[0003]
FIG. 15 shows an example in which an electric circuit element is assigned to a base element on a master slice using a conventional semiconductor integrated circuit design apparatus. In FIG. 15, reference numeral 1501 denotes a base element to which the transistor element T15a in the electric circuit is assigned, 1502 denotes a base element to which the transistor element T15b is assigned, and 1503 denotes a base element to which the transistor element T15c is assigned. Further, 1504 to 1507 are base elements to which a resistance element R15a connected to T15a is assigned, 1508 to 1511 are base elements to which a resistance element R15b connected to T15b is assigned, and 1512 to 1515 are connected to T15c. The base element to which the resistance element R15c is assigned is shown. Here, it is assumed that the assignment of base elements of the transistor elements T15a to T15c has already been determined. Conventionally, when assigning a resistance element in an electric circuit to a base element, an unassigned base element having a small resistance value is searched and the distance (external wiring length) from other circuit elements in the connection relationship is ascending in order. Only the allocation method was used. Therefore, when assigning in order of the resistance elements R15a to R15c, the assignment of R15a to the base elements 1504 to 1507 is determined first, and then the assignment of R15b to the base elements 1508 to 1511 is determined. Here, if the base elements are assigned in the order of the shortest distance from T15b connected to R15b, they become 1506 to 1509 (or 1507 to 1510), but 1506 and 1507 have already been assigned as base elements of R15a. Therefore, it cannot be assigned twice. Similarly, when assigning R15c, 1512 to 1514 are assigned in order, and when searching for a base element having a small resistance value close to T15c, the base element 1515 is assigned.
[0004]
[Problems to be solved by the invention]
If prioritizing the assignment of the circuit element to be assigned from the base element that shortens the external wiring length as in the conventional device, the circuit element assigned earlier obstructs the circuit element to be assigned later. If a nearby base element to be assigned is insufficient in a congested circuit as shown in FIG. 15 without being assigned to a position, a base element 1515 at a remote position is assigned. As a result, the circuit resistance element R15c cannot be assigned to a group of four positions, and there is a high possibility that the resistance element will vary in characteristics due to a difference in conditions during diffusion. Furthermore, since the length of the internal wiring connecting between the underlying elements necessary for realizing the resistance element becomes long, an adverse effect due to the wiring resistance occurs or unwiring occurs.
[0005]
The present invention solves the above-described conventional problems, and assigns resistance elements in a given electric circuit to base elements on a master slice in consideration of the connection relationship with other electric circuit elements. An object of the present invention is to provide a semiconductor integrated circuit design method capable of preventing variations in characteristics of resistance elements and shortening the external wiring length and the internal wiring length.
[0006]
[Means for Solving the Problems]
In order to achieve this object, the semiconductor integrated circuit design method according to the present invention has two allocation methods, namely, an element configuration priority allocation method and an automatic element selection allocation method when an electric circuit element is allocated to a base element on a master slice. Provided with a method, and evaluation of each arrangement shape by an evaluation function having parameters such as the adjoining balance element and the spread of the combination element, and the assignment determination process is performed by adopting the assignment result having the better evaluation value. This is realized by repeating the assignment process until assignment of all electric circuit elements to the base element is completed.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to FIGS. In the master slicing method, elements on the electric circuit are assigned to the master slice base prepared up to the element formation process of transistor elements, resistor elements, and capacitor elements on a semiconductor substrate in advance, and wiring is performed between the elements. Configure the circuit.
[0008]
FIG. 1 is a block diagram showing a hardware configuration of a semiconductor integrated circuit design apparatus according to an embodiment of the invention.
[0009]
The semiconductor integrated circuit device is a CAD (Computer Aided Design) device realized by a workstation or the like, and the display 101 is realized by a CRT (cathode ray tube), an LCD (liquid crystal display device), or the like. The input unit 102 is realized by a keyboard, a mouse, or the like. The CPU 103 is a central processing unit that controls the entire semiconductor integrated circuit device. The storage unit 104 is realized by a memory, a hard disk, or the like.
[0010]
FIG. 2 is a flowchart showing a processing procedure according to a semiconductor integrated circuit design method according to an embodiment of the present invention.
[0011]
In this design device, when assigning the resistance elements in the electrical circuit to the underlying elements on the master slice, the type, number, and connection method of the underlying elements used to realize the resistance value of the electrical circuit elements are used as element configuration data. Input is performed by the input unit 102 (step S201).
[0012]
Next, the wiring length between the terminals of the actual element is shorter than the method of searching for and assigning the underlying element described in the element configuration data input in S201 to the resistance element in the given electric circuit and the connection information of the electric circuit. By assigning to the underlying elements on the master slice by using the two methods of searching and assigning the underlying elements, and evaluating the respective arrangement shapes, the assignment result having the better evaluation value is adopted ( Step S202 ).
[0013]
Next, using a wiring area secured or specified in advance on the master slice, the wiring between terminals of the actual element is wired based on the connection information of the electric circuit by the maze method or the like, for example, in the same manner as the conventional CAD apparatus. This is performed (step S203). Here, the maze method is a method of searching for wiring paths in all directions by labeling the wiring grid in an order that ripples spread from the starting point, and if there is a wiring path, always find the shortest one There is a feature that can be.
[0014]
FIG. 3 is a flowchart showing a more detailed processing flow of the element assignment unit S202.
[0015]
The element assignment unit S202 reads the electric circuit information given first, and stores the connection information of the electric circuit elements (step S301).
[0016]
Next, element configuration priority assignment is performed (step S302). In the element configuration priority assignment, as described in the element configuration data in the read electric circuit information, a base element necessary for realizing each circuit element is searched and provisional assignment is performed. The circuit element arrangement shape assigned in step S302 is evaluated using an evaluation function described later, and the evaluation value is stored (step S303).
[0017]
Next, automatic element selection assignment is performed (step S304). In automatic element selection assignment, based on the electric circuit information read in step S301, a base element of the same type as the resistance element to be assigned is searched, and the distance from other electric circuit elements having a small resistance value and a connection relationship is searched. Temporary allocation is performed in order from the closest. The allocation is repeated until the difference between the circuit element value to be allocated and the element value of the base element to which temporary allocation has been performed becomes zero. The arrangement shape of the circuit element assigned in step S304 is evaluated using an evaluation function described later, and the evaluation value is stored (step S305).
[0018]
Next, the evaluation value of the arrangement shape by the element configuration priority assignment stored in step S303 and step S305 is compared with the evaluation value of the arrangement shape by automatic element selection assignment (step S306), and the evaluation value becomes better (smaller). The circuit element that has been temporarily assigned is formally assigned and determined (step S307).
[0019]
Next, it is determined whether or not all circuit elements have been assigned to base elements (step S308). If there is a circuit element that has not been assigned, the above-described method (steps S302 to S308) is performed. Repeat the assignment with. If the assignment has been completed for all the circuit elements in step S309, the element assignment process is terminated.
[0020]
FIG. 4 shows a master slice base on which an electric circuit element is to be assigned in one embodiment. In FIG. 4, 401 indicates a base element region in which 5 KΩ resistive elements are arranged, 402 indicates a base element region in which 10 KΩ resistive elements are arranged, and 403 indicates a base element region in which transistor elements are arranged. In addition, the type of the resistance element arranged in 401 and 402 is “SP”.
[0021]
FIG. 5 shows an electric circuit A to be assigned to the base element on the master slice. In FIG. 5, reference numerals 501 to 503 denote 20 KΩ resistance elements, and reference numerals 504 to 511 denote transistor elements.
[0022]
FIG. 6 shows a result of assigning the resistance elements 502 and 503 and the transistor elements 504 to 511 in the electric circuit A of FIG. 5 on the master slice base of FIG. 4 using this apparatus. In FIG. 6, reference numerals 601 to 610 denote the results of assigning the elements 502 to 511 in the electric circuit A.
[0023]
FIG. 7 shows a result of assigning the resistance element 501 in the electric circuit A of FIG. 5 to the base element in the middle of assignment in FIG. 6 in step S302 of this apparatus. In FIG. 7, reference numeral 701 denotes a resistive base element whose assignment has already been determined. Reference numeral 702 denotes a base element to which the transistor element 504 in the electric circuit A is assigned, and reference numeral 703 denotes a base element to which the resistance element 501 in the electric circuit A is assigned.
[0024]
Here, the electric circuit element 501 is given the notation method of the element configuration shown in FIG. 8 as circuit information. In FIG. 8, 801 indicates the type of the resistance element, 802 indicates the resistance value, and 803 indicates the configuration method. In this embodiment, “SP” means the type of resistance, “10000” means a resistance value of 10000Ω, and “2S” means that two base elements are connected in series. When 501 is assigned to a base element, a base element having the same type and resistance value as the resistance element described in the element configuration data is searched for, and the base element that is the closest to the other circuit elements 504 in connection relation Then, the one that has not been determined to be assigned to other circuit elements is selected and assigned. In this embodiment, since the configuration method is described as two in series, the circuit element is assigned to the base element by repeating this operation twice.
[0025]
Next, in step S303 of this apparatus, the arrangement shape of the element configuration priority assignment result in step S302 is evaluated, and the evaluation value is stored. Hereinafter, an evaluation function used in the present apparatus when evaluating the arrangement shape will be described. Equation 1 shows an evaluation function when ac is assigned to a certain circuit element C.
[0026]
F (ac) = w1 × L (ac) + w2 × I (ac) + w3 × D (ac) + w4 × N (ac) (Equation 1) In Equation 1, F is the evaluation value, L is the external wiring length, I represents the internal wiring length, D represents the distance from the assignment determination base element group, and N represents the adjacent element value. The distance D to the assignment-determined base element is obtained as the sum of the distances from the center point of the base element group whose assignment has already been determined in the circuit element C to the center point of each base element that has not been assigned. The adjacent element value N is set to 1 when a base element adjacent to the assigned base element is already assigned as another circuit element, and is set to 0 otherwise. Further, w1 to w4 indicate the weights related to the respective evaluation parameters. The evaluation value F is obtained as a sum of values obtained by multiplying each evaluation parameter value by the respective weighting factor.
[0027]
FIG. 9 shows a result of assigning the resistance element 501 in the electric circuit A of FIG. 5 to the base element in the middle of assignment in FIG. 6 in step S304 of the present apparatus. In FIG. 9, reference numeral 901 denotes a resistive base element whose assignment has already been determined. Reference numeral 902 denotes a base element to which the transistor element 504 in the electric circuit A is assigned, reference numerals 903 to 906 denote base elements to which the resistance element 501 in the electric circuit A is assigned, and reference numeral 907 denotes a base element group. In automatic element selection assignment, until the resistance value of the circuit element 501 to be assigned is satisfied, the assignment positions of other circuit elements that are connected in the same type of base element that has been given as circuit information and have a small resistance value Search in ascending order starting from, and make assignments. In this embodiment, the resistance base elements 904 of the same type that are close to the circuit elements 902 that are connected are assigned in order. After assigning the base element, find the difference between the resistance element value to be assigned and the resistance value of the assigned base element. If the difference is not 0, update the assignment target resistance element value to the difference value obtained. Then, the next base element is searched. In this way, 903 and 905 are assigned sequentially, and finally 906 is assigned. At this time, since the difference between the resistance element value to be assigned and the resistance value of the assigned base element becomes zero, the assignment of the circuit element 501 is terminated.
[0028]
Next, in step S305 of this apparatus, the arrangement shape as a result of automatic element selection / allocation in step S304 is evaluated, and the evaluation value is stored.
[0029]
Next, the evaluation values of the two assignment results stored in steps S303 and S305 are compared in step S306 of the present apparatus. In this embodiment, when the evaluation values stored in S303 and S305 are compared, the evaluation value stored in S305 is larger than the evaluation value stored in S303. This is the evaluation value of the arrangement shape assigned by the automatic element selection assignment in step S304 as the evaluation value stored in step S305. In the present embodiment, the assignment method in step S304 is as shown in FIG. Since only one base element 906 is assigned away from the base element assigned to the other, the distance between the base elements constituting the circuit resistance element 501 is increased, and the value of Iy in the evaluation function formula is accordingly increased. This is because the evaluation value as a whole is also increased. Therefore, the process proceeds to step S307.
[0030]
In step S307, the assignment result obtained in step S302 is adopted, and assignment determination processing for the base element is performed according to the assignment result. It becomes impossible to assign other circuit elements to the base element determined to be assigned by this assignment determination process. When the assignment process is completed for all the base elements to be assigned, the process proceeds to step S309.
[0031]
In step S309, it is determined whether all circuit elements in the given electric circuit have been assigned to the lower level of the master slice. If the assignment has been completed, the element assignment process is terminated. If there is a circuit element for which assignment has not been completed, assignment processing for the remaining circuit elements is continued.
[0032]
Next, an embodiment of assigning resistance elements to which an element configuration method using base elements having different resistance values is given will be described.
[0033]
FIG. 10 shows the electric circuit B to be assigned. 10, reference numerals 1001 and 1002 denote resistance elements of 20 KΩ, reference numerals 1003 and 1004 denote resistance elements of 25 KΩ, and reference numerals 1005 to 1008 denote transistor elements. FIG. 11 shows the result of assigning the circuit elements in FIG. 10. 1101 is assigned 1001, 1102 is assigned 1002, 1103 is assigned 1003, and 1104 to 1107 are assigned 1005 to 1008. The resistance element 1004 is not assigned. FIG. 12 shows the result of assigning the resistance element 1004 to the base of FIG. 11 in the middle of assignment in step S302. In FIG. 12, reference numerals 1201 to 1203 and 1205 to 1208 denote base elements that have already been assigned, and 1204 denotes a result of assigning the resistance element 1004.
[0034]
Here, a notation method of the element configuration of the resistance element 1004 is shown in FIG. “SP 5000” in the first term in FIG. 13 means one base element of resistance type SP of 5000Ω, and “SP 10000 * 2S” in the second term in FIG. 13 is a ground element of resistance type SP of 10,000Ω. Are connected in series, and the resistance element 1004 expresses that these resistors are further connected in series.
[0035]
FIG. 14 shows a result of assigning 1004 resistance elements to the base of FIG. 11 in the middle of assignment in step S304. In FIG. 14, reference numerals 1401 to 1403 and 1405 to 1408 denote base elements that have already been assigned, and 1404 denotes a result of assigning 1004. In the same manner as in the embodiment for assigning the electric circuit A, the two assignment results in the electric circuit B are evaluated in step S305. In step S306, the evaluation values are compared, and an assignment result that improves the evaluation value is adopted. In the assignment of the resistance element 1004 in the electric circuit B, the automatic element selection / assignment step S302 1204 is assigned as a group of base elements, and the distance from the transistor element 1407 in the connection relationship is short, so the arrangement shape evaluation value Get better. In contrast, in the element configuration priority assignment step S304 1404, only one 5KΩ resistive element is allocated apart, and two 10KΩ resistive elements are far away from 1407, so the arrangement shape evaluation value is deteriorated. . Therefore, the assignment result in step S302 shown in FIG. 12 is adopted.
[0036]
In this way, there are two allocation methods to the base element, and the allocation shape is evaluated for each of them. As a result, by adopting the one that improves the evaluation value, the connection relationship with other circuit elements is taken into consideration. Thus, it is possible to obtain an arrangement result in which variation in characteristics is less likely to occur within a circuit element composed of a plurality of bases.
[0037]
【The invention's effect】
According to the semiconductor integrated circuit design method of the present invention, element configuration assignment and automatic element selection assignment are performed on the underlying element on the master slice, and the assignment with improved arrangement shape is employed to compensate for the disadvantages of the respective assignment methods. On the other hand, it is possible to suppress the occurrence of variations in resistance element characteristics and deterioration in resistance value accuracy due to wiring resistance in accordance with the assignment state of other circuit elements to the underlying element.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a hardware configuration of a semiconductor integrated circuit design apparatus according to an embodiment of the present invention. FIG. 2 is a flowchart illustrating a processing procedure of a semiconductor integrated circuit design method according to an embodiment of the present invention. FIG. 4 is a flowchart showing an example of a more detailed processing procedure of the element allocating unit. FIG. 4 is a diagram showing a master slice base used in one embodiment of the present invention. FIG. 5 is an electric circuit to be allocated in one embodiment of the present invention. 6 is a circuit diagram of FIG. 6A. FIG. 6 is an explanatory diagram showing a process of assignment to a base element in one embodiment of the present invention. FIG. 7 is an explanatory diagram of a method for allocating to a base element in step S302. FIG. 9 is an explanatory diagram of an element configuration definition method in the embodiment. FIG. 9 is an explanatory diagram of a method for assigning to a base element in step S304. FIG. FIG. 11 is an explanatory diagram showing a process of assignment to a base element in one embodiment of the present invention. FIG. 12 is an explanatory diagram of a method for assigning to a base element in step S302. 13 is a diagram illustrating a configuration method of a resistance element. FIG. 14 is an explanatory diagram of an allocation method to a base element in step S304. FIG. 15 is an explanatory diagram illustrating an example of a conventional element allocation method.
DESCRIPTION OF SYMBOLS 101 Display apparatus 102 External input device 103 Central processing unit 104 Memory | storage device 401 5Kohm resistance base element area | region 402 10Kohm resistance base element area | region 403 Transistor element area | regions 501-503 Resistance element 504-511 Transistor element 601-602 Assigned to a base element Assigned resistance elements 603 to 610 Transistor element 701 assigned to base element Resistive element 702 assigned to base element Transistor element 703 assigned to base element Resistive element 801 assigned to base element Element type 802 element Value 803 Element configuration 901 Resistor element 902 assigned to the base element Transistor elements 903 to 906 assigned to the base element Resistor element 907 assigned to the base element Resistor element assigned to the base element Group 1001 to 1004 Resistive elements 1005 to 1008 Transistor elements 1101 to 1103 Resistive elements 1104 to 1107 assigned to the base element Transistor elements 1201 to 1203 assigned to the base element Resistive element 1204 assigned to the base element Resistive elements 1205 to 1208 assigned to the base element Transistor elements 1401 to 1403 assigned to the base element Resistive element 1404 assigned to the base element Resistive elements 1401 to 1408 assigned to the base element Transistor elements 1501 to 1503 determined by the transistor elements 1504 to 1515 assigned to the base element Resistive elements assigned to the base element

Claims (3)

A method of designing a semiconductor integrated circuit by allocating and wiring an element in an electric circuit designed as a semiconductor integrated circuit to an actual element formed in advance on a master slice,
A first step of trying two assignment methods for an unassigned electric circuit element to a base element for which assignment is not decided;
The results of the allocation method of the two types, a second step of obtaining the evaluation value by the evaluation using the evaluation function,
A third step of comparing the evaluation values of the two assignment results and adopting an assignment result that improves the evaluation value to determine assignment to the underlying element;
Said second step of evaluating the assignment result comprises:
The distance between the terminals that occurs when another electrical circuit element that is connected to the assignment target electrical circuit element is assigned to the base element, and the distance that occurs when the assignment target electrical circuit element is assigned to the base element A method for designing a semiconductor integrated circuit, characterized in that a sum of values obtained by multiplying distances by individual weights is used as an evaluation value. One of the allocation methods used in the first step is:
2. The design method of a semiconductor integrated circuit according to claim 1, which is an element configuration priority assignment method for searching and assigning a base element suitable for the element type based on an element configuration list registered in advance for each electric circuit element. . One of the allocation methods used in the first step is:
2. An automatic element selection assigning method in which assignment is performed in order from a base element in which a distance between terminals generated when assigned to a base element of another electric circuit element that is connected to the target electric circuit element is shortened. 2. A method for designing a semiconductor integrated circuit according to 1.

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