JPH02303142A - Automatic layout in analog lsi - Google Patents

Abstract

PURPOSE:To optimize a whole layout by a method wherein a wiring operation is executed against a plurality of arrangement results, an influence by the arrangement results is reduced, a plurality of layout patterns are prepared, a degree of freedom of an arrangement wiring operation is enhanced and the arrangement wiring operation is improved in a top-down manner after a bottomup layout has been designed. CONSTITUTION:While an obtained DR tree is used, an automatic arrangement wiring operation regarding a layout element with reference to individual nodes is executed from a leaf toward a root in a bottom-up manner. Regarding an obtained chip layout, an external terminal position of a block corresponding to the individual nodes is optimized; when the terminal position is changed, a wiring operation of this part is executed again. When an empty region is a designated value or higher, several layouts out of the nodes at a level (i) are cancelled; a layout operation is executed again. In this manner, a layout pattern against the individual nodes of the DR tree is improved, i.e., the terminal position is optimized and the empty region is improved from the root toward the leaf in a top-down manner.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] This application is applied to analog LSI using bipolar process.
This paper relates to the design automation of layout patterns. (Conventional technology l Analog LSI layout pattern design has stricter restrictions on electrical characteristics than digital LSI layout pattern design, so it has been said that it is difficult to automate. Therefore, manual design is common. However, in recent years Due to the increasing complexity of the circuit as the circuit scale increases,
Automation of layout design for analog LSIs is becoming more important, and at the research stage there is a method that adapts the master slicing method, which processes only wiring on a base on which elements are built in advance, to analog LSIs.
Digital Embedded Master Slice LSIJ (IEICE technical research report, VLD87-28.1987-12
) Ya, Semi-automatic analog layout system that interactively supports manual design "About a module design support system for analog LSI" (N, child of the Institute of Information and Communication Engineers 19
1989 Spring National Conference, 1989-3), etc. have been reported. [Problems to be Solved by the Invention] (1) Placement Problem Since the shapes and sizes of elements such as transistors, resistors, and capacitors handled in the bipolar process vary widely, it is necessary to reduce the gaps that occur when placing the elements, that is, the empty areas. It has been difficult with conventional methods to arrange them so that they are small. The techniques mentioned in the previous section have solved this problem, but in order to clarify the problem addressed by the present invention, we will describe the avoidance measures used in these methods. In the former, the problem of empty space is solved by making the shape of the element uniform and making the size constant. In the latter case, the layout designer attempts to reduce free space through conversational operations. In order to fundamentally solve the problem, the present invention automatically arranges elements in arbitrary shapes. Furthermore, due to electrical characteristics, there are elements that should be placed close to each other or separated from each other, and this needs to be taken into consideration. (2) Wiring problem Another issue is the wiring problem. Digital LSI
In , a method of securing a wiring area called a channel and wiring using two layers has been automated and technically established. However, in bipolar process analog LSIs, the challenge is to minimize the total wiring length by using only one layer of wiring as much as possible and effectively utilizing the area on the device where the wiring can pass. This is a problem that cannot be solved using conventional methods. It is said that wiring methods called ``maze method'' and ``line segment search method'' are effective for solving the problem of being able to pass wiring on the element and giving priority to first-layer wiring, but the wiring results of these wiring methods are The quality of the wiring greatly depends on the placement results of the elements, and no placement method has been reported so far that takes into consideration how to improve the wiring results of these wiring methods. The present invention has been devised in view of the above points, and an object of the present invention is to provide a new and useful automatic layout method for analog LSIs that eliminates the above-described conventional problems. [Means for Solving the Problems] In order to achieve the above object, the present invention first automatically groups elements in a circuit diagram into several groups in consideration of their electrical characteristics, and then groups them hierarchically. By repeating this, a group of elements is expressed as a tree structure. That is,
A group may consist of at most several children's groups, and each child's group may consist of at most several grandchildren's groups. For the tree structure obtained in this way,
Placement and wiring can be performed for each group (f). Elements that should be placed close to each other are confined within the group, and a layout pattern can be designed that takes electrical characteristics into consideration. Next, each A placement and wiring method for each group will be described. In the present invention, placement and wiring within a group are processed separately. As a first step, placement processing is performed with the aim of minimizing the free space between elements, and placement candidates are In the second step, we devised and adopted a method of performing wiring processing with priority to the first layer for all the candidates obtained in the previous step, and then selecting several more candidates from among them. When the layout of the target group is completed, move on to the layout of the group in the higher hierarchy that has that group as a child.There are multiple layout patterns for child groups, so you can In layout design, the optimal layout pattern is selected by considering the influence of each child on each other.Here, since the number of children in each group is limited, the shape of the children's group is It is now easy to minimize the free space even if it is arbitrary, and it is possible to suppress the increase in computer usage time when applying wiring to multiple candidates.In addition, it is possible to reduce the tree structure from the lower layer to the bottom. After designing the layout of the amplifier, the layout pattern is optimized by improving the placement and wiring in a top-down manner. Therefore, by applying the automatic layout method of the present invention, the layout pattern can be optimized by taking electrical characteristics into consideration. , it is possible to automatically place and route a layout pattern consisting of elements of arbitrary shape with the goal of minimizing free space and giving priority to first-layer wiring. By assembling them hierarchically, we can limit the number of objects (groups of children) to be processed at once in the next stage of placement and wiring, localize the problem and speed up the processing, and also reduce electrical We have devised ways to obtain layout patterns that take characteristics into consideration.In addition, placement processing and wiring processing are inseparable from each other, and although it is said that it is difficult to process them simultaneously, placement and wiring are performed for each group. Since the process is processed in the order of , and then moves on to the next layer, the overall effect can be expected to be the same as processing placement and routing at the same time.Furthermore, (1) In order to perform routing for multiple placement results, By reducing the influence of placement results on the quality of wiring and (2) improving the degree of freedom in placement and routing in groups one level higher, by preparing multiple layout patterns that are the placement/routing results for a certain group. (3) By performing top-down improvements after bottom-up layout design,
We are trying to optimize the overall layout. Embodiment 1 First, a layout model of a bipolar process to which the present invention is applied will be explained, and then an embodiment of the present invention will be explained. (1) The target is the layout and wiring of functional blocks in the LSI of the target bipolar process at the element level (transistors, resistors, etc.). The entire LSI is realized using the same floor planning and building block automatic layout techniques as digital LSIs. (2) Layout pattern of elements A layout pattern corresponding to each element is prepared in advance. An example of a layout pattern is shown in Figure 1 (
Shown in a) to (e). Figures (a) and (b) respectively show the basic shape of the transistor and a state in which the terminal positions can be replaced, and (C) to (e) respectively show the basic shape of the resistor element and the desired resistance value when expanded and contracted. It shows the flat state and the bent state. Elements whose shape changes are expanded and contracted when placed based on the basic shape. The element also has terminals for wiring connections. (3) Element and design rule The outer shape of the element is rectangular, and as long as the outer shapes do not overlap,
Design rules regarding minimum spacing are guaranteed (Fig. 1 (h)
). (4) Wiring layer and wiring area Metal is used for wiring, and if the first layer cannot be wired, a second layer of metal is also used for wiring. At this time, in addition to being able to use the area other than the element as a wiring area, as shown in FIG.
As shown in g), there is also a region on the element where wiring can be made. Kokinjo/J- and E Method Each step of the automatic layout method according to the embodiment of the present invention is shown below. [Hierarchization process of 1-layer circuit diagram information First, the information necessary for the layout of the target circuit is
Express it in a tree structure as shown in the figure. That is, using a rule-based system, rules that take electrical characteristics into consideration are applied to circuit diagram information to perform hierarchical grooving. Hereinafter, the circuit diagram information expressed in a tree structure will be referred to as a DR tree. [21 Placement and Routing Process Using the obtained DR tree, automatic placement and routing is performed bottom-up from the leaf to the root for the layout elements for each node. [3] Layout optimization step The external terminal positions of the blocks corresponding to each node are optimized for the obtained chip layout, and if the terminal positions are changed, rewiring is performed for that part. Also,
If the free space is greater than or equal to the specified value, the layout of some of the nodes at level i is canceled and re-layout is performed. In this way, the layout pattern for each node of the DR tree is improved, that is, (1) optimization of terminal positions and (2) improvement of free space are performed in a top-down manner from the root to the leaves. Each step will be explained in detail below. Generation process of DR tree for placement and routing (see FIG. 2) [DR tree definition] (1) A node whose bus length from the root is i is called a level i node. Also, let Li be the layout element corresponding to the node at level i. (2) The layout element Li is a functional block such as an oscillation 6, an operational amplifier, and a converter, which is composed of 20 to 200 elements. (3) Layout element L of the lowest node that becomes a leaf
m is an element such as a transistor or a resistor. (4) There are at most several level i nodes at level i+1
node as a child. (5) At each level, the estimated area of the layout element Ll is configured to fall within a specified range. (6) Layout elements Li corresponding to several level i+1 nodes that are children of one node at level i
+1 adds the following conditions to each other. ■It is necessary to configure specific circuits such as current mirror circuits and differential amplifier circuits and place them adjacent to each other. ■Have a strong connection request. ■Isolation can be shared. (Definition route) A DR tree is generated by using a rule-based system to iteratively execute the three types of rules listed below in order from the bottom up, and sequentially determining the parent node from several nodes. Ru. [Selection Criteria Rule Details] Determine the selection criteria for node grooving. Conflicts between rules are handled based on the priority of each rule. For example, (Rule A): The details of the nodes constituting the differential amplifier circuit are targeted for grooving. (Rule B): Node details with mutually strong wiring requirements are targeted for grooving. (Rule C): Grouping targets are node details that can share isolation. When there are three rules, the priorities are given in the order of A, B, and C. [Grooving rule details] A node to be grooved is determined based on the determined selection criteria, and a parent node is generated. [Backtrack Rule Group] When the expected area of the corresponding layout element between nodes at level i is greater than or equal to a certain value, grooving is stopped and some nodes at level i are deleted. A ray corresponding to each node based on the DR tree. The layout of each out element is automatically designed in the order of (1) placement (2) wiring while maintaining the hierarchical structure of the DR tree while taking into account the element shape. Design is processed from the bottom up, so when you place and route a node at level i, the placement and routing for its child nodes, i.e. nodes at level i+1, have already been completed, and the layout is a vertical rectangle, horizontal rectangle, square. Layout candidates are prepared for several external shapes. (1) Based on the multiple layout candidates prepared for the automatically placed layout element Li+1, use the minimum free space as the objective function,
Generate several configurations with different shapes. (2) For each automatic wiring arrangement, perform actual wiring between Li+1, that is, within L1, using the first layer metal, and store multiple layout results with a high first layer wiring rate (for nodes at level i (placed and routed layout candidates were generated). The above processing is performed up to the root of the DR tree. Layout optimization process Layout patterns designed from the bottom up may leave room for macroscopic improvement, so we will improve the placement and routing from the top down in the following two points:
The wiring left unwired in the bottom-up wiring is done using the second layer of metal. (1) Terminal position improvement layout element If the decrease in the wiring rate of the first layer in the L construction is due to the external terminal position of Li+1, the L
For i+1, the external terminal position improvement is added to the objective function and re-layout is performed. (2) Free space improvement (Figure 3) The area of layout element Li is Li+1 included in it.
If the area is larger than the total area by a certain value, that is, if the free area is large, Li+1 is re-layouted to improve the free area. The above process is performed for Li that is the target of re-layout, and this process is continued until L1+1 becomes the lowest level. Effects of the Invention 1 As described above, according to the present invention, a layout pattern consisting of elements of an arbitrary shape is automatically placed and routed with the goal of minimizing free space and 1-layer wiring invasion, taking into consideration electrical characteristics. This makes it possible to significantly shorten the time required for the layout design process of a bipolar process analog LSI, which has conventionally been designed manually.

[Brief explanation of the drawing]

Figures 1 (a) to (h) are diagrams for explaining the layout model, and Figures (a) to (e) are examples of a transistor and a resistor element, respectively, and the transistors are removable. Does it have terminals, and does the resistor have to expand and contract its basic shape to match the desired resistance value? The figure (0 to (g) is an example in which the wiring passes over the element, and the figure (h) shows the relationship between the external shape of the element and the design rule. is a diagram for explaining a DR tree. Figure 3 is a diagram for explaining an example of free space improvement.
In the figure, there are several dark colored rectangles indicating empty areas. Ll... Layout element Lm corresponding to the root node
...Layout element Li corresponding to the leaf node...
・Layout element corresponding to the node of Lebel i Representative Patent Attorney Takeshi Sugiyama (and 1 other person) Figure 3 Example of free space improvement Basic shape Terminal positions can be swapped (a)
(b) Basic shape Desired resistance value Bend (c) (d)
(e) Figure 1 Layer (f) (g) Model

Claims (1)

[Claims] 1. Automatically grouping elements in a circuit diagram of an analog LSI into several groups in consideration of electrical characteristics,
This process is repeated hierarchically to represent a group of elements in a tree structure, and the process includes an automatic wiring process for each layer in which placement and routing is performed for each group on the tree structure obtained through the above process. An automatic layout method for analog LSI, characterized by: 2. The automatic wiring process includes: performing a placement process with the aim of minimizing the free space between elements, and preparing a plurality of placement candidates; performing a wiring process that prioritizes one layer for all the candidates obtained in the process; 2. The automatic layout method for an analog LSI according to claim 1, further comprising the step of selecting some candidates from among the candidates.