JPH04167073A - Channel wiring processing method - Google Patents

Abstract

PURPOSE:To obtain a high connection rate even if there is an obstacle in a channel by preferentially assigning main lines which are small in the number of assignable tracks. CONSTITUTION:The terminals of cell arrays 1 and 2 arranged on a substrate are connected by using main lines 11a - 14a assigned for tracks in the channel 3 between the cell arrays 1 and 2 while the obstacle 4 in the channel 3 is by- passed. Then a position restriction graph including a main line 13a which is not under position restrictions, main lines 12a and 14a which are restricted by other main lines, and the obstacle 4 in the channel is generated and the respective main lines 11a - 14a and obstacle 4 are weighted and given order. Therefore, the main line 11a whose assigned truck is restricted by the obstacle 4 can be assigned preferentially to other main lines 12a - 14a. Consequently, the high connection rate is obtained even when there is the obstacle 4 in the channel.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention provides a method for connecting a plurality of wires for connecting terminals of cell rows arranged on a substrate to tracks of channels between cell rows to prevent obstructions in the channels. The present invention relates to a channel wiring processing method that enables automatic allocation while avoiding the problem.

[Conventional technology]

FIG. 1 is a schematic diagram showing cell rows formed on a substrate and channels between them, and shows terminals 18 to 1d in cell row 1.
and terminals 28 to 2d in cell row 2, for example, terminal 2
When connecting a and lb, la and 2c, 2b and ld, and Ic and 2d, four wires 11.12.13.
14 is allocated within the channel. Conventionally, this allocation was performed in the following procedure.

That is, as shown by the broken line in FIG. 1, a wiring grid 8 is set at a position where wiring can be placed within the channel 3,
The main lines 11a to 1 in the wiring are placed in the grid, that is, in the tracks 98 to 9d, which are parallel to the cell rows 1 and 2 while avoiding the obstacles 4.
4a, and branch lines 11b, 12b = 14 for grids oriented orthogonally to cell row 1.2, i.e. columns 10a to 10m.
b, llc to 14c are allocated, respectively.

By the way, in FIG. 1, for example, the terminal 1c of the cell row 1
and terminal 2c of cell row 2 are located above in the same column 10, so support! 5112c and 14b do not overlap, the trunk lines 12a and 14a are allocated to a track closer to the cell row 1 side than the trunk line 12a, or in other words, the trunk line 12a is allocated to a track closer to the cell row 2 side than the trunk line 14a. There is a need. Regarding the other main lines 11a and 13c, such consideration is not necessary between each other and between the main lines 12a and 14a.

Therefore, such a position constraint relationship is expressed as a position constraint graph using a directed graph as shown in FIG. The position constraint graph shows each of the main lines 11a and 12 of the four wires 11 to 14.
Regarding the vertices ■ to O representing a, 13a, and 14a, respectively, the vertices ■ and O that have a positional constraint relationship are placed at appropriate distances in the upward and downward directions, and an arrow pointing from vertex 0 to vertex ■ is placed between them. is attached to represent the connection relationship, and the other vertices ① and 0 are arranged side by side regardless of this.

For example, in FIG. 5, the relationship between vertex 0 → θ, which is a connected component, is as described above. Vertex 0 is located on the track closer to cell row 1 than vertex θ.
This means assigning it to a truck closer to the side. The other vertices (2) and 0 are independent components without such restrictions.

Next, in which order is the wiring 11 placed on any of the tracks 98 to 9d?
The order in which to allocate the 14 main lines 11a to 14a is determined. In the graph of Figure 5, the ranking is based on the number of all vertices included in the path from this starting point to another vertex (■) along the arrow, starting from the vertex where the arrow does not enter, ■, 0.0. 5) is taken as the rank of each vertex, and the vertices are sequentially allocated from the highest numerical value to the lowest numerical value indicating the rank.

In other words, in the graph of Figure 5, no arrows enter the vertices ■, O, and 0, so the arrows are traced using these as starting points, but since the vertices ■, 0, and 0 are starting points, the rankings for all of them are The rank is “1”, and the vertex ■ is also ranked “2”.
”, therefore, the allocation to the tracks first gives priority to the main line 12a indicated by the vertex θ, and then the vertices ■, 0.0
This is done for the main lines indicated by , lla, 13a, and 14a. If the rankings are the same, allocation can be made from either trunk line.

Next, the main line 11 of the wiring according to the order determined as described above.
The wiring procedure for a to 14a is assigned to channels 98 to 9d according to the flowchart shown in FIG.

FIG. 6 is a flowchart showing the wiring allocation process according to the conventional method.
d, when allocating trunk lines to tracks within a channel in the same manner as shown in FIG. Positional constraints between trunk lines regarding allocation positions are created as a directed graph in which each trunk line is a vertex and upward and downward constraints are expressed by arrows (step Tl).

Next, based on this positional constraint graph expressed as a directed graph, if a vertex that no arrow enters among the vertices is the starting point, the number of all vertices included in the path from this starting point to other vertices by following the arrow. The order of allocation to the tracks is determined by making the order of the vertices to be the order of the vertices (step T2).

It is determined whether or not there is a trunk line that has not been allocated to a track yet and can be allocated to a track (step T3). If there is a trunk line, the vertex with the largest value indicating the rank of the corresponding vertex Give priority to the main line corresponding to , and assign it to the track as close to cell column 2 as possible, and delete the vertices corresponding to that main line from the position constraint graph (
Step T4).

Returning again to step T3, it is determined whether or not there is a main line, and if there is, the above-described process is repeated, and if there is no main line, the process ends.

FIG. 7 is a schematic diagram showing the result of wiring according to the conventional wiring processing method as described above. First, the main line 12a corresponding to the highest vertex (1) whose numerical value indicating the rank is "2" is connected to cell column 2. It is assigned to the nearest track 9d. Since the rankings of the other vertices ■ and 0.0 are both "l", it is possible to simply repeat the above process and assign the main lines f3a and 14a corresponding to the vertex 0.0 to the tracks 9c and 9b, respectively. . However, for the main line 11a corresponding to the vertex {circle around (2)}, the allocation ends with no track available for allocation.

As a result, as shown in FIG. 7, the main lines 12a, 13a,
14a can be allocated without any problem, but main line 11
As for a, it becomes impossible to allocate it.

[Problem to be solved by the invention]

In the conventional method as described above, if there is an obstacle in the channel, the obstacle is not taken into consideration (because the main line is assigned to the track, the track usage efficiency is poor and the wiring is not possible). There were problems such as a large number of trunk lines, a reduction in connection efficiency, and the need for many trucks to solve this problem.

The present invention has been made in view of the above circumstances, and its purpose is to set vertices corresponding to obstacles in the channel in a position constraint graph and assign ranks to these vertices, so as to detect the presence of obstacles. In order to avoid inconveniences such as mutual interference between branch lines, priority is given to trunk lines that are subject to restrictions during allocation, in other words trunk lines with a small number of allocatable tracks. An object of the present invention is to provide a channel wiring processing method that allows a high efficiency to be obtained.

[Means to solve the problem]

The channel wiring processing method according to the present invention creates a position constraint graph that includes trunks that are not subject to position constraints, trunks that are constrained by other trunks, and obstacles in the channel, and Give weight to each item and rank them.

[Effect]

According to the present invention, it is thereby possible to allocate a trunk line whose tracks to be allocated are restricted by an obstacle with priority over other trunk lines.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on drawings showing embodiments thereof.

FIG. 1 is a schematic diagram showing cell rows formed on a substrate to which the method of the present invention is applied and channels between them.
indicates a cell column, and 3 indicates a channel. As mentioned above, in FIG. 1, the wirings 11 to 1 in which terminals 1a to 1d of cell row 1 and terminals 2a to 2d of cell row 2 are assigned to channel 3
4, among the wiring grids 8 set in channel 3, a grid oriented parallel to cell row 1.2, that is, a grid with main lines 11a to 14a in the track, and a grid oriented perpendicular to cell row 1.2, That is, branch line 1 is connected to columns 10a to IOs+.
1b'' 14b and llc to 14c, the following positional restrictions are required between the main lines 11a to 14a of the wirings 11 to 14.

For example, for the main line 11a, the track 9 under the obstacle 4
d cannot be placed without using the branch line 12c, it is necessary to place the main line 11a closer to the cell row 2 side than the obstacle 4 between the in-channel obstacle 4 and the main line 11a, and the branch line 12c and 14b are arranged using the same column IOK, so that the main line 12a is arranged closer to the cell row 2 side than the main line 14a so that the branch lines 12c and 14b do not overlap.

Regarding other trunk lines 13a, trunk lines 11a, 12a, 1
4a and the obstacle 4, no such positional restriction occurs.

Based on these facts, a position constraint graph expressed as a directed graph as shown in FIG. 2 is created.

In FIG. 2, 0.0.0 represents each trunk line 11a.

The vertices corresponding to 12a, 13a, and 14a, and ■ indicate the vertex corresponding to the obstacle 4. In the graph, ■- represents the relationship between the aforementioned obstacle 4 and trunk line 11a, and 0-■ represents the positional constraint relationship between trunk lines 12a and 14a, while vertex 0 represents a connected component that does not have such a constraint relationship. It is an independent component.

Next, weights and rankings are assigned to each of the vertices ① to 0 and ② based on such a positional constraint graph. The weight is "l" for each of the vertices ■ to 0, and the vertex ■ is the track 9a, 9b, 9c that overlaps the obstacle 4 in FIG.
The number “3” is used as a weight. The ranking is determined by starting from a vertex to which these arrows do not enter, and by the sum of the weights of the vertices included in the route from each starting point to each other vertex by following the arrow.

For example, the rank of vertex ■ is "4" which is the sum of the weight of vertex "3" and the weight of vertex "1", similarly, the rank of vertices 0 and 0 is "bi" respectively, and the rank of vertex ■ is "2". , and trunk lines corresponding to vertices with a large value indicating this rank are allocated with priority over other trunk lines.

Next, wiring is performed based on this order, and this wiring process will be explained according to the flowchart shown in FIG.

FIG. 3 is a flowchart showing the processing steps of the method of the present invention. First, create a position constraint graph that is a directed graph that expresses the trunk position constraints regarding the allocation position when allocating to tracks in a channel based on trunk information with trunks and obstacles as vertices, and upper and lower relationships with arrows. do(
Step St).

Next, when there is a trunk line whose allocatable tracks are restricted by the intra-channel obstacle 4, add a vertex representing the intra-channel obstacle and an arrow pointing from this vertex to the vertex representing the trunk line to the position constraint graph ( Step S2).

For each vertex in the position constraint graph, the weight of the vertex that requests a connection is all "1", and the weight of the vertex that represents an obstacle in the channel is the number of tracks that are constrained when allocating a trunk line due to the existence of that vertex. weight (step S3)
).

Next, in the positional constraint graph, a vertex without an arrow is taken as a starting point, and the rank of each vertex is determined as the cumulative weight of all vertices included in the path from this starting point to other vertices following the arrow. (Step S4).

In step S5), it is determined whether there is a trunk line that has not been allocated yet and can be allocated on the track.
If there is a main line, the main line with the highest rank is prioritized and allocated to a track as close to the cell row 2 side as possible, and the vertex corresponding to that main line is deleted from the position constraint graph (step S6).
).

Returning again to step S5, it is determined whether or not there is a main line, and if there is, the above-described process is repeated, and if there is not, the process ends.

FIG. 4 is a schematic diagram showing the result of wiring according to the above-described method, and the above-described process will be specifically explained based on this diagram. First, in the position constraint graph shown in FIG. 2, since the vertex with the largest numerical value indicating the rank is ■, the main line 11a corresponding to the vertex ■ is allocated to the track 9d closer to the cell row 2 side.

As a result, the main line 11a of the wiring 11 is formed between columns 10b to 10j on the track 9d, and the branch line 11b on the column 10b connects to the terminal 2a of the cell row 2, and the branch line 11c on the column 10j connects the terminal 2a of the cell row 1. It will be connected to terminal 1b of.

The vertex with the next highest rank is ■, but since the obstacle 4 has already been placed, the main line 12a corresponding to the vertex with the next highest rank is assigned to the track 9c closer to the cell row 2 side. As a result, the main line 12a is formed between columns 10j and 10k on the track 9c, and the main line 12a is
0. The upper branch line 12b is connected to the terminal 1a of the cell row l, and the upper branch line 12c of the column 10 is connected to the terminal 12g of the cell row.

Similarly, the main line 13a is connected to column 1 on track 9b.
It is formed between 0h and 11, and connects terminal 2b of cell row 2 at branch line 13b on column 10h, and also connects terminal 2b of cell row 2 to column 1o.
It is connected to the terminal 1d of the cell row 1 by a branch line 13c on Il.

Furthermore, the main line 14a is connected to columns 10k to 1 on the track 9a.
The upper branch line 1 is formed between 0+w and column 10.
4b is connected to the terminal IC of the cell row 1, and the branch line 14c on the column 10s is connected to the terminal 2d of the cell row 2, thereby reducing the occurrence of trunk lines that cannot be wired as shown in FIG. , the wire connection rate can be increased.

In addition, in the above-mentioned implementation, the connection relationship is represented by an arrow pointing from the top to the bottom in Figure 2, and the case where weights and rankings are assigned based on this has been explained. It may be represented by an upward arrow, and weights and rankings may be assigned based on this. In this case, trunk lines will be allocated from the cell column 1 side according to the order.

〔Effect of the invention〕

As described above, in the present invention, vertices corresponding to obstacles in the channel are set in the position constraint graph, weights are assigned to the vertices representing the obstacles and each main line, and the allocation order is determined based on this weight. Since we decided to perform the wiring by giving
Trunk lines subject to allocation restrictions can be allocated with priority over other trunk lines, making it possible to obtain a high connection rate even when an obstacle exists within the channel.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing cell rows and channels on a substrate to which the method of the present invention is applied, FIG. 2 is a graph showing the positional constraint relationship between main wiring lines, and FIG. Flowchart showing the wiring processing process, FIG. 4 is a schematic diagram showing the wiring mode according to the method of the present invention, FIG. 5 is a position constraint graph used in the conventional method, FIG. 6 is a flowchart showing the processing process of the conventional method, and FIG. The figure is a schematic diagram showing a wiring pattern according to a conventional method. l... Cell row 2... Cell row 3... Channel 4... Obstacle in channel 11.12.13.
14...Wiring 11a, 12a, 13a, 14a...
・Trunk lines 11b, 12b, 13b, 14b, llc, 12
c, 13c, 14c...” Branch lines In the diagram, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa 2nd
Figure □ Figure 3 Figure 5 Procedure amendment 118) 3. Representative of the person making the amendment Moriya Shiki 5, "Detailed Description of the Invention" column of the specification subject to amendment, Drawing 6, Contents of Amendment 6-1 (() of "Detailed Description of the Invention" of the specification) (Note) (In the 11th specification, page 5, line 12, "create as a directed graph" is corrected to "create as a directed graph.") (2) In the specification, page 6, line 17, "main line 11a 6-2 Figure 4 of the drawing is corrected as shown in the attached sheet. 7. List of attached documents

Claims (1)

[Claims] (1) In a channel wiring processing method in which terminals of cell rows arranged on a board are connected to tracks in a channel between cell rows using trunk lines allocated while avoiding obstacles in the channel, A positional constraint graph is created that expresses the constraint relationship between the positions of trunk lines, including the constraints imposed by the obstacles when allocating trunk lines to each track, and weights are set for each trunk line and obstacle based on the positional constraint graph. , a channel wiring processing method characterized in that an allocation priority order to the track is determined based on this weight, and wiring is performed based on this order.