JPH0496250A - Block shape determining method for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To make it possible to reduce an unavailable region where no wiring exists by including a block shape comparison process which carries out a cell line-reduction process again when the length of cell line is longer than the shape of blocks and carries out a truck number-reduction process again when the number of trucks is more than the shape of blocks. CONSTITUTION:Comparison is made between a predicted shape of a block and a required shape of an input block where decision is made as to whether the block shape be changed or not. When it is decided to change the block shape, a cell line is reduced, if it calls for reduction in its cell line. When the change calls for the reduction in the number of blocks, the number of trucks is reduced. When it is decided to change no block shape, a detailed wiring route is decided. More specifically, attempts are made to move cell lines vertically in conformity to the number of wiring trucks existing in a channel which is a wiring region clamped by cell spacing and decide the coordinates of a wiring which connects signal terminals, thereby forming a final wiring pattern and deciding the block shape.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for determining the block shape of a polycell type semiconductor integrated circuit.

(Prior Art) A polycell type semiconductor integrated circuit block has a plurality of rectangular cells having a logic function and generally having the same height arranged to form a cell row, and a plurality of cell rows are arranged. It is formed by providing wiring between the cell rows. The blocks thus formed are further combined with blocks having various functions to form a semiconductor integrated circuit having desired functions. that time,
The block shape is one of the important factors that influences the layout area of the entire semiconductor integrated circuit formed by combining blocks.

FIG. 4 is a layout diagram showing the arrangement results of each block, and in the same figure, 41.41... and 42.42
. . . each indicate a cell row, 43 and 44 each a block, and 45 an empty area where no wiring exists.

As shown in FIG. 4, cell row 41 in block 43
It is assumed that the length of the block 44 is different from the length of the cell row 42 in the block 44, and the cell row 41 is longer than the cell row 42. In this case, an empty area 45 is generated adjacent to the block 44 during boat fishing, and the overall layout area increases by the size of the empty area 45. Therefore, free space 4
Setting a block shape without 5 is an important means for reducing the layout area of the entire semiconductor integrated circuit.

FIG. 5 shows an algorithm showing a conventional block shape determination method, and in the same figure, 51. 52. 53.54,
55, 56, and 57 are processes, respectively, and FIG. 6 shows the layout of the block shape set by the conventional block shape determination method. In the same figure, 61 and 62 are cell rows, and 63 is the number of cell rows. 64 indicates a block in which the number of cell rows is 3, and 64 indicates a block in which the number of cell rows is 4.

Hereinafter, a conventional block shape determination method will be explained based on the flowchart shown in FIG.

First, in step 51, the desired shape of the block is input, and then in step 52, the expected number of cell rows that are expected to form the block shape input in step 51 is set.

Next, in process 53, the cells are distributed and arranged in each cell row so that the expected number of cell lines is obtained, and in process 54, the signal terminals of each cell are connected to each other based on the positional relationship of each arranged cell. Determine the approximate route of the wiring.

Next, in process 55, based on the approximate wiring route determined in process 54, the cell rows are moved up and down according to the number of wiring tracks existing in the channel, which is the wiring area between cell rows, and the signal terminals are moved up and down. Determine the coordinates of the wiring to connect and set the detailed wiring route. Therefore, in this process 55, the shape of the block is tentatively determined.

Next, in process 56, the block shape determined in process 55 and the desired block shape input in process 51 are compared, and it is determined whether the determined block shape is compatible or not, that is, the cell row of the determined block shape is determined. Determine whether the number should be changed.

If it is determined in process 56 that the number of cell lines should be changed, the number of cell lines is changed in process 57 so that it approaches the input shape. On the other hand, if it is determined in process 56 that the number of cell rows is not to be changed, the process ends.

To specifically explain the above block shape determination method, the expected number of cell rows set in process 52 is 3, and process 5
3. As a result of performing steps 54 and 55, a block 63 having a length as shown in FIG. 6(a) is formed, and step 56
As a result of comparison with the expected number of cell rows in step 5, if the length of the formed cell row 61 is longer than the expected number of cell rows, the number of cell rows is increased in step 57, and further in step 53.
Steps 54 and 55 are performed to form a block 64 having a cell row 62 shorter in length than the cell row 61 as shown in FIG. 6(b). Then, by repeating the above process, a block having a desired shape can be formed.

(Problems to be Solved by the Invention) However, with the above method, there is a problem that when the number of cell rows is changed, the length of the cell row changes significantly, and when the number of cell rows remains the same, the block There was a problem in that it was not possible to take detailed measures such as slightly shortening the width of the block, that is, the length of the cell row, or slightly lowering the height of the block.

In view of the above, the present invention changes the block shape to fit a preset shape by slightly changing the length of the cell row and the height of the block. The present invention provides a method for determining the block shape of a semiconductor integrated circuit that can reduce the amount of noise.

(Means for Solving the Problems) In order to achieve the above object, the present invention arranges a plurality of cells having logic functions to form cell rows, arranges the plurality of cell rows, and connects wiring between the cell rows. By applying
A method for determining a block shape of a semiconductor integrated circuit that forms a block having a desired shape is applicable, in which a through wiring that penetrates the cell row and connects the signal terminals of the cells is connected to a through area that connects the signal line inside the cell. a first penetration region,
When allocating the through wiring to a second through area prepared in advance for a through area inside the cell or a third through area provided between the cells, the through wiring is assigned to an unused second through area. a track number reduction step of reducing the number of tracks between the cell rows by allocating the number of tracks to the area or by newly providing a third penetration region between cells and allocating it to the third penetration region; If a plurality of potential penetration regions exist and the third penetration region is included in the plurality of penetration regions, the penetration wiring passing through the third penetration region may be connected to other potential penetration regions in the cell row. Changing the wiring route so that it passes through the penetration region and deleting the penetration region of the node 3, and if there are multiple penetration regions of equal potential included in one cell row and the wiring route is changed to pass through the penetration region. If the second penetration region is included, the wiring route is changed so that the penetration wiring that passes through the second penetration region passes through another penetration region in the cell row, and a cell row shortening step of shortening the length of the one cell row by allocating a through wiring of a different potential using the second through region to the second through region and deleting the third through region; If the length of the cell row shortened in the cell row shortening step is longer than the length of the cell row in a preset block shape, performing the cell row shortening step again;
If the number of tracks reduced in the track number reduction step is greater than the number of tracks of a preset block shape, the block shape comparison step includes a step of performing the track number reduction step again. be.

(Function) According to the block shape determination method for a semiconductor integrated circuit of the present invention, the length of the cell rows is shortened by the track number reduction step of reducing the number of tracks between cell rows and by eliminating the third penetration region. cell row shortening step, and if the length of the cell row shortened in the cell row shortening step is longer than a preset length, the length of the cell row is shortened in the step of repeating the cell row shortening step and the track number reducing step. If the number of tracks is greater than a preset number of tracks, the process includes a block shape comparison step of performing the track number reduction step again, so that the length of the cell row and the height of the block can be slightly changed. I can do it.

(Embodiment) FIG. 1 is a diagram showing an algorithm of a block shape determining method according to an embodiment of the present invention.
, 12, 13, 14, 15, 16° 17. 18, 19.
20 and 21 each indicate a process. In addition, FIG. 2 is a layout diagram of through wiring, and in the same figure, 21
is a cell row, 22 is a through wiring, 23 is a wiring between cell rows, 24
25 is a first penetration region, 25 is a second penetration region, 26 is a cell, 27 is a third penetration region, and 28 and 29 are signal terminals. Furthermore, FIG. 3 shows a layout diagram when the length of the cell row is changed by changing the number of through wirings. In the same figure, 21 is a cell row, 31 is a signal terminal, and 32 and 33 are Penetrating wirings 34 and 35 indicate inter-cell wirings, respectively.

Hereinafter, the procedure of the block shape determining method according to one embodiment of the present invention will be explained based on the flowchart of FIG.

First, as shown in FIG. 1, after inputting the desired shape of the block in step 11, in step 12 the number of cell rows expected to have the desired shape input in step 11 is set.

Next, in process 13, so that the set number of cell rows is reached,
Cells are distributed and arranged in each cell row, and in step 14, a rough route of wiring connecting signal terminals is determined from the positional relationship of the arranged cells.

Next, in process 15, the predicted shape of the block is determined by predicting the shape of the block from the number of wiring tracks between the cell rows and the length of the cell rows. Then, in step 16, the predicted shape of the block determined in step 15 is compared with the desired shape of the block input in step 11, and it is determined whether the shape of the block is to be changed.

Next, when it is determined in process 16 that the shape of the block is to be changed, if the change is to shorten the cell row, the cell row is shortened in process 17, and if the change is to decrease the number of tracks, process 18 is performed. Decrease the number of tracks. In either case, the process returns to step 15 to predict the block shape again.

Note that detailed procedures of process 17 and process] 8 will be described later.

On the other hand, if it is determined in process 16 that the shape of the block is not to be changed, detailed wiring routes are determined in process 19. In other words, the cell rows are moved up and down according to the number of wiring tracks existing in the channel, which is the wiring area sandwiched between the cell rows, the coordinates of the wires that connect signal terminals are determined, and the final wiring pattern is to determine the block shape.

Next, in process 20, the block shape determined in process 19 is compared with the desired shape input in process 11, and it is determined whether or not to significantly change the block shape, that is, change the number of cell rows. If it is determined in process 20 that the number of cell rows is to be changed, after changing the number of cell lines in process 21,
Returning to process 13 again, cells are distributed and arranged in each cell row so that the changed number of cell rows is achieved.

On the other hand, if it is determined in process 20 that the number of cell rows is not to be changed, the process ends.

Hereinafter, detailed procedures of the above-mentioned process 17 and process 18 will be explained based on FIGS. 2 and 3, and these processes are performed by optimizing the through wiring that penetrates the cell rows.

First, processing 17, that is, a method for shortening the length of cell rows by reducing the number of through wirings will be described.

The through wiring is provided to penetrate through the other cell row in order to connect the signal terminals of the cells in the cell rows when another cell row is interposed between the cell rows, Specifically, as shown in FIG. 2(a), the through wiring 22 penetrates the second cell row 21b and connects the signal terminal 28 of the first cell row 21a to the third cell row 21c.
It is used to connect the signal terminal 29 of the terminal.

Further, as the area where the through wiring 22 is arranged, three types of areas described below are usually adopted. That is, as shown in FIG. 2(b), the first penetration region 24 is provided inside the cell 26 and connected to the logic circuit of the cell 26, and the first penetration region 24 is provided inside the cell 26 in advance and is connected to the logic circuit of the cell 26. The second penetration region 25 which is not connected to the logic circuit and the cells 26 provided by widening the interval between the cells 26
There is also a third penetration region 27 that penetrates between the two.

However, when adopting the third penetration region 27, the cell 2
The length of the cell row 21 becomes longer because the distance between the cell rows 21 and 6 becomes wider.

Generally, the shape of a block can be changed by changing the wiring route and changing the number of through wirings. The layout diagram shown in FIG. 3(a) uses two through wirings 32 and 33, and the through wiring 33 adopts the second through area 25 or the third through area 27. shall be taken as a thing.

In this case, in process 17, if the through wiring 33 adopts the third through area 27, the inter-cell wiring 34 shown in FIG. 3(a) is replaced with the inter-cell wiring shown in FIG. By changing the route like the wiring 35, the through wiring 33 consisting of the third through area 27 is deleted.

Furthermore, if the through wiring 33 adopts the second through area 25, the third through area 27 used by the through wiring of another potential and the second through area 27 used by the through wiring 33 are The third through area 27 used by the through wiring 33 is deleted.

As a result of the above, the layout diagram shown in FIG. 3(b) is obtained, and the length of the cell rows can be shortened.

In addition, in process 18, by performing the process opposite to process 17, the wiring 35 shown in FIG.
Since the route is changed to the wiring 34 shown in FIG. 3A, the number of tracks of the inter-cell wiring 35 provided between the cell rows 21 is reduced.

As explained above, according to the embodiment, the cell row shortening step (process 17) and the track number reduction step (process 18)
and the block shape comparison step (processing 16), the length of the cell row and the height of the block can be slightly changed, and the shape of the block can be changed to match the set tough rock shape. can.

(Effects of the Invention) As explained above, according to the block shape determining method according to the present invention, the number of tracks is reduced by reducing the number of tracks between cell rows, and the length of the cell row is reduced by deleting the third through region. a cell row shortening step for shortening the length of the cell row, a step of re-performing the cell row shortening step if the length of the cell row shortened in the cell row shortening step is longer than a preset length, and the track number reducing step If the number of tracks reduced in step 1 is greater than the preset number of tracks, the block shape comparison step is performed again. can be changed to

Therefore, according to the present invention, the ineffective area without wiring can be reduced, and the layout area of a semiconductor integrated circuit can be reduced, so that the practical effects thereof are extremely large.

[Brief explanation of the drawing]

FIG. 1 is a flowchart of a block shape determining method according to an embodiment of the present invention, FIG. 2 is a layout diagram of through wiring when the above block determining method is applied, and FIG. 3 is a diagram showing a through wiring layout when the above block determining method is applied. FIG. 4 is a block layout diagram showing the conventional general arrangement state; FIG. 5 is a flowchart of the conventional professional block shape determination method; FIG. 6 is the conventional block shape diagram. FIG. 4 is a block layout diagram when the determination method is applied. 11.12.1B, 14, 16, 17, 18°19.2
0.21... Process 21... Cell row 22... Penetrating wiring 23... Wiring between cell rows (wiring) 24... First penetrating region 25... Second penetrating region 26... -Cell 27...Third penetration region 28.29.31...Signal terminal 32.33...Through wiring 34.35...Inter-cell wiring (wiring) 41.42...
・Cell row 43.44...Block 45...Invalid area 51.52, 53, 54, 55, 56.57...Processing 61.62...Cell row 63.64...Block (Q ) Payment (b) b (C) Figure 2 Figure 3 Figure 4 (b) Figure 6 Flood Figure 5

Claims (1)

[Claims] (1) A semiconductor integrated circuit in which a block having a desired shape is formed by arranging a plurality of cells having logical functions to form cell rows, arranging the plurality of cell rows and providing wiring between the cell rows. A method for determining a block shape, wherein a through wiring that penetrates the cell row and connects the signal terminals of the cells is placed in advance in a first through region having a signal line inside the cell as a through region, and inside the cell. When allocating the through wiring to the second through area prepared for the through area or the third through area provided between the cells, the through wiring is allocated to the unused second through area, or a track number reduction step of reducing the number of tracks between the cell rows by creating a new third penetration region between cells and allocating the third penetration region to the third penetration region; If there are a plurality of through regions and the third through region is included in the plurality of through regions, the through wiring that passes through the third through region passes through another through region in the cell row. changing the wiring route and deleting the third penetration region, and also if there are a plurality of equipotential penetration regions included in one cell row and the second penetration region is included in the plurality of penetration regions. If a through area is included, the wiring route is changed so that the through wiring that passes through the second through area passes through another through area in the cell row, and the third through area is used. a cell row shortening step of shortening the length of the one cell row by assigning a through wiring of a different potential to the second through region and deleting the third through region; If the length of the shortened cell row is longer than the length of the cell row in a preset block shape, the step of shortening the cell row is performed again, and the number of tracks reduced in the step of reducing the number of tracks is set in advance. 1. A block shape determining method for a semiconductor integrated circuit, comprising: a step of comparing block shapes, comprising a step of performing the track number reducing step again if the number of tracks is greater than the number of tracks of the block shape.