KR100385862B1 - Method of improving routing delay for symmetrical FPGA - Google Patents

Abstract

The present invention relates to a technique for improving signal delay of field programmable semiconductor arrays (FPGAs) having a symmetric circuit structure.

According to the present invention, there is provided a method for improving wiring delay in a field-processing semiconductor, comprising: a first step of dividing a wiring form between logical blocks into subnet units of a double pin net, and sequentially determining whether to integrate the subnets; Step 2, adjusting the track position of the two subnets so that the mergeable subnets have the same track value, and adjusting the track position of the remaining subnets.

Further, according to the present invention, there is provided a recording medium having recorded thereon a program for realizing the above-described method for improving the wiring delay of the field processing semiconductor.

Description

How to fabricate field-processed semiconductors {Method of improving routing delay for symmetrical FPGA}

The present invention relates to a technique for improving signal delay of a field programmable semiconductor array (FPGA) having a symmetrical circuit structure. More specifically, the present invention relates to a technique for minimizing the number of switching elements in a wiring path constituting each net. It is about.

In the field-processed semiconductor, the wiring path connecting pins to pins is composed of a plurality of metal wires and switch elements. Such field-processed semiconductor circuits have many signal lines, of which signal lines connecting pins having the same potential are called "nets". A net connecting more than two pins is called a "multi pin net", and a net connecting two pins is called a "double pin net".

1 is a diagram showing a typical wiring structure of a symmetrical field processed semiconductor. The logic blocks 1 are denoted by L and arranged at regular intervals in the horizontal and vertical directions of the chip, and pins 11 are drawn to each logical block 1. In the figure, a field-processed semiconductor is shown in which four logic blocks are arranged. The connection block 2 is an area between the logic blocks 1. The switch block 3 means the area between the connection blocks 2. Wiring tracks 4, 5, 6, 7, 8, and 9 are derived from the connecting blocks 2 in the horizontal and vertical directions. The number of logic blocks 1, the number of pins 11, and the number of wiring tracks 4, 5, 6, 7, 8, and 9 are adjusted according to the capacity of the chip.

In the connection block 2, the switch element 12 exists at the position where the pin 11 and the wiring track of the logic block meet. For example, the switch element 12 exists at the position where the wiring track 7 and the pin 11 of the logic block meet. This switch element 12 can be implemented using the MOS transistor 13.

In the switch block 3, the intersection of the wiring tracks of the connection block 2 in the diagonal direction is called the switching point 10. When an electrical signal is generated at the pin 11 of the logic block 1, it is transmitted to another switch block in the chip through the switch element 12 of the adjacent connection block. The switch block transmits a signal to a desired position by controlling the direction in which the signal flows using each switch of the switch point. In the case of commercial field processing semiconductors, the switching point 10 is composed of six switch elements 14, 15, 16, 17, 18, and 19.

A general design flow diagram for a symmetric field processed semiconductor configured as described above is shown in FIG. First, connection information of an electronic circuit is mapped to a logic element in a field-processed semiconductor (S1), and the logic element is placed in a logic block (S2). At this time, the number of logic blocks and the total wiring length are minimized. Next, the logic blocks on which the logic elements are arranged are connected using a switch element and a metal wire (S3). When wired in this way, a bit-stream is generated (S4), and an on-site semiconductor chip is programmed (S5).

The conventional wiring technique for the above-described wiring step S3 can be largely divided into two types. The first is to divide each net into several double pin nets and then wire them in units of double pin nets. In this case, the maze routing is effective, and at every moment, a near optimal wiring path can be found. However, there is a disadvantage in that it is difficult to achieve optimal wiring in the entire wiring surface. In particular, since the wiring of the double pin net uses a switch whenever necessary, excessive switching devices are frequently required. Therefore, there is a problem that a significant signal delay occurs.

The second method is to wire each net in units. Wiring is performed so that each net is connected to a steiner tree. This wiring improves the wiring length and the number of switches. However, when wiring hundreds or thousands of nets, it is difficult to optimize the entire wiring surface due to the interaction effect.

A conventional typical wiring technique will be described with reference to FIG. As wiring resources for field-processed semiconductors are limited, a particular consideration in wiring is to use the minimum wiring track. In order to do this, the routing device usually assigns nets to empty wiring tracks from the bottom or left of the wiring tracks.

In the example of FIG. 3, four nets a, b, c, d are configured. Among them, a, b and c are double pin nets, and d is a multi pin net and connects three pins. If the net number of pins connected is prioritized, the order a, b, c, d is obtained. Nets a and b are each on the first track and net c is on the second track. Since the net d may be divided into two subnets and wired, two switch elements 23 and 24 are required in the connection block 22 to connect the connection blocks 20, 21 and 22.

In symmetric field processing semiconductors, the location of the subnet is in the connection block. Using this property, if the wiring arrangement of FIG. 3 is changed as shown in FIG. 4, two subnets of the net d are connected by the switch element 25, thereby reducing one switch element.

It is an object of the present invention to provide a method of optimizing signal delay of field processed semiconductors by minimizing the number of switch elements by removing unnecessary ones from switch elements present in the connection block.

1 is an internal structure diagram of a general field processing type semiconductor,

2 is a flowchart illustrating a design process of an on-site semiconductor according to the prior art;

3 is a wiring arrangement diagram designed by the prior art;

FIG. 4 is a wiring arrangement diagram designed according to the present invention in which the wiring arrangement shown in FIG. 3 is improved;

5 is a flowchart illustrating a design process of an on-site semiconductor according to the present invention;

6 is a flowchart illustrating in detail a signal delay optimization step shown in FIG. 5;

FIG. 7 is a detailed flowchart illustrating a switch optimization step for the net shown in FIG. 6;

8 is an exemplary diagram of a wiring arrangement designed according to the prior art;

9 is a graph for optimizing the wiring arrangement shown in FIG. 8;

10 is a view showing a state in which the wiring arrangement shown in FIG. 8 is designed and optimized by the present invention.

According to the present invention for solving the above technical problem, there is provided a method for optimizing the signal delay of the field-processed semiconductor. First, in the field processing type semiconductor, logic elements constituting a semiconductor circuit are arranged at regular intervals on a plane, and a predetermined number of wiring tracks exist in the horizontal and vertical directions between the logic elements, and the wiring tracks and the logic pins There is a switch element at this location.

The method for manufacturing an in-situ semiconductor includes a technology mapping step of mapping connection information of the semiconductor circuit to the logic device, and disposing the logic device in the logic block such that the number of logic blocks and the total wiring length are minimized. Arrangement step, wiring step of connecting the logic blocks between the switch element and the metal wire, if the signal delay of the semiconductor circuit manufactured by the steps to measure the signal delay to be improved, redistribution so as to minimize the number of switch elements A wiring delay improvement step and a programming step of generating and programming a bit string of the semiconductor circuit having optimized signal delay.

The wire delay improving step may include: a first step of dividing a wiring form between the logic blocks into subnet units of a double pin net; a second step of sequentially determining whether the subnets are integrated; A third step of adjusting the track position of the two subnets so that the nets have the same track value, and a fourth step of readjusting the track position of the remaining subnets.

Preferably, the method for improving the wiring delay of the field processing type semiconductor is a post-processing wiring method of reducing the switch element after wiring.

In addition, according to the present invention, a first step of reading wiring information of a wiring track of a semiconductor circuit and modeling it in a net unit in a computer, and the subnets and switch elements constituting the net are represented by nodes and edges, respectively. A second step of forming a graph, a third step of determining whether two subnets connected across any edge where two switch elements are located can be integrated; and if the two subnets can be integrated, the two subnets are merged and one A fourth step of removing the switch elements of the second step, a fifth step of repeatedly performing the third to fourth steps for all edges, and a sixth step of repeatedly performing the second to fifth steps for all nets A computer readable recording medium having recorded thereon a program is provided.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the wiring delay improvement method of the field-processing semiconductor according to the present invention.

5 is a design flow chart of an on-site semiconductor according to the present invention. The step S1, the arrangement step S2, the wiring step S3, the bit string generation step S4, and the step S5 of programming the field-processed semiconductor chip are the same as in the prior art.

However, in the present invention, after the wiring step S3, the step of measuring the signal delay of the circuit with respect to the result (S6) and the case where the signal delay does not reach the specification or to further improve the signal delay is performed. The wiring delay improving step, that is, the signal delay optimization step S7 is further included.

A detailed flowchart of the signal delay optimization step S7 is shown in FIG. 6.

First, all the net information is read in step S100, and then the counter j is initialized. Then, switch optimization for the j-th net is performed in step S101. In steps S102 and S103, it is determined whether or not the processing for all nets is completed so that one optimization process is performed for each net.

A detailed flowchart of the optimization performing step S101 is shown in FIG.

Step S200 is a process of initializing the number of pins K, the counter i, and the graph to '0', and step S201 sets a graph having K-1 nodes and sets the graph to 'K'. This step is to assign a value of 'K-1'. At this time, each node of the graph represents one subnet. In step S202, the positions of the switch elements required to connect each subnet, that is, each node constituting the graph, are determined. According to the information, the edge is formed in accordance with the position of the switch element in step S203. Here, the edge refers to one or more switch elements existing between the subnets. When forming the graph by steps S201, S202, and S203, adjacent subnets with the same track value constitute one supernode from the beginning.

In step S204, the number of connected edges is selected one from each node constituting the graph, and the counter i is increased by one. In step S205, it is determined whether any of the nodes connected to the selected node can be integrated. If possible, the process proceeds to step S206, in which the two nodes, that is, the two subnets, are integrated and the graph is modified. If there is nothing integrated in step S205, the flow advances to step S207 to cancel the selection and select another node. In step S208, it is determined whether all nodes have been checked for integration. If the inspection is completed, the step (S209) of outputting the final graph is performed.

A net with K nodes has K-1 subnets (double pin nets), each subnet having its own track value by the wiring harness. The track value is defined as a natural number assigned to each track, going from bottom to top or left to right in each horizontal and vertical channel. Taking the wiring diagram of FIG. 3 as an example, the nets a and b have a track value 1, and the net c has a track value 2. In net d, two subnets have track values 1 and 2, respectively. Switch elements are added when subnets belonging to the same net have different track values. That is, the net d requires four switch elements because the two subnets have different track values, but only three switch elements are required if the wiring is wired to have the same track value as shown in FIG. Therefore, as a post-processing technique, the subnets belonging to the same net are rearranged to have the same track value.

An embodiment of the present invention will be described with reference to the flowchart of FIG. 7 and FIGS. 8 to 10.

FIG. 8 is a wiring diagram of one net connecting five pins and includes four subnets s1, s2, s3, and s4. That is, the number K of nodes is 5 and in this case, three switch elements are additionally arranged. Subnets can be wired independently, which is a very important factor in increasing the wiring rate. Therefore, in the conventional wiring, the switch element is frequently used as shown in FIG. 8.

When the wiring is completed using the subnets as described above, the excessively used switch element is removed by performing the method for improving the wiring delay of the field processed semiconductor according to the present invention.

In the case of an on-site semiconductor having five nodes, the number of subnets s1, s2, s3, and s4 is "K-1 = 4", and the graph obtained in step S201 is shown in Table 1 below.

s1 s2 s3 s4 s1 s2 s3 s4

Step S202 determines the position of the switch element connecting between each subnet, where a switch element is needed to connect between s1 and s2, s2 and s3, s2 and s4, s3 and s4. If this is displayed on the graph of Table 1, it is as Table 2, and it is as shown in FIG. In FIG. 9, the number beside the node representing the subnet means a track value.

s1 s2 s3 s4 s1 One s2 One One One s3 One One s4 One One

As can be seen from the graph of Table 2, the subnet having the smallest number of edges among the subnets is s1. Therefore, step S204 selects s1 as the least cost subnet, where i = 1. Step S205 determines whether s1 selected in step S204 can integrate with an adjacent s2. If it is possible to move s1 to the track of s2 or s2 to the track of s1, then the condition of integration is satisfied. If it is possible to move s1 to the position of s2, the graph is modified as shown in Table 3 in step S206. At this time, K = 3 and i = 0. Determine if the s1 and the other three subnets can be integrated.

s1 / s2 s3 s4 s1 / s2 One One s3 One One s4 One One

As a result of the determination in step S208, since i <K, the flow advances to step S204 to determine whether or not the current nodes s1 / s2, s3, and s4 are integrated. For example, assuming that s4 can be integrated into s1 / s2, i = 1 by step S204, but K = 2 and i = 0 by step S205 and S206. At this time, in step S206 the graph is modified as shown in Table 4.

s1 / s2 / s4 s3 s1 / s2 / s4 One s3 One

Since i <k in step S208, step S204 is performed. Step S204 determines whether node s3 can be integrated with node s1 / s2 / s4, and assuming that it can be integrated, the graph leaves only one supernode.

At this time, i = 1 at step S204, but K = 1 and i = 0 at step S205 and S206. Therefore, step S204 is performed again because i <k in step S208. In step S204, since i = 1 is determined as a single node that cannot be integrated in step S205, the process proceeds to step S207, and in step S208, i = K, so step S209 is reached.

If all the subnets of the net are integrated into one supernode s1 / s2 / s4 / s3 as in this embodiment, the wiring is improved as shown in FIG. 10 and can save a total of three switch elements. By performing the step S101 of minimizing the switch elements for the respective nets, there is an effect of significantly reducing the wiring delay.

Since the present invention processes one net at a time, the degree of improvement may vary depending on the wiring order, such as a margin in the wiring area as the net to be wired first. Therefore, if proper results are not obtained by one action, the net order is readjusted and steps S101, S102, and S103 are repeated.

According to the present invention as described above, it is possible to improve the operation performance of the circuit by removing unnecessary switch elements that may be present in the wiring. The present invention has an effect that can be applied to all existing wiring for the symmetric field processing semiconductor.

Claims (3)

Logic elements constituting a semiconductor circuit are arranged at regular intervals on a plane, and a predetermined number of wiring tracks exist in the horizontal and vertical directions between the logic elements. In the method of manufacturing the existing field-processing semiconductor, A technology mapping step of mapping connection information of the semiconductor circuits to the logic device, an arrangement step of disposing the logic device in a logic block such that the number of logic blocks, total wiring length, etc. are minimized, and switching elements between the logic blocks And a wiring step of connecting using a metal wire, and a wiring delay improving step of rewiring so that the number of switch elements is minimized when the signal delay of the semiconductor circuit manufactured by the above steps is measured and the signal delay is improved. A programming step of generating and programming a bit string of the optimized semiconductor circuit, The wiring delay improving step may include: a first step of separating a net connecting the logic blocks wired in the wiring step into sub-units of a double pin net; A second step of allocating tracks and assigning track values to respective subnets constituting the respective nets; A third step of forming a graph in which each subnet and both ends of the subnet are represented by nodes and edges, respectively; A fourth step of judging whether two subnets connected at both ends of an arbitrary edge where two switch elements are located can be connected by one track, and determining whether the two subnets are integrated together; A fifth step of integrating the two subnets, removing one switch element from the edge, and reconstructing the graph according to the integration result by adjusting the track position of the subnets that can be integrated in the fourth step and assigning one track value; , And And a sixth step of performing the fourth and fifth steps for all the edges and subnets. The method of claim 1, wherein the method for improving the wiring delay of the field processing semiconductor is a post-processing wiring method for reducing the switch element after wiring. Logic elements constituting a semiconductor circuit are arranged at regular intervals on a plane, and a predetermined number of wiring tracks exist in the horizontal and vertical directions between the logic elements. In order to minimize the number of the switch element in the process of manufacturing the existing field-processed semiconductor, On your computer, A first step of reading wiring information of a wiring track of a semiconductor circuit and modeling it in a net unit; A second step of forming a graph in which the subnets constituting the net and both ends of the subnet are represented by nodes and edges, respectively; A third step of determining whether two subnets connected at both ends of an arbitrary edge where two switch elements are located can be connected to one track, and determining whether the two subnets are integrated; A fourth step of reconstructing the graph according to the integration result by adjusting the track position of the subnets that can be integrated in the third step, assigning one track value, integrating the two subnets, and removing one switch element from the edge; , A fifth step of repeating the third and fourth steps for all edges, and A computer-readable recording medium having recorded thereon a program comprising a sixth step of repeating the second to fifth steps for all nets.