JPH03162110A - Bias circuit for field effect transistor - Google Patents

Abstract

PURPOSE:To prevent the excess of a drain current and to improve the efficiency of an FET by adjusting a variable resistor connected to the base of a transistor and setting the emitter output voltage of an emitter follower consisting of this transistor. CONSTITUTION:To the gate of a field effect transistor(FET) 1, a transistor 2 brought to emitter follower connection is connected. That is, the transistor 2 is constituted so that a variable resistor 3 is connected between the base and a bias supply power source 4, and a voltage supplied to the base can be brought to variation control. Accordingly, by adjusting the variable resistor 3 and setting an emitter output voltage in advance, a state that a roughly constant voltage is applied to the gate of the FET 1 can be held. In such a way, the increase of a drain current is prevented, and the efficiency of the FET 1 can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bias circuit for field effect transistors (FETs) used in communication devices and the like.

[Conventional technology]

Conventionally, as this type of FET bias circuit, one that controls changes in gate bias voltage using a variable resistor has been used. For example, FIG. 2 is an example. In the figure, 1 is a FET, and the gate of this FETI is connected to a bias supply power source 4 via a large current prevention resistor 6 and a protection resistor 7. Further, a variable resistor 3 for bias setting and a gate zero voltage prevention resistor 8 are connected to the bias supply power source 4. The movable contact of the variable resistor 3 is connected to the connection point of the resistor 6.7.

In this structure, by adjusting the movable contact of the variable resistor 3, a voltage obtained by dividing the gate voltage -Vg applied from the movable contact to the gate supply power source 4 is obtained, and this divided voltage is used as the gate voltage. It can be supplied to the gate of FET1 as a signal.

[Problem to be solved by the invention]

In the conventional bias circuit described above, the setting of the bias point is achieved by voltage division using the variable resistor 3, so the FETI
A resistor is connected in cascade to the gate side of the circuit. Therefore, if the gate breakdown voltage of FET1 is low and a leakage current flows through the gate due to breakdown, if that current becomes relatively large, the leakage current and the resistor connected in cascade to the gate will cause a voltage increase. A descent occurs. As a result, as shown in FIG. 3, the gate bias voltage VGS moves from the initial set value A to the set value B, and as a result, the drain current increases. Flows excessively, and as shown by the broken line in FIG. 4, unnecessary power is consumed in the FET, resulting in a problem of decreased efficiency. The purpose of the present invention is to prevent excessive drain current due to read current and improve FET efficiency.
An object of the present invention is to provide a T bias circuit.

[Means for Solving the Problems] A bias circuit of the present invention includes a transistor connected as an emitter follower to the gate of an FET, a variable resistor for bias setting connected between the base of this transistor and a bias supply power source, and A current limiting emitter resistor is connected between the emitter of the transistor and the bias supply power source.

[Effect]

In this structure, by adjusting the variable resistor connected to the base of the transistor to set the emitter output voltage of the emitter follower made of the transistor, even if leakage current occurs at the gate of the FET, the gate voltage of the FET can be adjusted. is kept approximately constant to prevent excessive drain current.

In addition, the increase in gate current is prevented by the engineered resistance,
Prevent gate bias from becoming unstable.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of one embodiment of the present invention, particularly showing only the gate bias circuit. In the figure, 1 is a FET, and a transistor (bibolar transistor) 2 is connected to the gate of this FETI as an emitter follower.
are connected.

That is, the transistor 2 has a base and a bias supply power source 4.
A variable resistor 3 is connected between the base and the base so that the voltage supplied to the base can be varied and controlled. Further, the collector of transistor 2 is grounded, and the emitter is connected to the FET 1.
connected to the gate. Further, an emitter resistor 5 for current limiting is connected between this capacitor and the bias supply power source 4.

According to this precept, if the emitter output voltage is set by adjusting the variable resistor 3, the emitter of the transistor 2,
That is, since the resistance on the output side is low, even if a leakage current of a certain value or more flows from the gate of the FETI connected to the emitter, the output voltage of the emitter will not change. Therefore, it is possible to maintain a state in which a substantially constant voltage is applied to the gate of the FET 1, thereby making it possible to prevent an increase in drain current and improve the efficiency of the FETI.

Note that when the gate current exceeds a certain value, the emitter follower will no longer supply current and the function of maintaining the gate bias at a constant voltage may be lost. If the current flowing through the emitter resistor 5 inserted between the emitter resistor 5 and the output voltage of the transistor 2 is determined, the leakage current from the gate of the FETI can be limited to within a certain value. It is possible. [Effects of the Invention] As explained above, in the present invention, a transistor is connected as an emitter follower to the gate of the FET, and a variable resistor for bias setting is connected between the base of this transistor and the bias supply power source. By adjusting the variable resistor to set the emitter output voltage, even if leakage current occurs at the gate of the FET, the gate voltage of the FET can be kept approximately constant and excessive drain current can be prevented. .

In addition, since a current limiting resistor is connected between the emitter of the transistor and the bias supply power supply, if the current flowing there is determined by the emitter output voltage and the emitter resistor, leakage at the gate of the FET can be avoided. The current can be limited to a certain value or less, and it is also possible to prevent gate bias from becoming unstable when the gate current increases beyond a predetermined certain value.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the bias circuit of the present invention, Fig. 2 is a circuit diagram of a conventional bias circuit, Fig. 3 is a characteristic diagram of FET gate voltage vs. drain current, and Fig. 4 is a circuit diagram of a conventional bias circuit. FIG. 3 is a characteristic diagram of human power car output power and drain current. 1...FET, 2...Transistor (emitter follower). 3... Variable resistor, 4... Bias supply power supply, 5... Emitter resistor, 6... Large current prevention resistor, 7
...Protective resistor, 8...Gate zero voltage prevention resistor. Figure 1 Figure 2

Claims (1)

[Claims] 1. A transistor connected as an emitter follower to the gate of the field effect transistor, a variable resistor for bias setting connected between the base of this transistor and the bias supply power supply, and a variable resistor connected between the emitter of the transistor and the bias supply power supply. 1. A bias circuit for a field effect transistor, comprising a connected emitter resistor for current limiting.