JP3113951B2 - GaAs FET protection power supply circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a GaAs FET (Gallium Arsenide Field Effect Transistor) protection power supply circuit,
In particular, the present invention relates to a GaAsFET protection power supply circuit provided with a function of protecting an ultrahigh-frequency GaAs FET in a wireless communication device using an ultra-high frequency from being destroyed by an overcurrent.

[0002]

2. Description of the Related Art When an ultra-high frequency GaAs FET is used, if the bias application order of the gate, source, and drain electrodes is incorrect, it may be destroyed.

For example, when a bias is used with a common grounded drain type, when power is turned on, a control voltage must first be applied to the gate, and then applied to the drain.

In this case, if the power supply is not turned off in the order of turning off the drain voltage and then turning off the gate voltage, an excessive current flows through the drain and GaAs
There is a possibility that the FET may be destroyed.

Conventionally, a circuit has been used in which a gate and drain bias supply circuit has a time constant to delay the rise of the drain voltage when power is turned on.

[0006]

SUMMARY OF THE INVENTION Ultra-high frequency GaAsFE
In the conventional power supply circuit for T, the drain or source bias power supply has a time constant and the rise of the drain or source bias voltage is delayed more than the rise of the gate bias voltage. Due to the influence of the time constant existing in the circuit, the drain or source bias voltage cannot be completely reduced to 0 V even though the gate bias voltage is 0 V, and the drain or source current flows, and in the worst case, the GaAs FET is destroyed. There was a point.

[0007] An object of the present invention is to solve the above-mentioned problem, and the order of the fall of the drain bias voltage and the gate bias voltage when the power is turned off is always such that the drain voltage is turned off and then the gate voltage is turned off. An object of the present invention is to provide a GaAsFET protection power supply circuit in which a GaAsFET is prevented from being destroyed due to an excessive current flowing in the applied state.

[0008]

SUMMARY OF THE INVENTION The GaAs FET of the present invention
The protection power supply circuit is divided into two branches by inputting either one of the positive and negative DC power supplies, one of which is connected to the GaAs FET through the integration circuit.
And the other is output as a drain or source bias voltage of the GaAs FET through a transistor switch circuit controlled by the output of the integration circuit. When the DC power is turned on, the gate bias voltage is output. A configuration is provided in which the GaAs FET is protected by raising the voltage earlier than the voltage for the drain or source bias and dropping the voltage for the drain or source bias earlier than the voltage for the gate bias when the DC power supply is cut off. Have.

The GaAs FET protection power supply circuit of the present invention has a configuration in which two positive and negative DC power supplies are input.

[0010]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram (A) and an output voltage characteristic diagram (B) of a first embodiment of the present invention.

FIG. 1 shows a case where a GaAs FET is used in a grounded drain system and a case where a negative potential is applied to a source and a negative potential is also applied to a gate as a bias voltage.

Referring to FIG. 1B, the minus power source -Vcc is divided into two, one of which is provided with an appropriate time constant by an integrating circuit composed of R1 and C1 so that the gate bias is reduced. Voltage VG characteristic 1 is obtained, and when the voltage at the point a is reached, the transistor switch Q formed in the other source system is turned on, and the source bias voltage V
Generate s.

When the power is turned off, R1, C in FIG.
When the output voltage of the integrating circuit consisting of 1 reaches the point b, the transistor switch Q is turned off and the source bias voltage Vs
Rapidly drops to 0V.

On the other hand, the gate bias voltage VG is R
1, the voltage gradually decreases with the time constant of C1, and a time difference is generated between the voltage and the source bias voltage Vs.

This time difference can be set to a desired time by selecting R1 and C1 of the integrating circuit and the bias resistors R3 and R4 of the transistor switch Q.

FIG. 2 is a circuit diagram (A) and an output voltage characteristic diagram (B) of a second embodiment of the present invention.

The circuit shown in FIG. 2A is a GaAs FET protection power supply circuit which can be used in a source grounded system. In this embodiment, the control of the drain bias voltage VD is performed by the same switching transistor Q as in FIG. Perform in.

The voltage at point c shown in FIG. 2 is determined by appropriately selecting the Zener voltage of the Zener diode CR.

An integrating circuit composed of a resistor R9 and a capacitor C3 provides a predetermined time constant as in the case of R1 and C1 in FIG. A resistor R5 is used for current limiting, a resistor R6 is used for setting a bias point of the switching transistor Q, a resistor R7 is used for setting a bias point of the Zener diode CR, and a capacitor C2 adjusts a rise time of a drain bias VD. Is used for the purpose of accelerating the fall of the drain voltage VD.

As shown in FIG. 2 (B), the gate bias voltage VG drops gradually, while the drain bias voltage VD drops sharply, and a desired time difference can be secured between the two voltages. It has become something.

[0022]

As described above, according to the present invention, when an ultra-high-frequency GaAs FET is operated, the source or drain bias voltage is controlled to rise when a certain gate bias voltage is reached, and the gate bias voltage is controlled. By controlling the drain voltage and the source bias voltage not to be applied unless the voltage is applied to the gate of the GaAs FET, an excessive current due to the application of only the drain bias voltage and the source bias voltage is suppressed, and the GaAs FET is destroyed. There is an effect that can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram (A) and an output voltage characteristic diagram (B) of a first embodiment of the present invention.

FIG. 2 is a circuit diagram (A) and an output voltage characteristic diagram (B) of a second embodiment of the present invention.

[Explanation of symbols]

 1 Gate bias voltage VG characteristic 2 Source bias voltage Vs characteristic 3 Drain bias voltage VD characteristic 4 Gate bias voltage VG characteristic C1 to C3 Capacitor CR Zener diode Q Switching transistor R1 to R9 Resistance

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 17/00-17/70

Claims (2)

(57) [Claims] In a GaAs FET protection power supply circuit,
A positive or negative DC power supply, an integration circuit that integrates an output voltage of the DC power supply to generate a gate bias voltage of the GaAs FET, and turns on when an output voltage of the integration circuit is equal to or higher than an output voltage of the DC power supply. The voltage is adjusted to the GaAs
output to the source bias of the sFET, and turn off when the output voltage of the integration circuit is equal to or less than a fixed value, and the GaAs FET is turned off.
A transistor switch circuit for preventing supply of an output voltage to a source bias of the GaAs.
sFET protection power supply circuit. 2. In a GaAs FET protection power supply circuit,
Two positive and negative DC power supplies, an integration circuit for integrating the output voltage of the negative DC power supply to generate a gate bias voltage for the GaAs FET, and the negative DC voltage after a lapse of a predetermined time from the rise of the negative DC voltage Output the first
A delay circuit, a second delay circuit that blocks the output of the negative DC voltage after a lapse of a predetermined time from the fall of the negative DC voltage, and a second power supply of the DC power supply that is turned on by the output of the first delay circuit. The output voltage is output to the source bias of the GaAs FET, and the output of the second delay circuit
a GaAs FET protection power supply circuit, comprising: a transistor switch circuit for blocking supply of an output voltage to the source bias of the GaAs FET.