JPH0316182A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make a film thickness of a gate oxide film uniform and to enhance a write characteristic by a method wherein a floating gate which has been formed collectively on a channel region and on a control gate via a substrate and via an insulating film is formed and the floating gate is formed so as to stride the control gate in a gate-width direction. CONSTITUTION:In a one-layer gate ultraviolet-light erasable type ROM, the following are provided: a source 4 of an opposite conductivity type and a drain 5 of the opposite conductivity type which have been formed on a semiconductor substrate 1 of one conductivity type by being separated from a channel region; a control gate electrode 3 of the opposite conductivity type which has been formed on the substrate 1 by being separated from the channel region; a floating gate 2 which has been formed collectively on the channel region and on the control gate 3 via the substrate 1 and via an insulating film 6. The floating gate 2 is formed so as to stride the control gate 3 in a gate-width direction. Thereby, a film thickness of a gate oxide film is formed so as to be equal on the control gate and on the channel region; a write characteristic can be enhanced.

Description

[Detailed Description of the Invention] [Table of Contents] Industrial Application Fields Prior Art Problems to be Solved by the Invention Means for Solving the Problems Action Principle Diagram of the Present Invention (1) Principle Diagram of the Present Invention (1) (Fig. 1) (Fig. 2) Principle diagram of the present invention (6) (Fig. 11) Example Embodiment of the present invention (2) (Fig. 3. Fig. 4 The present invention (
Example of 3) (Figure 5 Example of present invention (4)) (Figure 6 Example of present invention (5)
(Fig. 7 Example of the present invention (6) (No. 1)
Figures 2 and 13 [Summary] Regarding the single-gate ultraviolet erasable ROM (EFROM) used as redundant cells in mask ROMs and its manufacturing method, the alignment margin is increased and the cell area is reduced. It is formed in the same process as the mask ROM, with the aim of making the gate oxide film uniform in thickness and improving the write characteristics. and a drain of the opposite conductivity type,
a control gate electrode of an opposite conductivity type formed on the substrate apart from the channel region; A floating gate is formed integrally over the channel region and the control gate through the substrate and an insulating film, and the floating gate is formed to straddle the control gate in the gate width direction. (2) The gate length of the floating gate is formed larger on the control gate than on the channel region. (3) When making the mask ROM as a redundant cell, the control gate is formed and the peripheral circuit FE
This process involves forming the T gate, word line, and floating gate at the same time. (4) When fabricating a mask ROM as a redundant cell, a control gate is formed at the same time as bit lines are formed. (5) A gate oxide film is formed, and then a conductive film is formed on the entire surface of the substrate. A resist is deposited on the conductive film, and an opening is opened in the resist in the area where the control gate is to be formed. (6) forming the control gate by introducing impurities through the opening using the resist as a mask;
) The control gate is connected in parallel to a conductive film formed on the substrate via an insulating film.

[Industrial Application Field] The present invention is a one-layer gate ultraviolet erasable ROM (EFROM).
), its manufacturing method, and a manufacturing method of a mask ROM having a single-layer gate EFROM.

A single-layer gate EFROM has a structure in which a control gate is provided on the substrate and a floating gate of a non-volatile memory section is formed using the first layer of conductive film, and it has come to be used as a redundant cell in a mask ROM.

In recent years, as the capacity of mask ROMs has increased, the chip collection rate has become worse. For this reason, one possible method is to use redundant cells, which are often used in RAM, to replace the defective cells. In the case of a mask ROM, such a method cannot be adopted because the data held by the cells is fixed. For this reason, single-layer gate EFR, which is a non-volatile memory device,
Redundancy using OM can be considered.

In this specification, the following items (1) to (6) will be explained in correspondence with claims (1) to (6).

[Prior Art] (1) A conventional single-layer gate EFROM has a layout as shown in FIG.

Figure 8 (1). (2) is a plan view and a ^-^ sectional view showing the layout of a conventional single-layer gate EPROM corresponding to the present invention (1).

In the figure, ■ is a substrate, 2 is a non-volatile memory unit and a floating gate (floating gate), 3 is a control gate (abbreviated as control gate cG, here the base side), 4 is a source. 5 is a drain, 6 is an insulating film, 7 is a wiring, and the area between the source and drain is a channel region.

Each symbol shown in the figure is as follows.

Lvr. : FG gate length Wrc : FG gate width Lca : CG gate length. a: Gate width of cG d+: Thickness of gate oxide film of FG d2: Thickness of field oxide film d=: Thickness of gate oxide film of cG Wcy: Distance between channel region and CG or. Each arrow indicates the X and Y directions, respectively.

now. In single-layer gate EFROM, VFG: F
Voltage of G Vcc: If the voltage of CG. These voltages are determined by the capacitance ratio of each part of the FG and Vra.
= Vcc/ ((da/dt) (LFGWFG/
LCGWCG)+1+(dz/dz)(LcrW
cy/LccWcG)) , ・ ・ ・(1) The relationship is established.

Here, since d:l << dz, vycξVCG/ (1 + (d3/d+) (LFcWya/LccWcc)
] ・ ・ ・(2) Here, if VFG can be increased, the threshold voltage V
The width of the amount of change ΔVth can be made thicker. Writing characteristics can be improved.

To improve the writing characteristics by increasing the VFG thickness, the VFG
# Ideally, it would be VCG. To do this, in (2) 2, in a normal device, d y
= d +, so LraWra << L
It is better to set it to cc and Wca.

Here, in Figure 8 of the conventional example. is in the χ direction -ΔX
If it shifts, LrcWrc/LcJcc HaLycW
ra/Lca (Wcc, - ΔX), and the characteristics shift in the direction where the characteristics are not good.

Therefore, with this layout, there is no margin for positioning in the X direction, making it difficult to manufacture devices that meet strict positional accuracy.

In this way, in the conventional layout, one layer of gate EFRO
In order to ensure the stability of M, positioning was extremely difficult.

(2) FIG. 9 is a plan view showing a cell layout when integrating a conventional single-gate EFROM corresponding to the present invention (2).

In this case, two rectangular floating gates 2 are formed with a source contact hole ν, 3 in between.

Here, in order to make LFcWra<<LcJcc, if the gate length is made constant (LPG=Lee), wee must be increased. The cells extend in the horizontal direction, resulting in an increase in the area of the cells.

(3). (4) All conventional mask ROMs are “゜0
A method has been used to provide redundancy using ゜゛ or continuous areas of all "1s," but in this case, partial redundancy cannot be achieved, so efficient redundancy cannot be achieved. Therefore, the mask ROM
The production yield was reduced.

(5) FIGS. 10 (1) to (3) are sectional views illustrating a conventional example corresponding to the present invention (5).

FIG. 10 is an excerpt from the beginning of the process shown in FIG.

In Figure lO (1). An oxide film 11 and a field oxide film l2 are formed on the substrate 1.

Next, a resist 52 is deposited on the entire surface of the substrate, a control gate forming portion is opened, and P' (or As'') is injected through the opening to form an n° type control gate 3.

In FIG. 10(2), the resist 52 and oxide film 11 are removed. A gate oxide film 11 is newly formed on the substrate by thermal oxidation.
Form A.

On this occasion. On the ion-implanted control gate 3, the oxidation rate increases and the oxide film grows thickly, and the film thickness becomes dI<d,
becomes.

As a result, VFG becomes smaller than equation (2). Deteriorates write characteristics.

In FIG. 10(3), a polysilicon film 54 is grown as a conductive film over the entire surface of the substrate by vapor deposition and patterned to form the floating gate 2.

(6) Single-layer gate EpRo? Since the control gate of I is a diffusion layer, the layer resistance and junction capacitance become large, causing a delay in the rise time of the control gate, and deteriorating the writing and continuous writing characteristics.

[Problem to be solved by the invention]

An object of the present invention is (1) to create a layout that further increases the alignment margin of a gate EFROM, improves write characteristics, and facilitates manufacturing.

(2) The purpose is to create a layout that can reduce the cell area and achieve high integration.

(3), (4) When building a gate EFROM as a redundant cell in a mask ROM, it is possible to form it in the same process as the mask ROM without increasing the number of processes, and the purpose is to improve manufacturing yield.

(5) The purpose is to improve write characteristics by making the gate oxide film thickness equal on the control gate and on the channel region.

(6) The purpose is to reduce the layer resistance and junction capacitance of the control gate, reduce the delay in the rise time of the control gate, and improve the single write and successive write characteristics.

(Means for Solving the Problems) The above problems can be solved by: (1) a source of opposite conductivity type and a drain of opposite conductivity type formed in a semiconductor substrate of one conductivity type with a channel region separated;
A control gate electrode of an opposite conductivity type formed on the substrate apart from the channel region, and a floating gate integrally formed on the channel region and the control gate via the substrate and an insulating film. (1) A semiconductor device in which the floating gate is formed to straddle the control gate in the gate width direction, or (2) the gate length of the floating gate is formed larger above the control gate than above the channel region. or (3) the semiconductor device according to claim 1 or 2 as a mask ROM.
When fabricating the semiconductor device as a redundant cell, there is a step of introducing impurities of opposite conductivity type into the substrate to form a control gate of the semiconductor device on the surface of the substrate, and a step of forming a conductive layer on the substrate via an insulating layer. Covered. The conductive layer is patterned to form a mask ROM.
The word line, the gate of the peripheral circuit FET, and the floating gate of the semiconductor device are formed simultaneously. Using these word lines and gates as masks, impurities of opposite conductivity type are introduced into the substrate, and the source and drain of the mask ROM cell and the source of the peripheral circuit PET are formed on the surface of the substrate. A method for manufacturing a semiconductor device, comprising the steps of forming a drain, and a source and drain of the semiconductor device. Or. (4) Is the semiconductor device according to claim 1 or 2 a mask 1? O
a step of introducing an impurity of an opposite conductivity type into the substrate to form a bit line of the mask ROM and a control gate of the semiconductor device on the surface of the substrate when fabricating it as a redundant cell of M;
A conductive film is deposited on the substrate via an insulating film, and the conductive film is patterned to form word lines of the mask ROM and peripheral circuit F.
forming a gate of the ET and a floating gate of the semiconductor device;
Using these gates as a mask, impurities of opposite conductivity type are introduced into the substrate, and the sources of the peripheral circuit FETs are formed on the surface of the substrate.
A method for manufacturing a semiconductor device, comprising a step of forming a drain, and a source and drain of the semiconductor device. Alternatively, (5) the method for manufacturing a semiconductor device according to claim 1 or 2, wherein a gate oxide film is formed on the substrate by thermal oxidation.
Next, a conductive film is grown on the entire surface of the substrate, a resist is deposited on the conductive film, an opening is made in the resist in the control gate formation area, and an impurity is introduced through the opening using the resist as a mask. A method for manufacturing a semiconductor device comprising a step of forming a control gate, or (6) a source of an opposite conductivity type and a drain of an opposite conductivity type formed on a semiconductor substrate of one conductivity type with a channel region separated therebetween;
A control gate of an opposite conductivity type formed at a distance from and opposite to the channel region, and a floating gate integrally formed on the channel region and the control gate via the substrate and an insulating film. This is accomplished by a semiconductor device having a control gate connected in parallel to a conductive film formed on the substrate via an insulating film.

[Function] (1) Figures 1 (1) to (4) are diagrams of the principle of the present invention (1), including a plan view and an A-A sectional view showing the layout of a single-layer gate EPROM. B-8 sectional view. It is a CC sectional view.

The present invention eliminates the influence of -ΔX and obtains stable characteristics by forming a floating gate across the control gate in the gate width direction and providing the part (a) in Figure 1. This is what I did.

(2) Fig. 2 is a principle diagram of the present invention (2), and the gate E
FIG. 3 is a plan view showing the layout of a FROM cell.

Here, in order to make LraWya << L(Jcg), we adopted a layout in which LPG < LCG since increasing , increases the area of the cell.

In the figure. The following relationship holds between each D representing distance.

DI +02+03=04+DS+06. Here, D
．． , D3, D is taken as the minimum dimension of the vacuum gap.

The present invention includes +LFGWF. <<In order to get closer to LccWcc, as much as possible in the process, the cell is not extended horizontally by a layout in which G is larger than one FG,
This allows the cell area to be reduced.

(3) The present invention is more effective than mask ROM} EFROM
When making redundant data, writing is performed in a common process, increasing manufacturing yield without increasing the number of processes.

(4) The present invention is a mask ROM using a diffusion layer in the bit line.
By using the gate EFROM, the gate EFROM can be made redundant without increasing the number of steps.

(5) The present invention forms a gate oxide film prior to ion implantation for forming a control gate, and performs ion implantation through a polysilicon layer for forming a floating gate. This is intended to suppress the increase in oxidation rate caused by the influence of ion implantation.

As mentioned above, in the conventional example, dl<63 and at/dz
= about 1/2 to 1/3. For example, d+/dz=1/
3, from equation (2), Vrc'il/4 VcG
becomes.

However, in the present invention, since d + /dy = 1, VFG': 1/2 Vcc, and the width of ΔV can be increased.

(6) Figures (1) to (4) are diagrams of the principle of the present invention (1). A plan view showing the layout of a single-layer gate EPROM, ^
-Al1 side view, BB sectional view, c-c Ur side view.

In the present invention, the control gate is formed by a diffusion layer 3. By using a backing gate (a conductive film formed on the substrate via an insulating film) 8 connected in parallel to this, the resistance and capacitance of the control gate are reduced, thereby increasing the speed.

Next, explanation will be given using a numerical example.

The capacitance of the diffusion layer is CJD1[qχsioz εO NA ND/2(N
a + No) (φ-V)) ”” SJD,
The capacity of the lining gate is Cca= (χsiotεo /tax) Sce/(
1+2Zsioz” goV /ZstQNAtaxZ
)””. Here, C,,: Capacity of the failure layer Cce: Capacity of the backing gate SJD: Capacity of the failure layer S, . : Area of backing gate q : Electron charge χ31 : Relative permittivity of St χ,1. , : relative dielectric constant ε of Si02. : Vacuum relative dielectric constant NA2 Concentration of substrate N0: Concentration of diffusion layer φ: Built-in voltage V: Applied voltage Lox: Thickness of oxide film. Now SJIl = SCG = 4 μm x 700 μm + q
= 1.602X10-19C, χ, =+= 1
1.7. χ s+oz= 3.9 +e
o = 8.86 XIO-1C/Vcm, NA
= IXIO”cm-3+ N. = 5X1019
am-'(fi='0.83 V, to
Assuming x=4000 people and calculating the capacity when V=5V, CJD=1. (16 XIO-”C,Cc
c=1.03 XIO-13G, layer resistance of diffusion layer=60Ω/mouth. Gate layer resistance = 40Ω/port. Then, the resistance R of the diffusion layer is ．． = (700/4)x60=10.
5 KΩ gate resistance R,. = (700/4)X40
= 7. O KΩ Therefore, the time constant is τ1t+= CJDX RJD=l. l1 nS+τc
c” CccX Rca=0.72 nS. However, in this case SJD= SCG= 2,!/ m X700 p m
, and each area is divided into 172 parts.

CJD=0.53 XIO-l3C, Ccc=0.
52 XIO-13C, parallel capacitance c = 10.5
xlO-" c. Also, as above, the layer resistance of the diffusion layer = 60Ω/hole, the layer resistance of the gate = 40Ω/hole. Parallel resistance R = 8.25KΩ Therefore, the time constant τ is r = CXR = 0. It becomes 87 nS.

In this way, the time constant τ is approximately 21% higher than that in the case of only a diffused layer.
improves.

Furthermore, if you use polycide for the backing gate. The layer resistance is 5 to 10Ω/mouth. Even higher speeds can be achieved.

〔Example〕

(1) An embodiment of the present invention (1) will be described with reference to FIG.

In this example, +1 cc does not change due to the margin (a) even if there is a shift during alignment, so there is no need for a margin for alignment.

(2) FIGS. 3 and 4 are plan views of two embodiments of the present invention (2) showing layouts for integrating single-layer EPROM cells.

FIG. 3 shows an arrangement in which the cells face each other, and FIG. 4 shows an arrangement in which the cells are in the same direction.

In this example, a layout can be created that allows the cell area to be reduced, and higher integration can be achieved.

(3) Do Fig. 5 (1) to (7) show an example of the present invention (3) in the order of steps? It is a sectional view for explanation.

Part ■ = Cell part of mask ROM, Part ■: Peripheral circuit (n-channel FET) part, Part ■: Redundant single-layer gate EPROM part. Figure 5 (1) to (5) showing the process order are parts ■ to ■. This is a common process.

1 l of oxide film (SiO2 film) with a thickness of 300 mm on the process base 1 in FIG.
A nitride film (Si3N4 film) 5l with a thickness of 1500 mm is formed, and field oxide film forming portions are opened in the nitride film 51 at locations ① and ②.

A field oxide film 12 having a thickness of 6,000 wafers is formed by wet thermal oxidation in the process shown in FIG. 5(2).

In the step of FIG. 5(3), the nitride film 51 is removed, and a resist 52 with a thickness of 7000 mm is deposited on the entire surface of the substrate. Open the write cell part at the part,
At part ■, open the control gate forming part, and from the opening
(or As'') is implanted, and writing is performed to make the substrate surface of the write cell portion into an n-type at the region (2), and an n-type control gate 3 is formed at the region (2).

P+ implantation conditions are energy 60 KeV, dose I
XIO”C””.

Activation annealing after ion implantation in subsequent steps is performed by heat treatment in a subsequent step or by a separate step.

In the step of FIG. 5(4), the oxide film 11 is removed. A new gate oxide film 11A with a thickness of 250 nm is formed on the substrate by thermal oxidation, and a polysilicon film (or polycide film) 54 with a thickness of 4000 nm is formed as a conductive film over the entire surface of the substrate by vapor deposition. Long.

In the process of FIG. 5 (5), the polysilicon film 54 is patterned and the area ■ is P
ET gate 55 is formed. Floating gate 2 is formed in part ■, and the word line of the cell (gate > 58
(Note: The poly-Si film 8 in this example is removed. The poly-Si film 8 is applied to the embodiment of the present invention (6) described later.)
.

Next, As'
(or P) is implanted to form an n° type source 56 and drain 57 of the FET in the region ■, and an EFFET in the region ■.
A source 4 and a drain 5 of the ROM are formed, and an n-type source 59 and a drain 60 of the cell are formed in the region (2).

In part (■), a cross section of part A-A in the direction perpendicular to the page is shown below.

In the part section, cross sections of sections B-B and C-C in the direction perpendicular to the page are shown below.

The ^S implantation conditions were an energy of 70 KeV and a dose of 4XlO "cn+-".

In the above manner, the redundant EFROM could be manufactured in the same process as the mask ROM without increasing the number of processes.

After this, the normal process of mask ROM (Fig. 5 (6), (
7) Mask RO with redundant EFROM added via
Completely abstain from M.

In FIG. 5(6), a film 61 of 1,000 thick is formed on the entire surface of the substrate by a vapor phase process, covering the word line 58.
The PSG (phosphosilicate glass) membrane 62 of 00 people was sequentially heated. Planarize the substrate surface.

In FIG. 5 (7), an AI layer with a thickness of 1 um is placed on the PSG film 62.
A bit line 63 is formed. A cover PSG film 64 is placed thereon.

(4) FIGS. 6(1) to 6(7) are sectional views illustrating an embodiment of the present invention (4) in the order of steps.

Part ■: Mask ROM cell part, Part ■: Peripheral circuit (n-channel FET) part, Part ■: Redundant single-layer gate EPROM part. Figure 6 (1) to (5) showing the process order are parts ■ to ■. This is a common process.

An oxide film (SiOz film) 1 with a thickness of 300 mm is placed on the process substrate l shown in FIG. 6 (1).
A nitride film (SiJ4 film) 51 having a thickness of 1,500 μm is formed, and field oxide film forming portions are opened in the nitride film 51 at portions ① and ②.

A field oxide film 12 having a thickness of 6,000 wafers is formed by wet thermal oxidation in the process shown in FIG. 6(2).

Step (3) in FIG. 6: The nitride film 51 is removed, a resist 52 with a thickness of 7,000 mm is deposited on the entire surface of the substrate, and an opening is made in the area where the bit line will be formed. In the region (2), the control gate forming portion is opened, and P' (or As") is injected through the opening to form an n' type bit line 53 in the region (2) and an n' type control gate 3 in the region (2).

P0 implantation conditions are energy 70 KeV, dose I
X 10"cm-".

Activation annealing after ion implantation in subsequent steps is performed by heat treatment in a subsequent step or by a separate step.

Step oxide film 11 in FIG. 6(4) is removed, a new gate oxide film 11^ with a thickness of 250 mm is formed on the substrate by thermal oxidation, and then a conductive film is formed over the entire surface of the substrate by vapor deposition. A polysilicon film (or polycide film) 54 with a thickness of 4,000 layers is formed.

In the step (5) of FIG. 6, the polysilicon film 54 is patterned to form a region F.
ET gate 55 is formed. Floating gate 2 is formed in region (2). In this section, the word line 58 of the cell is formed (
Note: The poly-Si film 8 in this example is removed; this poly-Si film 8 is applied to the embodiment of the present invention (6) described later).

next. Cover part ■ with a 7000A resist (not particularly shown), and use the gates of parts ■ and ■ as a mask to apply As''
(or P) is implanted to form an n-type source 56 and drain 57 of the FET in the region (2). EF for part ■
The source 4 and drain 5 of the ROM are formed.

In part (■), a cross section of part A-A in the direction perpendicular to the page is shown below.

In section (2), the cross sections of section B-B and section C-C in the direction perpendicular to the page are shown below.

The As implantation conditions were an energy of 70 KeV and a dose of 4.times.10@15 am.

In the above manner, the redundant EFROM could be manufactured in the same process as the mask ROM without increasing the number of processes.

After this, the normal process of mask ROM (Fig. 6 (6), (
7) Mask RO with redundant EFROM added via
Complete M.

In Figure 6 (6). Using the resist 65 with an opening in the write cell portion as a mask, B° is implanted.

The B implantation conditions were an energy of 180 KeV and a dose of IXIO "cm-".

The threshold voltage of the injection cell increases and writing is performed.

In FIG. 6 (7), a SiOz film 61 with a thickness of 1000 mm and a thickness of 60 mm is formed over the entire surface of the substrate by covering the word line 58.
The PSG film 62 of oo person is sequentially lengthened to planarize the substrate surface.

Next, an A1 bit line 6 with a thickness of 1 μm is placed on the PSG film 62.
3 (for lining the diffusion bit line), and a cover PSG film 64 is formed thereon to a certain length.

(5) FIGS. 7(1) to 7(3) are sectional views illustrating an embodiment of the present invention (5).

This figure is a diagram for explaining the process improvement of the gate EFROM.

The difference from Figure 6 is that a gate oxide film is formed before the control gate is formed, and ions are implanted through the polysilicon layer for forming the floating gate to form the control gate, thereby increasing the gate oxide film in the control gate area. This is a point that was suppressed.

In FIG. 7(1), an oxide film 11 and a field oxide film l2 are formed on a substrate l.

In FIG. 7(2), the oxide film l1 is removed and a gate oxide film 11A is formed on the substrate by thermal oxidation.

In FIG. 7(3), a polysilicon film 54 is formed as a conductive film over the entire surface of the substrate.

Next, a resist 52 is deposited on the substrate, a control gate forming portion of the resist 52 is opened, and P° is injected through the opening to form an n° type control gate 3.

P゜ implantation conditions are energy 200 KeV, dose IX
IO"cm-".

After this, the process is similar to that shown in FIG. 6, and the polysilicon film 54 is patterned to form a floating gate, and the source and drain of the EFROM are formed.

(6) An embodiment of the present invention (6) will be described with reference to FIG.

In this example, a backing gate 8 made of a polySt film forming a control gate (diffusion layer) 3 and a floating gate 2 is connected to a wiring 7.
are connected in parallel.

FIGS. 12 and 13 are plan views of two embodiments of the present invention (6) showing layouts for integrating single-layer gate EFROM cells.

FIG. 12 shows an arrangement in which the cells face each other, and FIG. 13 shows an arrangement in which the cells are in the same direction.

In these examples. It is possible to create a layout that reduces the cell area and allows for higher integration.

Next, an embodiment of the manufacturing process for manufacturing the present invention (6) into a mask ROM will be explained with reference to FIGS. 5 and 6, and the differences will be explained.

(a) Corresponding to Fig. 5 In the process of Fig. 5 (5). The polysilicon film 54 is patterned to form part F
The gate 55 of the ET is formed, the floating gate 2 and the lining gate 8 are formed in the region (2), and the word line (gate) 58 of the cell is formed in the region (2).

(b) Corresponding to Fig. 6 In the process shown in Fig. 6 (5), the polysilicon film 54 is patterned and the area F is
ET gate 55 is formed. Floating gate 2 and backing gate 8 are formed in region (2). The word line 58 of the cell is formed in this area.

(a). All other steps in (b) are exactly the same as in FIGS. 5 and 6.

(Effects of the Invention) As explained above, according to the present invention, (1) a layout with a larger alignment margin for the gate EPROM can be achieved, and manufacturing can be facilitated;

(2) We were able to create a layout that reduced the cell area and achieved higher integration.

(3). (4) A gate EPROM can be built into the mask ROM as a redundant cell without increasing the number of steps, contributing to an improvement in manufacturing yield.

(5) The thickness of the gate oxide film can be made equal on the control gate and on the channel region, and the width of ΔV, which is one index of write characteristics, can be improved by 30 to 50%. .

(6) The layer resistance and junction capacitance of the control gate are reduced, the delay in the rise time of the control gate is reduced, and the writing and continuous writing characteristics are improved.

[Brief explanation of drawings]

Figures 1 (1) to (4) are principle diagrams of the present invention (1), and are plan views showing the layout of a single-layer gate EPROM;
The sectional view, B-8 sectional view, C-C sectional view, and Figure 2 are the principle diagrams of the present invention (2). Single layer gate EFRO
FIGS. 3 and 4 are plan views showing the layout of an M cell, and FIGS. ) is a sectional view explaining one embodiment of the present invention (3), FIGS. 6 (1) to (7) are sectional views explaining one embodiment of the present invention (4), and FIGS. 7 (1) to (3) is a cross-sectional view illustrating an embodiment of the present invention (5), and Figures 8 (1) and (2) are plan views showing the layout of a conventional single-gate EFROM corresponding to the present invention (1). and A-A sectional view, and Figure 9 shows a conventional single-layer gate EF corresponding to the present invention (2).
10 (1) to (3) are cross-sectional views illustrating a conventional example corresponding to the present invention (4); and FIG. 11 (1) to (4) is a principle diagram of the present invention (6), which is a plan view showing the layout of a single-layer gate EFROM;
A cross-sectional view, B-B cross-sectional view, CC cross-sectional view, FIGS. 12 and 13 are single-layer games} Plan views of two embodiments of the present invention (6) showing layouts for integrating EFROM cells. be. In the figure, l is the substrate, 2 is the non-volatile memory part and the floating gate (FG), 3 is the control gate (CG, A side), 4 is the source, 5 is the drain, and 6 is the insulation. membrane, 7 is wiring 8 is backing gate No. 3 Concave No. 4 Figure Hon Hatsuro [5] English 1 example 1 name ahead cross-sectional view Temple 7 Figure (1) Plan view (2) A-A cross section Book A5 Sun Moon (1) I L Kazuretsu Otoko 8 The conjuring diagram that shows the conventional A row of the picture book date and month (2), and the previous day and month. 10 Fig. Example of a real wild goose of the present invention (ra) Fig. 12 (1) Plane ■ (3) 6-8 cross section (41C-C 餠面4S plane March (ra) principle) Fig. of the present invention (ra) Other fruit baskets 511 夷13 fig.

Claims (6)

[Claims] (1) A source of an opposite conductivity type and a drain of an opposite conductivity type formed on a semiconductor substrate of one conductivity type across a channel region; and a control gate of an opposite conductivity type formed on the substrate apart from the channel region. , a floating gate formed integrally with the substrate on the channel region and on the control gate via an insulating film, and the floating gate is formed to straddle the control gate in the gate width direction. A semiconductor device characterized by: (2) The semiconductor device according to claim 1, wherein the gate length of the floating gate is larger on the control gate than on the channel region. (3) The semiconductor device according to claim 1 or 2 is covered with a mask R.
When fabricating as a redundant cell of OM, there are two steps: introducing impurities of opposite conductivity type into the substrate to form a control gate of the semiconductor device on the surface of the substrate, and forming a conductive layer on the substrate via an insulating layer. The conductive layer is patterned to form mask ROM word lines and peripheral circuits F.
The gate of the ET and the floating gate of the semiconductor device are formed at the same time, and impurities of opposite conductivity type are introduced into the substrate using these word lines and gates as masks to form the source and drain of the mask ROM cell on the surface of the substrate. A method of manufacturing a semiconductor device, comprising the steps of forming a source and a drain of a peripheral circuit FET and a source and a drain of the semiconductor device. (4) The semiconductor device according to claim 1 or 2 is covered with a mask R.
When fabricating as a redundant cell of OM, a step of introducing impurities of opposite conductivity type into the substrate to form a bit line of the mask ROM and a control gate of the semiconductor device on the surface of the substrate, and an insulating layer on the substrate. A conductive film is deposited through the film, and the conductive film is patterned to form mask ROM word lines and peripheral circuits F.
The gate of the ET and the floating gate of the semiconductor device are formed, and impurities of opposite conductivity type are introduced into the substrate using these gates as a mask to form the source and drain of the peripheral circuit FET and the source of the semiconductor device on the surface of the substrate. A method for manufacturing a semiconductor device, comprising the steps of: forming a drain; (5) The method for manufacturing a semiconductor device according to claim 1 or 2, comprising: forming a gate oxide film on the substrate by thermal oxidation, then growing a conductive film on the entire surface of the substrate; manufacturing a semiconductor device, comprising the steps of: depositing a resist on a control gate, opening the resist in a control gate forming portion, and introducing impurities through the opening using the resist as a mask to form the control gate. Method. (6) a source of an opposite conductivity type and a drain of an opposite conductivity type formed on a semiconductor substrate of one conductivity type across a channel region; and a control gate of an opposite conductivity type formed on the substrate apart from the channel region; A floating gate is formed integrally with the substrate on the channel region and on the control gate via an insulating film, and the control gate has a conductive film formed on the substrate via an insulating film. A semiconductor device characterized by being connected in parallel.