JPH01233773A - Semiconductor nonvolatile memory - Google Patents

Abstract

PURPOSE:To realize a memory whose program characteristic is excellent and which is suitable for becoming minute by a method wherein, in a floating gate type semiconductor nonvolatile memory, a source region is formed of a thin and shallow junction. CONSTITUTION:After a gate oxide film 5 has been formed on the surface of a semiconductor substrate 1, a floating gate electrode 6, a control gate insulating film 7 and a control gate electrode 8 are formed one after another on the surface of the substrate 1. Then, a thin and shallow source region 3 and a dense and deep drain region 4 are formed by ion implantation in a self-alignment manner with reference to the floating gate electrode 6. A dense and deep region 2 for wiring use is formed to be away from the floating gate electrode 6. The drain region 4 is formed in a self-alignment manner by making use of the floating gate electrode 6 as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor nonvolatile memory used as an information storage device in electronic equipment such as computers.

[Summary of the invention]

The present invention is intended to realize a floating gate type semiconductor nonvolatile memory that has excellent program characteristics and is suitable for miniaturization by forming a source region with a thin and shallow junction.

[Conventional technology]

Conventionally, as shown in FIG. 2, a floating gate electrode 6 and a control gate electrode 8 are formed on the surface of a semiconductor substrate 1 via a gate insulating film 5, and ions are formed in a self-aligned manner with respect to the floating gate electrode 6. A source region 2 and a drain region 4 were formed by implantation.

[Problem to be solved by the invention]

However, in conventional semiconductor nonvolatile memory, since the capacitance between the source region 2 and the floating gate electrode 6 cannot be reduced, the capacitance between the floating gate electrode 6 and the control gate electrode 8 is reduced (by reducing the capacitance coupling). It was necessary to increase the ratio and lower the programming voltage. That is, in order to increase the capacitance between the control gate electrode 8 and the floating gate electrode 6, it was necessary to increase the area of the memory.

[Means to solve the problem]

In order to solve the above problems, the present invention reduces the capacitance between the source region and the floating gate electrode by forming the source region with a thinner and shallower junction than the drain region, resulting in excellent programming characteristics. In addition, we have realized a semiconductor nonvolatile memory that is suitable for miniaturization.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a sectional view of a semiconductor nonvolatile memory according to the present invention. A case where the memory is an N-type transistor will be explained. After forming a gate oxide film 5 on the surface of a P-type semiconductor substrate 1, a floating gate electrode 6, a control gate insulating film 7, and a control gate electrode 8 are sequentially formed. Generally, floating gate electrode 6 is patterned in a self-aligned manner with respect to control gate electrode 8. Therefore, the width of the floating gate electrode 6 is formed to be approximately equal to the width of the control gate electrode 8. Next, a thin and shallow source region 3 and a thick and deep drain region 4 are formed by ion implantation in a self-aligned manner with respect to the floating gate electrode 6. A dense and deep source region 2 for wiring is formed apart from the floating gate electrode 6. This dense source region is
Floating Gate 'T! If a sidewall is formed by using the stepped portion formed by the single pole 6 and the control gate electrode 8, and then formed by ion implantation using the sidewall as a mask, the self-portion is formed at a certain distance from the floating gate electrode 6. Can be formed consistently. Drain region 4 is formed in a self-aligned manner using floating gate electrode 6 as a mask before sidewall formation. Approximately 10V is applied to the drain region 4 and approximately 12.5V is applied to the control gate electrode 8 to generate hot electrons near the drain region 4 due to the channel current, and a portion of them are injected into the floating gate electrode 6. Injected memory stores information because the channel conductance of non-injected memory is lower. The potential of the floating gate electrode is given by the following equation.

Ct Ct CtCt
CT Here, Ccei Capacitance CD between control gate electrode 8 and floating gate electrode 6; Capacitance C3 between drain region 4 and floating gate electrode 6: Capacitance C1Elk between source region 3 and floating gate electrode 6 ;Capacitance Ca between substrate 1 and floating gate electrode 6 ;Total capacitance around floating gate electrode 6 (CCG+
CD +Cs 10 sub)Vec; Potential of control gate electrode 8 VDi Potential of drain region 4 ■3; Potential of source region 3 ■3□; Potential Q of substrate 1; , vs = V sub −Ov, then V,
is as follows.

Ct Ct,
The capacitive coupling ratio to ensure Ct programming characteristics is (
From formula 2), the following formula is obtained.

Cy Cs +CB +C5ub +CccBy forming a semiconductor nonvolatile memory having the structure shown in FIG. 1, the capacitance C8 between the floating gate electrode 6 and the source region 3 can be reduced. Since C5 becomes smaller, the same capacitive coupling ratio can be obtained even if the capacitance C6 between the control gate electrode 8 and floating gate electrode 6 is reduced. That is, a small semiconductor non-volatile memory becomes possible. Furthermore, since the source region 3 is a shallow and thin junction, the channel length, which is the length between the source region 3 and the drain region 4, can also be shortened. The ability to shorten the channel length enables smaller semiconductor memories with even better programmability.

The thin and shallow source region 3 used in the present invention can be formed without increasing the number of manufacturing steps. When the channel length of the control system circuit of semiconductor nonvolatile memory becomes less than 2 μm, it becomes necessary to form the source and drain regions with a thin concentration in order to prevent a decrease in reliability due to the generation of hoft electrons at the edge of the drain region. It's coming. Therefore, the shallow source region 3 of the present invention can be formed without increasing the number of steps by forming the thin source and drain regions of the memory peripheral circuit transistor at the same time.

Further, the drain region 4 of the semiconductor nonvolatile memory of the present invention needs to generate sufficient hot electrons during programming, and therefore, unlike the source region 3, it needs to be formed in a dense region. By making the drain region 4 denser than the source region 3, a semiconductor nonvolatile memory with excellent program characteristics can be achieved.

FIG. 3 is a sectional view of a second embodiment of the semiconductor nonvolatile memory of the present invention. A control gate region 18 is formed on the surface of substrate l. Floating gate electrode 6 is formed on top with control gate insulating film 17 interposed therebetween. As shown in Figure 3,
Also when the control gate region 18 is formed within the substrate 1,
By forming the source region 3 thinner and shallower than the drain region 4, a semiconductor nonvolatile memory with excellent program characteristics and suitable for miniaturization can be realized.

〔Effect of the invention〕

As explained above, the semiconductor nonvolatile memory of the present invention has excellent program characteristics and is suitable for miniaturization by forming the source region thinner than the drain region and with a shallow junction. It has the effect of

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a semiconductor nonvolatile memory according to the present invention, and FIG. 2 is a sectional view of a conventional semiconductor nonvolatile memory. FIG. 3 is a sectional view of another embodiment of the semiconductor nonvolatile memory of the present invention. 1... Semiconductor substrate 3... Thin and shallow source region 4... Drain region 6... Floating gate electrode 8... Control gate electrode Applicant: Seiko Electronic Industries, Ltd. 1 company Figure 1 Figure 2

Claims (1)

[Claims] A semiconductor nonvolatile memory comprising a source region and a drain region formed at intervals on the surface of a semiconductor substrate, and a floating gate electrode formed on a channel region between the source region and the drain region with a gate insulating film interposed therebetween. A semiconductor nonvolatile memory according to claim 1, wherein the source region is formed to have a lower concentration than the drain region.