JPH0316157A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a contact defect from being produced by a method wherein a convex pattern is formed in advance in a region used to form a contact hole on a first-layer interconnection so that an SOG(spin-on-glass) layer is not formed. CONSTITUTION:A field oxide film 3 is formed; at the same time, an island- shaped oxide-film pattern 3S whose height h1 is equal to that of the field oxide film 3 is formed in a region Ac which is used to form a contact hole and to which an interconnection layer is interlayer-connected at the upper part inside an element formation region 2. As a result, an SOG layer 16 with which a CVD-method SiO2 film 15 on a first-layer Al interconnection 13 at the upper part of the island-shaped oxide-film pattern 3S is coated to be very thin is removed completely by an etching operation; the SOG layer 16 is not exposed on a side face of a contact hole 18; moisture and an organic-substance gas are not released from the side face of the contact hole 18. Thereby, a second- layer Al interconnection 19 which is deposited inside the contact hole 18 becomes a homogeneous layer which is not made coarse particles; a contact resistance between the first-layer Al interconnection 13 and the second-layer Al interconnection 19 becomes a sufficiently low and stable value.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Embodiment Process sectional view of the first embodiment (Fig. ) Process sectional view of the second embodiment (Fig. 2) Plan view of the semiconductor device according to the second embodiment (Fig. 3) Process sectional view of the third embodiment (Fig. 4) Third embodiment A plan view of a semiconductor device according to the present invention (Fig. 5) Effects of the invention [Summary] This invention relates to an improvement in a method for manufacturing a semiconductor device, particularly a method for manufacturing a semiconductor device with a multilayer wiring structure in which the wiring formation surface is flattened by applying SOGN. , the purpose of this is to prevent the contact resistance of the interlayer connection part of the wiring from increasing due to degassing from the SOG layer, thereby improving the characteristics and reliability of the semiconductor device. In a method for manufacturing a semiconductor device in which a second wiring a layer is formed via an interlayer insulating film after flattening by applying a glass layer, the first wiring layer is flattened before applying the spin-on glass layer. The method includes the step of forming a region on the layer in which a contact hole is to be formed to be higher than the surrounding area using a convex layer to make it difficult for a spin-on glass layer to be applied to the region in which a contact hole is to be formed.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for manufacturing a semiconductor device having a multilayer wiring structure in which a wiring formation surface is flattened by applying an SOG (spin-on-glass) layer.

In highly integrated semiconductor ICs and the like where miniaturization has progressed, not only patterns such as elements and electrode wirings are reduced in the lateral direction, but also wiring is multilayered.

In semiconductor devices with multilayer wiring, it is extremely important to planarize the lower layer to improve the accuracy of upper layer pattern formation and the coverage of upper layer wiring in order to increase yield and reliability. . A method that has been widely used recently as a means to easily planarize the lower layer is:
There is a method of applying an SOG layer, but this method has the problem of easily causing contact failure at the interlayer connection portion of wiring, and an improvement is desired.

[Conventional technology]

A conventional semiconductor device whose lower layer is planarized using SOG is an example of a MOSFET as shown in FIG. 6(a).
(It was formed by the method described with reference to the process cross-sectional diagram of the powder.

Referring to FIG. 6(a), for example, a p-type silicon (St) substrate 51 is first subjected to normal selective oxidation (LOCOS method) to form an element of 7i type. A field oxide film 53 for element isolation is formed to define the periphery of the region 52. (Channel stopper omitted) Fig. 6 (
Refer to b) Next, according to a normal MOS process, a gate oxide film 54 is formed on the device type t2 nozzle region 52, and a polySt layer is formed, an impurity is introduced into the polySi layer, and patterning is performed to form the gate oxide film 54. For example, an n+ type polySt gate electrode 55 is formed thereon, and ions are implanted using this gate electrode 55 as a mask to form an n+ type source region 56 and drain region 57.

? 6(C) Next, after removing the exposed gate oxide film 54, an oxide film for impurity blocking was formed on the Si exposed surface for 5 days. Next, a lower layer made of phosphosilicate glass (PSG) etc. was formed on this substrate. After forming an insulating film 59 and forming a contact window 60 for the source and drain regions penetrating the lower insulating film 59 and the impurity blocking oxide film 58, a lower wiring material such as aluminum (Affi) is formed on the substrate.
A layer is formed and patterned by ordinary photolithography to connect the source wiring 61 and drain wiring 62 made of Al and other diffusion regions (not shown), and to extend over the lower insulating film 59 above the source region 56. 1st of 1
A layer Al wiring 63, a second 111Af wiring 64 extending over the lower insulating film 59 above the field oxide film 53, and the like are formed.

Refer to FIG. 6(d) Next, the AN wirings 61, 62, 63 of the lower layer (first layer)
, 64, etc., after forming a thin chemical vapor deposition (CVD) SiO2 film 65, which is a part of the interlayer insulating film, the upper ?
In order to flatten the upper surface of the interlayer insulating film forming the wiring, an SOG layer 66 is spin-coated on the substrate on which the thin CVD-SiO film 65 is deposited, and the SOG layer 66 is coated at a temperature of about 400 to 450''C. Layer 66 is dried and solidified.

Referring to FIG. 6(e), the coated surface of the SOG layer 66 is then entirely etched by plasma etching means using, for example, methane trifluoride (CFIF+) gas, and A2 is formed on the upper part of the field oxide film 53 and at a high position. The SOG layer 66 above the wirings 64, 65, etc. is removed, the lower parts are filled, and only the SOG layer 66 that contributes to planarization remains.

Referring to FIG. 6(f), a PSG film 67 is then formed as the remainder of the interlayer insulating film on the substrate by the CvD method, and then the AN wiring in the lower part, for example, the first A glabella contact window 68 exposing the first layer A2 wiring 63 is formed. Here, the Al wiring 63 in the lower part
On the top of the AN wiring 63, there is a thin CVD-Sin2 film 65, which is part of the interlayer insulating film directly attached to the AN wiring 63, and a PSG film 67, which is the remaining part of the interlayer insulating film. Since the SOG layer 66 for planarization is interposed, the end face of the SOG layer 66 is exposed on the side surface of the interlayer contact window 68.

Next, an Affi layer is formed on the substrate by a sputtering method or the like, and then patterning is performed by ordinary photolithography to connect the lower first layer A1 wiring through the interlayer contact window 68. An upper layer Al wiring 69 is formed on the PSG film 67 from 63, and thereafter a covering insulating film (not shown) is formed, and the semiconductor device is completed.

(Problem to be Solved by the Invention) However, in the above conventional method, the field oxide film 5
3, for example, the source region 56
For example, the first first layer AI! ．． Wiring 6
As explained with reference to FIG. 4(f), the end surface of the SOG layer 66 coated for flattening the upper wiring formation surface is exposed on the side surface of the interlayer contact window 68 formed in the interlayer insulating film 3. do.

Therefore, when depositing an upper wiring material layer such as the above-mentioned Ai layer on the interlayer insulating film, that is, the PSG film 67 including the inner surface of the contact window 68 between the eyebrows, by sputtering, it is necessary to , SO from the end surface of the SOG layer 66 exposed on the side surface of the glabella contact window 68.
Moisture and organic gases contained in G are released, and A1 particles 69G are made coarse by incorporating these moisture and organic substances.
However, the lower layer Al wiring 63 exposed inside the contact window 68
Since it is deposited on top, the /l wiring 69 of the upper N (second layer) formed by patterning this A1 sputtered film,
As mentioned above, the element type $. There is a problem in that the contact resistance with the lower layer (first layer) A2 wiring 63 disposed at a low position in the area becomes extremely high.

Furthermore, as shown in a schematic cross section in FIG. 7, the above problem is caused by, for example, the first layer AN wiring 63 which is formed over the parallel gate electrodes 55^ and 55B with the lower insulating film 59 interposed therebetween.
The upper layer A in the lower part between the gate electrodes 55A and 55B
When connecting the N wiring 69, SOG accumulates on the lower part of the /l wiring 63 in the first layer and is exposed in the contact window 68.
This occurs as before by outgassing from layer 66. (
In the figure, 51 is an St substrate, 65 is a CVD-Stow film, 6
7 is a PSG film, 69G is a coarse-grained Al particle) Therefore, in the process of forming a multilayer wiring in which the lower layer is planarized by applying an SOG layer, the present invention aims to improve the interlayer connection of wiring by degassing from the SOG layer. The object of the present invention is to improve the characteristics and reliability of a semiconductor device by preventing an increase in contact resistance of the semiconductor device.

[Means for Solving the Problem] The above problem is to flatten the unevenness on the first wiring layer by applying a spin-on glass layer, and then form a second wiring layer via an interlayer insulating film. In the method for manufacturing a device, before applying the spin-on glass layer, a region on the first wiring layer where the contact hole is to be formed is formed in advance higher than the surrounding area using a convex layer, and the contact hole is planned to be formed in the area on the first wiring layer. This problem is solved by a method of manufacturing a semiconductor device according to the present invention, which includes a step of making it difficult for a spin-on glass layer to be applied to a region.

[Function] That is, the present invention provides a second (upper layer) wiring layer on a first (lower layer) wiring layer.
The contact hole formation area with the wiring layer of SoG
Before applying the layer, it is formed higher than the surrounding area (or at a height equivalent to the highest level of the surrounding area), and the surface on which the first wiring layer and the first wiring layer are formed is flattened. This makes it difficult for the SOG layer to be applied to the area where the contact hole is to be formed.

This makes it possible to completely remove the SOG layer in the region where the contact hole is to be formed without deteriorating the flatness of the planarized surface, so an interlayer insulating film is formed on the SOG coated surface, When a contact hole is formed in the area where the contact hole is to be formed, the side wall of the SOG layer is not exposed on the side surface of the contact hole. Therefore, the second wiring layer buried in this contact hole does not come into contact with the side wall surface of the SOG layer in the contact hole and is not coarsened by degassing from the SOC. A good glabellar connection with low contact resistance between the first wiring layer and the second wiring layer can be obtained.

〔Example〕 The present invention will be specifically explained below with reference to illustrated embodiments.

FIGS. 1(a) to 1(g) are process sectional views of the first embodiment of the present invention, FIGS. 2(a) to (f) are process sectional views of the second embodiment of the present invention, and FIGS. The figure is a schematic plan view of a semiconductor device manufactured according to the second embodiment, FIGS. 4(a) to (h) are process sectional views of the third embodiment of the present invention, and FIG. 1 is a schematic cross-sectional view of a semiconductor device manufactured according to an example.

Identical objects are indicated by the same reference numerals throughout the figures.

Refer to FIG. 1(a) First Embodiment In a first embodiment of the present invention, for example, a MOS type semiconductor device having a multilayer wiring structure is manufactured using a method according to B, for example, on a P-type St base Vi1, At the same time, a field oxide film 3 with a thickness of approximately 6000 to 4000 mm (height h. = 3000 to 4000 mm) is formed to define an element formation region 2 by a selective oxidation method called LOGOS using an oxidation-resistant film (not shown) as a mask. An island-shaped oxide film pattern 3S having a thickness equal to that of the field oxide film 3 (height = h+) is formed in the element formation region 2 in a region where a contact hole is to be formed on which a connection between the eyebrows of the wiring layer will be made later. Form. (The description of the channel stopper is omitted.) Refer to FIG. 1(b) Next, according to the normal MOS process,
A gate oxide film 4 with a thickness of about 200 μm is formed on one surface of the Si substrate exposed on the surface, and a gate oxide film 4 with a thickness of 40 μm is formed on this substrate by the CvD method.
After forming a poly-SiN layer of about 0.00 mm, impurities are introduced into this poly-Si layer to impart, for example, n-type conductivity, patterning is performed by ordinary photolithography to form a poly-Si gate electrode 5. Then the field oxidation ff! 3. Using the island-shaped oxide film pattern 3S and the gate electrode 5 as a mask, apply arsenic (for example) to the two surfaces of the element formation region.
n-type source regions 6a, 6b and drain region 7 are formed by ion-implanting As'') at a high concentration.The source regions 6a and 6b shown on both sides of the island-like oxide film pattern 3S are shown on the paper. It is continuous in the front and back direction.

Refer to FIG. 1(C) Next, after removing the exposed gate oxide film 4, an impurity blocking oxide film 8 is formed on the St exposed surface by thermal oxidation.
Then, CVD. By law, the lower layer is about 5,000 to 6,000 people thick and consists of PSG, etc.! ! ! An edge film 9 is formed, and then a source contact hole (SC) 10s and a drain contact hole (DC) 100 are formed by normal photolithography, and then a contact hole (SC) 10s is formed on this substrate to a thickness of 6000 to 8000 by a sputtering method or the like.
An Al source wiring 11 is formed by forming an A2 wiring layer made of pure /l or /l-1% Si alloy, etc., and patterning is performed by ordinary photolithography to connect to the source region 6b at the contact window. A2 connected to the drain region 7 and extending above the field oxide film 3
Drain wiring? 2. An l-th first N/I which is connected to a diffusion region (not shown) and extends over, for example, the source region 6a of the element formation region 2, and whose connection end with the upper layer wiring extends over the island-shaped oxide film pattern 3S. A second first layer Aff extending from the l wiring 13 and a region not shown on the field oxide film 3
Wiring 14 and the like are formed.

Referring to FIG. 1(d), a CVD-SiO2 film 15 (7) of about 1,000 to 2,000 thickness (7), which is a part of the interlayer insulating film, is formed on the wiring formation surface, and then, for example, the film is heated at a rate of
SOG was applied using a spin coating method of about 40°C.
Dry and solidify at about 0 to 500'C. l6 indicates the applied SOGN.

Referring to FIG. 1(e), the above-mentioned SOGJi! 16 on the A2 drain wiring ml2 on the field oxide film 3, the second first
Etching is performed on the entire surface until the CVD-SiO film 15 on the first layer wiring at a high position such as the first layer/l wiring 13 on the layer Al wiring 14 and the island-like oxide film pattern 3S is exposed. . This entire surface etching substantially flattens the substrate surface.

Refer to FIG. 1(f) Next, a PSG film 17 with a thickness of about 6,000 to 8,000 layers, which is the remaining part of the interlayer insulating film, is deposited on the planarized substrate by CVD.
After forming by method D, this PSG film 17 and its lower part are coated with a CVD method in a region A where a contact hole is to be formed between wiring layers in which an island-like oxide film pattern 3S is disposed below the PSC film 17. The first film passes through the Sing film l5.
A contact hole 18 exposing the layered Al wiring 13 is formed. The first 11i/l wiring 13 above the island-like oxide film pattern 3S is etched in the previous step.
Since the SOG layer 16 that was thinly coated on the above CvD method Sin2 film 15 has been completely removed, the side walls of the SOG layer 16 will not be exposed on the side surfaces of the interconnection interlayer contact hole 18. do not have.

FIG. 1 (see opaque) Next, pure A1 or Af-1% is deposited on the PSG film 17 including the inside of the contact hole 18 by sputtering or the like.
An Af wiring layer made of Si alloy or the like with a thickness of about 1 μm is formed, and patterning is performed by ordinary photolithography to contact the first first layer Al wiring 13 in the contact hole 18 and on the PSG film 17. second extending
Layer A1 wiring 19 is formed. Here, as mentioned above, the SOG layer l6 is not exposed on the side surface of the contact hole 18, and no moisture or organic gas is released from the side surface of the contact hole l8.
The mAN wiring 19 becomes a homogeneous layer without coarse graining, and
The contact resistance between the layered Al wiring 13 and the second NAl wiring 19 has a sufficiently low and stable value.

After that, the coating insulating film is formed, and the M according to the present invention is formed.
The OS type semiconductor device is completed.

Next, before applying the SOG layer, a convex insulating film pattern is formed in the area where the contact hole is to be formed on the wiring layer to make it difficult for the SOG layer to be applied to this area. Regarding the second embodiment, FIG. 2(a)
This will be explained with reference to the process cross-sectional views shown in -(f) and the schematic plan view of the semiconductor device shown in FIG.

? Refer to FIG. 2(a) In the second embodiment, gate electrodes 23A and 23B made of poly-Si or the like and extending in parallel are formed on a semiconductor substrate 21 made of, for example, St with a gate oxide film 22 interposed therebetween. Using these gate electrodes 23A and 23B as a mask, source and drain regions (not shown) are formed by ion implantation, and then a lower insulating film 24 is formed on the entire surface of this substrate, and the gate electrodes 23A and 23B are formed thereon. An A42 layer 125 for the first layer wiring extending over the top of the substrate is formed by sputtering or the like.

At this time, the surface of the 11th layer 125 has a concave shape above the gap between the gate electrodes 23A and 23B, depending on the shape of the underlying layer.

Refer to FIG. 2(b) Next, a second CVD-SiOz film is formed on this Affi layer 125, and a resist is further applied thereon, and then the resist is patterned using photolithography technology. The CVD-SiO film is patterned using the resist 26 as a mask, and a convex CVD-SiO film pattern 27 is formed only in the area where the contact hole to be connected to the upper 142 wiring layer is to be formed, and this area is covered with a cushion. Make sure to cover the shape pattern.

Refer to FIG. 2(C) Next, after applying a resist 28 to the entire surface, the resist 28 is patterned using photolithography technology, and the Al layer 125 is patterned using the patterned resist 28 as a mask. The first consisting of A1
Layer wiring 25 is formed.

Refer to FIG. 2(d) Next, after removing the resist 28, CVD is applied to the entire surface of the substrate.
- Deposit a SiOz film 29. This CVD-Si02
The film 29 functions to suppress the /l protrusion formed on the surface of the first layer wiring 25.

Next, an SOG layer 30 is applied to the entire surface, filling the recesses on the surface and flattening the surface. At this time, the CVD-Sin2 film pattern 27 is formed in the area where the 11-/l contact hole shape is planned to be formed between the +1 wiring layer in the upper layer and the area is raised, so when applying the SOG layer 30, On the CVD-SiOz film pattern 27 in this area? Mostly SO
G layer 30 is not formed.

Thereafter, an annealing process is performed to evaporate the solvent of SOG1i30 and solidify it. Then, the entire surface is slice-etched and CVD-Sin. The SOG layer 3 may remain slightly on the film pattern 27 due to its surface shape.
Remove 0 just to be sure.

Refer to FIG. 2(e) Next, a PSG layer 31 is deposited on the entire surface, and then a resist 32 is applied on the entire surface, and then buttering is performed, and the patterned resist 32 is used as a mask to form a PSG layer.
A contact hole 33 is formed in the layer 31 and the CVD-SiO2 film 29 below it. As mentioned above, Al-A
l Since there is no SOG layer in the opening area of the contact hole 33, SOG layer is not present on the side surface of the opened contact hole 33.
The sidewalls of the OG layer 30 are never exposed.

Refer to FIG. 2(f) Next, after forming 11 layers on the entire surface, patterning is performed to form the first layer/l in the contact hole 33.
A second layer Aff wiring 34 connected to the wiring 25 is formed.

Note that as mentioned above, SOG is applied to the side surface of the contact hole 33.
Since the sidewalls of the layer 30 are never exposed, the second NA1 wiring 34 is SOGF! 30, and no increase in contact resistance occurs due to coarsening of the Al particles.

FIG. 3 schematically shows the planar shape of the semiconductor device manufactured according to the second embodiment, and each reference numeral in the figure represents the second embodiment.
Shows the same object as the figure.

Next, according to the third embodiment of the present invention, a method of forming a convex layer simultaneously with a poly-Si layer used for a resistance layer and a wiring layer will be described in FIG. ) ~
(This will be explained with reference to a process cross-sectional view of the mesh and a schematic plan view of the semiconductor device shown in FIG. 5.

With the increasing integration of semiconductor devices, for example, the board
In addition to being used as a gate electrode of a MOS transistor, the second poly-Si layer is often used as a resistance layer or a wiring layer.

This embodiment is particularly effectively applied to a semiconductor device in which poly-Si layers are formed in multiple layers.

Refer to FIG. 4(a). First, gate electrodes 23A and 23 made of, for example, a polySt layer are placed on a semiconductor substrate 21 via a gate oxide film 22.
B is formed, and source and drain regions (not shown) are further formed on the surface of the semiconductor substrate 21. Then, a lower insulating film 24 is deposited over the entire surface.

Refer to FIG. 4(b) Next, a second poly-Si layer is deposited on the lower insulating film 24, and patterning is performed using a resist 35 to form a poly-Si layer 36 that will be used as a resistance layer or a wiring layer. At the same time as forming the AI. -A cushion-shaped poly-Si pattern 37 is also formed in the area where the A1 contact hole shape is to be formed, spanning over the recess and covering this area. Herein lies the feature of this embodiment.

Note that this poly-Si pattern 37 is formed using all Al-
It is not necessary to perform this on the area where the Al contact hole is planned to be formed.
AI where the surface of the lower Af layer becomes a recess. -Although only the area where the Al contact hole is planned to be formed is the same as in the previous embodiment, in any case, the poly-Si layer pattern 36 as a resistance layer and wiring layer is formed at the same time, so the number of steps is increased. It can be done without.

Referring to FIG. 4(C), an interlayer insulating film 38 is then deposited on the entire surface of the substrate, and then a first OAl layer 125 is formed on the interlayer insulating film 38.

Refer to FIG. 4(d) Next, as in the previous embodiment, using a resist as a mask, the first (7)
) After patterning Aj 21 to form the first layer Al wiring 25, a CVD-S film is applied over the entire surface of the substrate as in the previous embodiment.
An iOz film 29 is formed.

Refer to FIG. 4(e) Next, an SOG layer 30 is applied to the entire surface to planarize the surface. Here, a poly-Si layer pattern 37 is formed in the area where the Al--Al contact hole is planned to be formed, and the height of this area is increased, so that the Cv low St02 film 29 above the poly-St layer pattern 37 is The fact that almost no SOG layer 30 is formed is exactly the same as in the previous embodiment.

Next, after performing an annealing treatment to solidify the SOG layer 30, the entire surface is slice-etched as in the previous embodiment to remove a small amount of the SOG layer 30 that may remain in the area where the AN-Al contact hole is planned to be formed. Remove it just in case.

Refer to FIG. 4(f) Next, as in the previous embodiment, an interlayer insulating film 31 is formed on the substrate.

Refer to FIG. 4(g) Next, as in the previous embodiment, using the resist 32 as a mask,
The first layer A1 is placed in the area where the I2-Af contact hole is to be formed.
Delivery! , 9125 is opened. At this time, as mentioned above, since the SOG layer 30 does not exist in the area where the Al-Al contact hole is planned to be formed,
The side wall of the SOG layer 30 is not exposed on the side surface of the opened contact hole 33.

Refer to FIG. 4(h) Next, after removing the resist 32, a first insulating layer is formed in the contact hole 33 on the interlayer insulating film 31 as in the previous embodiment.
The second layer 142 wiring 34 connected to the layer cotton distribution 25 is shaped. At this time, since the side wall of the SOG layer 30 is not exposed on the side surface of the contact hole 33 as described above, the second layer AN wiring 34 buried in the contact hole 33 does not come into contact with the SOG layer 30.

Therefore, the contact resistance does not increase due to coarsening of the A2 particles in the contact hole 33.

FIG. 5 is a plan view of a semiconductor device after completing the above steps, and each reference numeral in the figure indicates the same object as in FIG. 4.

As shown in the first, second, and third embodiments, in the method of the present invention, in forming a multilayer wiring including a planarization step using soc1H, Af-, An island-like oxide film pattern formed in advance at the same time as the field oxide film, a CVD-Sing film pattern 27 formed on the first layer/l wiring 25, a resistance layer, a wiring layer, etc. By forming a convex pattern such as the convex Si pattern 37 formed at the same time, the height of this area can be made higher than the surrounding area, and when flattening is performed by applying the SOG layer, this area is Is it mostly SOG? can be prevented from forming.

Even if a small amount of SOG layer is formed in this region for some reason, the SOG layer can be easily and completely removed by light etching of the entire surface.

Therefore, in the contact hole, the upper layer Al wiring no longer comes into contact with the SOG layer, and the upper layer Al wiring in the contact hole becomes coarse grained due to degassing from the SOG layer, resulting in poor contact with the lower layer A/2 wiring. This eliminates the occurrence of wire breakage and disconnection, and prevents deterioration in the characteristics and reliability of the semiconductor device caused by these.

In the above embodiment, an island-like oxide film pattern and a CVD-S film were formed simultaneously with the field oxide film on the convex-shaped layer provided in the area where the 11-An contact hole was to be formed.
Although the in2 film pattern and the wavy Si pattern are used, the invention is not limited to these. For example, instead of the CVD-Sin2 film pattern, a sputtered SiO2 film pattern, a SiN film pattern, and a SiON'fi! film pattern are used. WSiz (tungsten silicide), MoSiz (molybdenum silicide) on the polySi layer instead of the polySt pattern.
, TiSiz (titanium silicide), etc. may be used as long as it has a convex shape.

In addition, in the above embodiments, pure Affi or Affi-1%Si alloy was used as the wiring material, but the present invention also applies when using Af-St-Cu alloy or A/2-Cu alloy as the wiring material. It is also effective when using Cu or high melting point metals.

Furthermore, although the above embodiments have been described in the case of a MOS type semiconductor device, the present invention is not limited to the above, but can be applied to any device having a multilayer wiring structure in which planarization is performed using an SOG layer.
This applies to all semiconductor device manufacturing methods.

[Effects of the Invention] As explained above, according to the present invention, a convex pattern is formed in advance in the area where the contact hole is to be formed on the first layer wiring to increase the height of this area, and then the SOG layer is applied. When planarizing the second layer wiring formation surface, SOG is applied to the above area.
By preventing the layer from being formed, the sidewall of the SOG layer is prevented from being exposed on the side surface of a contact hole to be formed there, thereby making it possible to eliminate contact failure due to outgassing from the SOG layer.

Therefore, the characteristics of the semiconductor device are improved and at the same time the reliability is improved.

[Brief explanation of drawings]

1(a) to (g) are process sectional views of the first embodiment of the present invention; FIGS. 2(a) to (f) are process sectional views of the second embodiment of the present invention; The figure is a schematic plan view of a semiconductor device manufactured according to the second embodiment, FIGS. 4(a) to (h) are process cross-sectional views of the third embodiment of the present invention, and FIG. 5 is the third embodiment. A schematic plan view of a semiconductor device manufactured in accordance with the example, FIGS. 21 is a p-type Si substrate and a semiconductor substrate, 2 is an element formation region, 3 is a field oxide film, 3S is an island-shaped oxide film pattern, 4, 22 are gate oxide films, 5, 23A, 23B are gate electrodes, 6a, 6b is an n-type source region, 7 is an n-type drain region, 8 is an oxide film for impurity blocking, 9 and 24 are lower insulating films, 10S is a source contact hole (SC), and 100 is a drain contact hole (DC) , U is /l source wiring, 12 is Al drain wiring, 13 is first first layer Al wiring, 14 is second first layer Al wiring, 15 and 29 are CVD-Stag films, 16 and 30 are SOG layers, 17 and 31 are PSG layers 18, 33 are contact holes (between wiring layers), 19,
34 is a second layer Affi wiring 25 is a first layer Af wiring, 26, 28, 32, 35 are resists, 27 is a CVD-St (h film pattern, 36 is a poly-Si layer, 37 is a poly-Si pattern, 38 is an interlayer Insulating film, 125 indicates 1st layer wiring / 1st layer. Ga 2's Fruitful Ikuj's D's Young Face Concave Part 2
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Claims (4)

[Claims] (1) A method for manufacturing a semiconductor device in which unevenness on a first wiring layer is flattened by applying a spin-on glass layer, and then a second wiring layer is formed via an interlayer insulating film, the spin-on glass layer Before coating the contact hole formation area on the first wiring layer, a convex layer is used to form the contact hole formation area higher than the surrounding area in advance to make it difficult for the spin-on glass layer to be applied to the contact hole formation area. 1. A method of manufacturing a semiconductor device, the method comprising the steps of: (2) The method for manufacturing a semiconductor device according to claim 1, wherein the convex layer is formed of an island-shaped insulating film pattern formed simultaneously with a field insulating film that isolates elements. (3) The method for manufacturing a semiconductor device according to claim (1), wherein the convex layer is formed of an island-shaped insulating film pattern formed on top of the first wiring. (4) The method of manufacturing a semiconductor device according to claim 1, wherein the convex layer is formed of a conductive film pattern formed under the first wiring via an insulating film.