JPH03160796A - Mounting method for electronic component - Google Patents
Mounting method for electronic componentInfo
- Publication number
- JPH03160796A JPH03160796A JP1300598A JP30059889A JPH03160796A JP H03160796 A JPH03160796 A JP H03160796A JP 1300598 A JP1300598 A JP 1300598A JP 30059889 A JP30059889 A JP 30059889A JP H03160796 A JPH03160796 A JP H03160796A
- Authority
- JP
- Japan
- Prior art keywords
- terminals
- frame
- memory
- terminal
- electronic component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 description 5
- 230000007257 malfunction Effects 0.000 description 3
- 101100514842 Xenopus laevis mtus1 gene Proteins 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 210000000078 claw Anatomy 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
Abstract
Description
【発明の詳細な説明】
く産業上の利用分野〉
この発明は、本体の周囲に横方向に突出した端子を複数
個備えた7ラット・パッケーノ型やこれに類する形状の
電子部品を積層して実装する方法に関する。[Detailed Description of the Invention] Industrial Application Fields The present invention is directed to a device in which electronic components having a 7-latt Paceno type or a similar shape having a plurality of terminals protruding laterally around the main body are laminated. Regarding how to implement.
く従米の技術〉
第3図は複数個のメモリーICを用いたメモリー回路の
一例を示したものである。21u〜21dはメモリーI
C,22はデータパス、23はアドレスバス、24はC
PU,25はメモリーセレクト回路、26a −26c
lはセレクト端子であり、セレクト信号によって任意の
メモリーICを選択し、データの入出力を個別に行う回
路になっている。Advanced technology> Figure 3 shows an example of a memory circuit using multiple memory ICs. 21u to 21d are memory I
C, 22 is a data path, 23 is an address bus, 24 is C
PU, 25 is a memory select circuit, 26a - 26c
1 is a select terminal, which is a circuit that selects an arbitrary memory IC by a select signal and inputs and outputs data individually.
m4図はこのような回路を構或する場合の従米の接続方
法であり、各メモリーIC21a〜21dのデータ端子
とアドレス端子及びコントロール端子は互いに対応する
同一番号の端子同士間を相互に接続することによりデー
タバス22及びアドレスバス23、あるいはコントロー
ル回路27を通じてCPU24に一括して接絞し、セレ
クト端7−26a〜26dはそれぞれ独立にメモリーセ
レクト回路25に接続し、メモリーセレクト回路25を
アドレスバス23に接続してCPU24で制御するよう
にしてある。Figure m4 shows the typical connection method when constructing such a circuit, and the data terminals, address terminals, and control terminals of each memory IC 21a to 21d should be connected to each other by connecting terminals with the same number that correspond to each other. The data bus 22 and the address bus 23 or the control circuit 27 are connected to the CPU 24 at once, and the select terminals 7-26a to 26d are each independently connected to the memory select circuit 25, and the memory select circuit 25 is connected to the address bus 23. It is connected to and controlled by the CPU 24.
〈発明が角イ決しようとする課題〉
第4図のような接続方注では、プリント基板に犬装する
際に各メモリーI C21a〜21tJを横に拒べて各
端子を所定のパターンに接続する必要があるため、パタ
ーンの全艮が艮くなってノイズを拾ったり、誤動作を起
こしたりすることが多くなり、まr二犬装に要する面積
が火さくなるという問題があった。<Problem to be solved by the invention> In the connection method as shown in Fig. 4, each memory IC21a to 21tJ can be separated horizontally and each terminal connected in a predetermined pattern when mounted on a printed circuit board. As a result, all the parts of the pattern become red, which often picks up noise and causes malfunctions, and the area required for the two-dog arrangement becomes too large.
この発明はこれらのIfjl題,−4に訂目し、パター
ンの全艮を短くし、しかも小さな而植で所要数の電′F
一部品を実装できるようにすることを目的としてなされ
たものである。This invention abbreviates these Ifjl titles, -4, shortens all the patterns of the pattern, and moreover, allows the required number of elec-
This was done for the purpose of making it possible to implement one part.
く課題を解決するための手段〉
この発明では、本体の周囲に横方向に突出した端子を複
数個備えた形状の電子部品を積層して実装することを対
象としており、上述の目的を達威するために、電子部品
の本体が収納されるスペースとこのスペースの周囲に電
子部品の端子が載置される枠状部とを備え、電子部品の
特定の端子に対応する導電性パターンを上記枠状部の少
なくとも片面に形戊すると共に外周より突出させて外部
接続端子とし、他の各端子に対応する導電性パターンを
」二記枠状部の表裏両面にそれぞれ形成して相互間をス
ルーホールで接続した構造の補助基板を用いるようにし
ている。そして実装に際しては、この補助基板と電子部
品とを交互に複数個積ねてホルダーにより圧接した状態
で一体化することに上り、各’Ki1一部品の特定の端
子はそれぞれ独立し、またit応ずる他の各端子同士は
相互に接続された状態で複数個の電子部品を8lt層す
るのである。Means for Solving the Problems The present invention is directed to stacking and mounting electronic components having a plurality of terminals protruding laterally around the periphery of a main body, and achieves the above-mentioned objects. In order to do this, the main body of the electronic component is housed in a space, and the terminal of the electronic component is placed around this space. A conductive pattern corresponding to each other terminal is formed on at least one side of the frame-shaped part and protruded from the outer periphery to serve as an external connection terminal, and conductive patterns corresponding to the other terminals are formed on both the front and back sides of the frame-shaped part and through holes are formed between them. We are trying to use an auxiliary board with a structure connected by . When mounting, a plurality of these auxiliary boards and electronic components are stacked alternately and integrated in a state in which they are pressed together with a holder, and the specific terminals of each 'Ki1 component are independent, and depending on the IT. The other terminals are connected to each other and a plurality of electronic components are stacked in 8lt layers.
く作用〉
各電子部品の特定の端子はそれぞれ独立した状態となっ
ているので、侶Wの人出力はそれぞれ独立して行なわれ
、池の各端子については、対応する各端子同上が相瓦に
一括して並列に接続され、同一の信号を同時に人出力す
ることが可能な接続となっている。また電子部品を積層
しているので電子部品の個数が増えても実装面積は増加
しない。Since the specific terminals of each electronic component are in an independent state, the human output of the member W is performed independently, and for each terminal of the pond, each corresponding terminal is They are all connected in parallel, making it possible to output the same signal at the same time. Furthermore, since the electronic components are stacked, the mounting area does not increase even if the number of electronic components increases.
従って、前述の第3図のようなメモリー回路を構或する
場合、メモリーICのセレクト端子を特定の端子として
この部分を外部接続端子とすれば、一定の実装面積のま
までメモ+7 − I Cの実装数を任意に増滅してメ
モリー容量を適宜変化させることが容易となるのである
。Therefore, when configuring a memory circuit as shown in Figure 3 above, if the select terminal of the memory IC is designated as a specific terminal and this part is used as an external connection terminal, the memory IC can be connected to a memory circuit with a fixed mounting area. This makes it easy to arbitrarily increase or decrease the number of implementations and change the memory capacity as appropriate.
〈実施例〉
次に、図示の一実施例について説明する。f:lS1図
はこの発明によって電子部品を実装した状態の断面図、
第2図は積層に用いる補助基板の斜視図である。<Example> Next, an illustrated example will be described. Figure f:lS1 is a cross-sectional view of a state in which electronic components are mounted according to the present invention,
FIG. 2 is a perspective view of an auxiliary substrate used for lamination.
図において、1はメモリーIC,2は補助基板、3はメ
モリーICIが実装されるプリント基板、4はホルダー
である。メモリーICIは本体5のVdU’rに横方向
に突出した端子6a及び複数個の6bを備えた形状のも
のである.また補助基板2はメモリーICIの本体5に
対応した大きさと形状のスペース7と、このスペース7
を囲む枠状部8とを備えており、この枠状部8にはメモ
リーIC1の全部の端子にそれぞれ対応させて導電性パ
ターン9を形成してあるが、メモリーICIのセレクト
端子6aに対応する導電性パターン9は表面のみに設け
、且つ枠状部8の外周よりパターンと基板とを若干突出
させて外部接続端子10としてある。In the figure, 1 is a memory IC, 2 is an auxiliary board, 3 is a printed circuit board on which the memory ICI is mounted, and 4 is a holder. The memory ICI has a shape that includes a terminal 6a and a plurality of terminals 6b that protrude laterally from VdU'r of the main body 5. The auxiliary board 2 also has a space 7 of a size and shape corresponding to the main body 5 of the memory ICI, and this space 7.
The conductive pattern 9 is formed in the frame part 8 to correspond to all the terminals of the memory IC 1, and the conductive patterns 9 correspond to the select terminals 6a of the memory IC 1. The conductive pattern 9 is provided only on the surface, and the pattern and the substrate are slightly protruded from the outer periphery of the frame portion 8 to form an external connection terminal 10.
また他の各端子6bに対応する導電性パターン9は枠状
部8の表裏両面に形成して相互間をスルーホール11で
接続した構造となっている。なお、プリント基板3の表
面のメモリーICIが実装される位置には、端子配列に
応じて導電性パターン12a及び12bが形成してある
。Further, conductive patterns 9 corresponding to the other terminals 6b are formed on both the front and back surfaces of the frame portion 8 and are connected to each other by through holes 11. Note that conductive patterns 12a and 12b are formed on the surface of the printed circuit board 3 at positions where the memory ICI is mounted in accordance with the terminal arrangement.
メモリーICIの実装の際には、まずプリント基板3の
所定の位置に第1のメモ+7 − I C 1を置き、
その上に袖助基板2を所定の向きに置(1でメモ+7
− I C 1の各端子6a.6b上に補助基板2の枠
状部8を重h 7+.この時、メモ+7 − I C
1の本体5は補助基板2のスペース7内に位置し、補助
基板2との開に干渉は生じない。更に、この上にPtS
2のメモリーICIを置き、その上に別の補助基板2を
重わるというように、所定個数のメモリ−ICIと補助
基板2を交互に重わ、最後にホルダー4を全体を加圧す
る状態でプリント基板3に固定するのである。これによ
り、各メモリーIC1のセレクト端子6aはそれぞれ側
方に突出した外部按続端子10に接続された状態となり
、これ以外の各端子−6bは辱電性パターン9とスルー
ホール11を介して対応するもの同士がそれぞれ圧接さ
れてHEいに接続された状態となる。When mounting the memory ICI, first place the first memo +7-IC1 at a predetermined position on the printed circuit board 3,
Place the Sodesuke board 2 on top of it in the specified direction (note +7 at 1).
- Each terminal 6a of IC1. Place the frame portion 8 of the auxiliary board 2 on top of the 6b. At this time, memo +7 - IC
1's main body 5 is located within the space 7 of the auxiliary board 2 and does not interfere with the opening of the auxiliary board 2. Furthermore, on top of this, PtS
A predetermined number of memory ICIs and the auxiliary board 2 are stacked alternately, such as placing 2 memory ICIs and another auxiliary board 2 on top of it.Finally, the holder 4 is printed while pressurizing the entire holder 4. It is fixed to the substrate 3. As a result, the select terminals 6a of each memory IC 1 are connected to the external connection terminals 10 protruding laterally, and the other terminals 6b are connected to each other via the electrostatic pattern 9 and the through hole 11. The two parts are pressed against each other and are connected to each other.
従って、各メモリーICIの端子6bはそれぞれプリン
ト7&板3の所定の導電性パターン12L+に接1&さ
れ、例えば第3図におけるデータバス22あるいはアド
レスバス23への接続を一括して行うことが可能となる
。また最も下のtPJ1のメモリーIC1のセレクト端
子6aはプリント基板3の導電性パターン12uに接l
&されており、更に他のメモリーICIのセレクト端−
f−Gaはそれぞれ各外部接続端子10にリード線13
を配線することによって、導電性パターン12aまたは
リード#i13を介して第3図におけるメモリーセレク
ト回路25への接続を個別に行い、メモリーICIを選
択するセレクト信号を個々のメモリーICIに独立して
送ることができるのである。Therefore, the terminals 6b of each memory ICI are connected to the printed circuit board 7 and the predetermined conductive pattern 12L+ of the board 3, and for example, connection to the data bus 22 or address bus 23 in FIG. 3 can be made all at once. Become. In addition, the select terminal 6a of the memory IC1 of the lowest tPJ1 is in contact with the conductive pattern 12u of the printed circuit board 3.
&, and the select end of other memory ICI -
f-Ga has a lead wire 13 to each external connection terminal 10.
By wiring, the connection to the memory select circuit 25 in FIG. 3 is made individually via the conductive pattern 12a or lead #i13, and the select signal for selecting the memory ICI is sent to each memory ICI independently. It is possible.
なお、ホルグー4はメモリーICIの固定だけでなく、
その外部を覆って保護あるいは補強する作用も発揮jる
ものである、プリント基板3へのホルダー4の固定は、
例えばホルダー4の爪14をプリント基板3の係止穴1
5に挿入して基板3に係I卜することによって行われる
。また第1図では最Iユ部のメモリー■C1の本体5を
ホルグー4で押さえているが、本体5と共に端子部を押
さえ、あるいは端子部のみを押さえるようにしてもよく
、ホルダー4の形状や大きさはt=t東となる電子部品
の端子部の形状や積層個数などに応じて適宜選定すれば
よい。In addition, the Holgu 4 is not only capable of fixing the memory ICI.
The fixing of the holder 4 to the printed circuit board 3, which also has the effect of covering and protecting or reinforcing the outside, is as follows:
For example, connect the claw 14 of the holder 4 to the locking hole 1 of the printed circuit board 3.
This is done by inserting it into the substrate 5 and attaching it to the substrate 3. In addition, in FIG. 1, the main body 5 of the memory C1 in the most I unit part is held down by the holder 4, but the terminal part may be held together with the main body 5, or only the terminal part may be held down, depending on the shape of the holder 4. The size may be appropriately selected depending on the shape of the terminal portion of the electronic component where t=t east, the number of stacked parts, etc.
〈発明の効果〉
上述の実施例から明らかなように、この発明は、電了部
品の本体が収納されるスペースの周囲に電了部IW+の
端子が載置される枠状部を備えており、この枠状部に電
子部品の各端子に対応する導電性パターンを形成した構
造の補助基板を用い、この補助基板と電子部品とを交互
に複数個積ねてホルダーにより圧接した状態で一体化す
るようにしたものである。<Effects of the Invention> As is clear from the above-mentioned embodiments, the present invention includes a frame portion around a space in which the main body of the power-on part is housed, on which the terminal of the power-on part IW+ is placed. Using an auxiliary board with a structure in which a conductive pattern corresponding to each terminal of the electronic component is formed on this frame-shaped part, the auxiliary board and electronic components are stacked alternately and integrated by being pressed together with a holder. It was designed to do so.
従って、複数個の同一形状の電子部品を積層し、個別に
配線されるべき特定の端子をそれぞれ独立させ、また一
括して配線されるべき各端子.同士を相亙に按続させた
状態で実装することが可能となり、複数個の電子部品の
実装を比較的簡単に行うことができると共に、接続のた
めのパターンの全長を短くしてノイズを拾ったり、誤動
作を起こしたりすることをなくし、またほぼ電子部品1
個分の実装面積で任意の個数の電子部品を実装すること
が可能となって、電子回路の小形化が容易となる等の効
果が得られる。Therefore, by stacking a plurality of electronic components of the same shape, specific terminals that should be wired individually can be made independent, and terminals that should be wired all at once. It is now possible to mount multiple electronic components in a state where they are connected to each other, making it relatively easy to mount multiple electronic components, and reducing the overall length of the connection pattern to reduce noise pickup. This eliminates the possibility of malfunctions or malfunctions, and almost eliminates the need for electronic components.
It becomes possible to mount an arbitrary number of electronic components in a mounting area of 1,000 yen, which facilitates miniaturization of electronic circuits.
PttJ1図は、この発明の一実施例よって電子部品を
実装した状態の断面図、
第2図は、積層に用いる補助基板の斜視図、第3図は、
複数個のメモリーICを用いたメモリー回路の一例のブ
ロック結#iI図、第4図は、第3図の回路を構威する
場合の従米の接絞方法を示す結線図である。
1・・・メモリーIC ,
3・・・プリント基板 、
5・・・本体
7・・・スペース
9・・・導電性パターン、
11・・・スルーホール
2・・・補助基板
4・・・ホルダー
6a,6b・・・端子
8・・・枠状部
10・・・外部接続端子Figure PttJ1 is a cross-sectional view of a state in which electronic components are mounted according to an embodiment of the present invention, Figure 2 is a perspective view of an auxiliary board used for lamination, and Figure 3 is a
FIG. 4, a block diagram of an example of a memory circuit using a plurality of memory ICs, is a wiring diagram showing a method of close contact when the circuit of FIG. 3 is used. DESCRIPTION OF SYMBOLS 1... Memory IC, 3... Printed circuit board, 5... Main body 7... Space 9... Conductive pattern, 11... Through hole 2... Auxiliary board 4... Holder 6a , 6b...Terminal 8...Frame-shaped part 10...External connection terminal
Claims (1)
形状の電子部品を積層して実装する方法であって、電子
部品の本体が収納されるスペースとこのスペースの周囲
に電子部品の端子が載置される枠状部とを備え、電子部
品の特定の端子に対応する導電性パターンを上記枠状部
の少なくとも片面に形成すると共に外周より突出させて
外部接続端子とし、他の各端子に対応する導電性パター
ンを上記枠状部の表裏両面にそれぞれ形成して相互間を
スルーホールで接続した構造の補助基板を用い、この補
助基板と電子部品とを交互に複数個積ねてホルダーによ
り圧接した状態で一体化することにより、各電子部品の
特定の端子はそれぞれ独立し、また対応する他の各端子
同士は相互に接続された状態で複数個の電子部品を積層
することを特徴とする電子部品の実装方法。1. A method of stacking and mounting electronic components each having a shape that includes a plurality of terminals protruding laterally around the main body. A conductive pattern corresponding to a specific terminal of the electronic component is formed on at least one side of the frame-like part and protrudes from the outer periphery to serve as an external connection terminal, and a conductive pattern corresponding to a specific terminal of the electronic component is formed on at least one side of the frame-like part and protrudes from the outer periphery to serve as an external connection terminal. Using an auxiliary board with a structure in which corresponding conductive patterns are formed on both the front and back sides of the frame-shaped part and connected to each other through through holes, a plurality of these auxiliary boards and electronic components are stacked alternately and placed in a holder. It is characterized by stacking a plurality of electronic components by integrating them in a pressure-welded state, so that specific terminals of each electronic component become independent, and other corresponding terminals are connected to each other. How to mount electronic components.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1300598A JPH07105628B2 (en) | 1989-11-18 | 1989-11-18 | Electronic component mounting method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1300598A JPH07105628B2 (en) | 1989-11-18 | 1989-11-18 | Electronic component mounting method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH03160796A true JPH03160796A (en) | 1991-07-10 |
JPH07105628B2 JPH07105628B2 (en) | 1995-11-13 |
Family
ID=17886776
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1300598A Expired - Fee Related JPH07105628B2 (en) | 1989-11-18 | 1989-11-18 | Electronic component mounting method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07105628B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5346402A (en) * | 1992-03-09 | 1994-09-13 | Matsushita Electric Industrial Co., Ltd. | Electronic circuit device and manufacturing method thereof |
-
1989
- 1989-11-18 JP JP1300598A patent/JPH07105628B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5346402A (en) * | 1992-03-09 | 1994-09-13 | Matsushita Electric Industrial Co., Ltd. | Electronic circuit device and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
JPH07105628B2 (en) | 1995-11-13 |
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