JPH03157890A - Fifo memory - Google Patents

Abstract

PURPOSE:To obtain a FIFO memory whose memory area is small by dividing the time of writing to or reading from a storage means and performing the recording and writing operation. CONSTITUTION:A single-port SRAM 10 where a memory cell consists of six transistors (TR) is used as the storage means stored with data and a selector 4 alternates signals having specific period for reading and writing with a selecting signal CK which selects the writing and reading operation. Then when the selecting signal CK is in the reading period, an H signal is supplied to a tri-state buffer 12, but when the selecting signal is in the writing period, an L signal is supplied. Thus, the FIFO memory is constituted of the single-port memory, so the area of the memory cell is reduced and the large-capacity memory with small chip area is obtained.

Description

[Detailed description of the invention] (b) Industrial application fields FIELD OF THE INVENTION The present invention relates to FIFO memory.

(b) Prior Art FIG. 4 is a block diagram showing the structure of a conventional FIFO memory. In the FIFO memory, a dual port memory (41) is used as a memory cell, and this memory (41)
Input data bus (42) for inputting data to be written to
An output data bus (43) for outputting continuously transmitted data is connected. The memory (41) is configured such that address data is supplied from a write address counter (44) and a read address counter (45), respectively.

FIG. 5 is a circuit diagram showing memory cells of a double FIFO memory. This memory cell is static RAM
(hereinafter referred to as SRAM), and consists of a pair of inverters (1) (2) and two sets of 1-run inverters (3) (4) (5) (6). Inverter (
1) and (2) are composed of four transistors when formed using a CMOS cell or an nMOS cell. Therefore, the above memory cell is composed of six transistors7 and furthermore,
As a write bit line (b+) (b+)
, a read bit line (bz) (b2), a write word line (Il+), and a read word line (W2).

By the way, a normal 6-transistor SRAM is
As shown in the figure, the two inverters (1) and (2) include four transistors and two gate transistors (
3) (4) and a pair of bit lines (b,) (b,
) and -word lines (W, ).

(c) Problems to be Solved by the Invention The FIFO memory described above has the problem that it requires more transistors and more pin lines for each memory cell than SRAM, and the memory area is very large. .

FIFO memory is also used as a data buffer memory for communication.It is also built into LSI.In particular,
When built into an LSI, as mentioned above, the memory cell has a large number of transistors, and also has a bit line and word line for reading and writing, so as the memory capacity increases, There is a problem in that the area occupied by the FIFO memory becomes very large.

The present invention was made in view of the above-mentioned problems, and an object of the present invention is to provide a FIFO memory with a small memory area.

(d) Means for Solving the Problems The present invention provides a storage means for storing data, an input data bus for supplying data to be written to the storage means, and an output data bus for outputting data read from the storage means. and Goo 1 that controls the input to the storage means of the input data bus.
- means, a write address counter for specifying a write address, a read address counter for specifying a read address, and read and write addresses of both address counters are alternately selected and supplied as addresses of the storage means; It also includes a selection means for opening the gate means during a period when a write address is selected.

(E) Effect The selection means time-divides the reading or writing period to the storage + stage, and reading and writing are performed.

(F) Embodiments Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 3.

FIG. 1 is a block diagram showing the main parts of the present invention, FIG. 2 is a block diagram showing the configuration of the present invention, and FIG. 3 is a timing chart diagram of FIG. 2.7 In FIG. 1, data is stored. In this embodiment, the memory cell is a single-boat SRAM (SRAM) consisting of six transistors.
lO) is used. An input data bus (11) for writing data into this SRAM (10) is connected to a get means (12).
) to the bus (13) of the SRAM (10). In this embodiment, the gate means (12) is composed of a 3-state buffer, and when a selection signal (CK) output from a selector (14) to be described later is H, the gate means (12) is input to the 3-state buffer (12). is inverted at the input section and the same input is made, and the 3-state buffer (12) becomes 'ON'.Then, the data from the input data bus (11) is input to the bus (13), and the SRAM ( to).

On the other hand, the selection signal (CK
) becomes "°L", the 3rd date buffer (12) is inverted 1- at the input section, "H" is input, and 3
The stay l-buffer (12) is turned 'OFF'. Data is then transferred from the input data bus (11) to the bus (13).
) is not entered.

The selector (14) alternately repeats signals for a predetermined period for reading and writing in response to a selection signal (CK) for selecting writing and reading.

Then, if (CK) is within the read period,
The ``I('' signal is applied to the third date buffer (12), and the ``BI'' signal is applied during the write period.

A write address counter (hereinafter referred to as W counter) that specifies the write address of SRAM (10) (
15) is composed of an up counter in this embodiment. There is also a read address counter (hereinafter referred to as R counter) that specifies the read address of the SRAM (10) (
16) is similarly composed of an up counter. Address signals are applied to both address counters (15) and (16) via a latch (17), and data written first is read out.

When inputting the first data when the write period is selected with the selector (14), W
An address signal is given from the counter (15) to, for example, address O of the SRAM (10), and the 3rd buffer (12)
First write data is input from the input data bus (11) via the input data bus (11).

Then, for the next write, the W counter (15) is incremented by 1, and for the next write, the SRAM
Address 1 of (10) is designated at 1nos.

Furthermore, when the read period is selected by the selector (14), the R counter (16) first specifies the address 0 of the SRAM (lO), and the data written/written to 1 at this address,
In other words, the data written first is transferred to the output data bus (
18). Then, for the next readout, the R counter (16) increments one hair, and next, address designation of address 1 is specified.

On the other hand, since the 3-state buffer (12) is closed during the read period, no input is made from the input data bus (11).

Next, the present invention will be further explained with reference to FIGS. 2 and 3.

As shown in FIG. 3, the selection signal (CK) is given with one cycle consisting of a read period (R) and a write period (W). This selection signal (CK) is supplied to the selector (14)6.Furthermore, a read signal (π) and a write signal (Wl) are respectively input. 7; 1) When the flip-flops (20) and (23) are reset or reset, the first and third flip-flops (20) and (23) are ) are the first and second
The signal (Wl) is set by the rise or fall of the aforementioned selection signal (CK), and the internal write signal (
W″I(2) is formed.

Historically, the write signal (Wl) is input to the CK terminal of a flip-flop (24) serving as a buffer of the input data bus (11) for write data.

Then, at the rising edge of WR, write data is input from the flip-flop (24) to the 3-state buffer (12) as gate means. This 3-state buffer (12) is opened only when the selection signal (CK) is written, that is, when it is high, the write data passes through the bus, and the SR
It is written to a predetermined location of AM (10).

The internal write data E; (WR2) is input to the fifth solve flop (25). The selection (8 bows (CK)) is input to the CK terminal of the fifth foot flop (25) via the inverter (26).

The output from the Q terminal of the fifth flip-flop (25), the internal write signal (Wll, ) and the selection signal (CK
) is input to the NAND circuit (27), a write enable signal (WE) is output from this NAND circuit (27), and the CK terminal of the W counter (15) and the SRAM (10
) is applied to the WE terminal.

On the other hand, the read signal (RD) is input to the third and fourth flip-flops (22) and (23), respectively, and when the read signal (RD) becomes l or ' for reading, the selection signal (CK) The internal read signal (WR,) is set to CK of the R counter (16).
input to the terminal.

In addition, data from the SRAM (10) addressed by the R counter (16) is sent from the SRAM (10)'s board t□ (Data) terminal to the foot-flop (28) as an output buffer via the bus (13). A pig is entered.

The CK terminal of the flip-flop (28) has a selection signal of 0. The number (CK) is! j - can be obtained.

Read data (R1) from flip-flop (28)
) is a flip-flop (29
) is entered. CK of this flip-flop (29)
At the end, the read signal (RD) is connected to the inverter (31).
Input via . And this solve flop (
The output (R2) of 29) is input to a 3-state buffer (30) into which the read signal (Wl) is input, and data (Dat, a) is output from this output terminal.

The outputs of both the R counter (R6) and the W counter (15) are input to the selector (14), and a selection signal (CK
), the selector (14) reads the address end of the SRAM (10) as RA Sagiato 1.
) and write (Write), respectively, are supplied with outputs from address counters (15) and (16).

Note that the above-mentioned write signal (RD) and read signal (W
The pulse 11] of l) requires at least 1 to 1 or more of the selection signal (CK).

Now, in the FIFO memory of the present invention described above, after the reset signal, the write relay (RI) and the read ray No. 3 are simultaneously 5P! [In case of
This will be explained according to the diagram.

From Noset I-Nobuyumi, R counter (l[i),
The W counter (15) is reset, and each At1nos designation signal (indicates address jO) is inputted to the selector (14).

The selection signal (CK) is supplied with R and W as -cycles. In response to this signal CK, the RAM address is alternately supplied with Read O, which does not indicate reading of address 0, and the address of W port teO, which indicates writing of address 0.

On the other hand, the data written at address C) is read out to the flip-flop (28), and this data is held in the flip-flop (29).

Since the read signal (RD) is input from the impark (31) to the flip-flop (29), when the read signal (Wl) falls, the flip-flop (
29) The data at hair address ○ is read, and the 3-state buffer (30) is turned on.
' and the data at address ○ is output.

In addition, a read signal (RD) and a write signal (W r
t ) occurs, the firing i [i.e., RD,
After the fall of WR, the internal read and write signals (WR2) (RD2) fall from [1 to 1] due to the next rising or falling of the CK multiplier signal.

Then, the next CK multiplication signal rises and -η falls, that is, (WR2) for a period corresponding to one cycle of the CK multiplication signal.
(RD,) signal is formed. This internal read signal (
RD2) is input to Rka Kunta (1G), and the R counter (16) is incremented by 1 due to the increment of 1, and the next address to be directed to becomes address 1.

The write data is supplied to the flip-flop block (24), and at the rising edge of the write signal (Wl), data is supplied to the 3rd batcher (12).The 73rd batcher (12) receives the RAM enable signal (W E) is supplied, and unless this signal becomes L',
Remains in 'OFF' state.

As described above, the internal write signal (WR2) is generated from the write signal (Wl). This internal write signal (WR2) is input to the flip-flop (25), and the CK signal of this flip-flop (25) is input to the flip-flop (25).
Since the selection signal (CK) is input to the terminal, the second internal write signal (W
R,) is formed. This internal write signal (WRs)
, an internal write signal (WR2) and a selection signal (CK) are supplied to the NAND circuit (27).
) to write enable signal (WE) from SRAM (10
) and a third date buffer (12). This write enable signal (W E) is synchronized with the Read cycle of the selection signal (CK), so even if reading and writing of data occur simultaneously, S R is sent only during writing.
It becomes possible to write to AM34 (10). Then, due to the fall of the enable signal q (w h ) to lie 1, 3 sj
---I-Buffer 1-(12) is turned ON and the input r-Y is written from the bus to SRAM (10). Continued -C, write -f'+-pull signal (W E )
When 1 is raised, the W card notch (15) is incremented.

As shown in FIG.
By internally performing time-sharing processing, writing and reading are performed sequentially, making it appear as if reading and writing can be performed simultaneously.

Incidentally, in the embodiment described above, SRAM may be used as the storage/use means for i5, and dynamic RAM may be used for l:2. (5>t, in this case, the circuit that generates the riff L knot, etc. becomes 7 different.

(1-) Effects of the Invention As explained above, in the present invention, the FIFO memo can be configured with the memory of the memory board.
The area of the memory cell is reduced, and a memory with a large capacity can be provided with a small chip area.

[Brief explanation of the drawing]

Fig. 1 is a four-block diagram showing the main parts of the present invention, Fig. 2 is a block diagram showing the configuration of the invention, and Fig. 4 is a timing chart of Fig. 2. Figure 5 is a circuit diagram showing a conventional FIFO memory cell, and Figure 6 is a circuit diagram showing a 61-transistor SRAM. 10...SRAM, 11. Input data bus, 12
... 3 dates butshua (gu 1-means), 14...
・Selector, 15・W counter, 16...R counter.

Claims (1)

[Claims] (1) A storage means for storing data, an input data bus for supplying data to be written into the storage means, an output data bus for outputting data read from the storage means, and an input data bus for inputting the input data bus to the storage means. a gate means for controlling; a write address counter for specifying a write address; a read address counter for specifying a read address; alternately selecting read and write addresses of both address counters and supplying them as addresses to the storage means; A FIF comprising: a selector that opens the gate means during a period in which a write address is selected, and reads and writes to the storage means by time-sharing the read or write period.
O memory.