JPH03154346A - Gettering - Google Patents

Gettering

Info

Publication number
JPH03154346A
JPH03154346A JP29222389A JP29222389A JPH03154346A JP H03154346 A JPH03154346 A JP H03154346A JP 29222389 A JP29222389 A JP 29222389A JP 29222389 A JP29222389 A JP 29222389A JP H03154346 A JPH03154346 A JP H03154346A
Authority
JP
Japan
Prior art keywords
heavy metal
locos
semiconductor substrate
periphery
accumulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29222389A
Other languages
Japanese (ja)
Inventor
Masaki Aoki
正樹 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP29222389A priority Critical patent/JPH03154346A/en
Publication of JPH03154346A publication Critical patent/JPH03154346A/en
Pending legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To prevent contaminants of a heavy metal from accumulating to the field of a distortion at the periphery of LOCOS by forming an element isolation region on a semiconductor substrate by means of selective oxidation and allowing impurities of the heavy metal to be absorbed into the internal imperfect layer of the semiconductor substrate by performing heat treatment. CONSTITUTION:Intrinsic gettering(IG) heat treatment is performed for a silicon wafer 1 and an internal imperfect layer 2 is formed. Then, a prescribed position is thermally oxidized so as to form a device region and a field oxide film 3 is formed. While heat treatment (annealing with N2) is performed in an atmosphere of nitrogen (N2), annealing with N2 makes N2 4 accumulate to an interface of SiO2/Si, i.e., the periphery of local oxidation of silicon (LOCOS). This prevents a heavy metal to be mixed in a device process afterwards from accumulating to the periphery of LOCOS and its metal is absorbed into an IG layer 2. This approach prevents contaminants of the heavy metal in a semiconductor device process from accumulating to the field of a distortion at the periphery of LOCOS.

Description

【発明の詳細な説明】 〔概 要〕 ゲッタリング方法に係り、特に半導体デバイスの製造に
おいて重金属不純物をLOGO5(Local 0xi
da−tion of 5ilicon)の周辺に集積
するのを防止するゲッタリング方法に関し、 LOCO3の周辺の歪み場に半導体デバイスプロセス中
の重金属汚染が集積するのを防止し、半導体ウェハーの
内部欠陥層に吸収することを目的とし、半導体基板上に
選択酸化により素子分離領域を形成する工程、 窒素あるいは水素雰囲気中で該半導体基板を熱処理する
ことによって、該半導体基板内に混入した重金属不純物
が前記素子分離領域周辺に集積するのを抑制して該半導
体基板の内部欠陥層に該重金属不純物を吸収する工程、
を含むことを構成とする。
[Detailed Description of the Invention] [Summary] It relates to a gettering method, particularly in the production of semiconductor devices, in which heavy metal impurities are removed by LOGO5 (Local 0xi).
Regarding a gettering method that prevents heavy metal contamination during semiconductor device processing from accumulating in the strain field around the LOCO3 and absorbing it into the internal defect layer of the semiconductor wafer. A step of forming an element isolation region on a semiconductor substrate by selective oxidation with the aim of absorbing the heavy metal impurities into the internal defect layer of the semiconductor substrate while suppressing their accumulation in the periphery;
The composition shall include the following.

〔産業上の利用分野〕[Industrial application field]

本発明はゲッタリング方法に係り、特に半導体デバイス
の製造において重金属不純物をLOGO3(Lo−ca
l 0xidation of 5ilicon)の周
辺に集積するのを防止するゲッタリング方法に関する。
The present invention relates to a gettering method, and particularly to a gettering method for removing heavy metal impurities from LOGO3 (Lo-ca) in the manufacture of semiconductor devices.
The present invention relates to a gettering method for preventing oxidation of 5 ilicon from accumulating around the oxidation of 5 ilicon.

〔従来の技術〕[Conventional technology]

半導体デバイスの製造におけるシリコン基板内の一種の
清浄化技術であるゲッタリング技術において、特にFe
、 Cu、 Ni、 Cr等の重金属汚染に対しては従
来から半導体ウェハー内部にゲッタリング中心を作るイ
ントリンシックゲッタリング(IG;Intrinsi
c Getlering)が有効である。しかし半導体
デバイスの高集債化に伴い、例えば半導体基板(シリコ
ン等)上に熱酸化により形成されたフィールド酸化膜と
デバイス活性領域(形成領域)間で(LOCOS周辺)
で歪みが発生している場所(歪み場)がゲッタリングサ
イトとなり、こ\に上記重金属が集積することが指摘さ
れ始めている。
In gettering technology, which is a type of cleaning technology within silicon substrates in the manufacture of semiconductor devices, especially Fe
Intrinsic gettering (IG), which creates a gettering center inside a semiconductor wafer, has traditionally been used to deal with heavy metal contamination such as Cu, Ni, and Cr.
c Getlering) is effective. However, as semiconductor devices become more expensive, for example, between the field oxide film formed by thermal oxidation on the semiconductor substrate (silicon etc.) and the device active region (formation region) (around LOCOS).
It is beginning to be pointed out that the place where distortion occurs (strain field) becomes a gettering site, where the heavy metals mentioned above accumulate.

そこで本発明者はLOCOSを用いて素子分離をしたp
n接合に、デバイスプロセス中の代表的な重金属不純物
であるFeをイオン注入したTEG(Test Ele
ment Group)を作成し、DLTS (Dee
pLevel Transient 5pectros
copy)測定を行い、LOCOSパターンによるFe
濃度依存性を調べた。
Therefore, the present inventor used LOCOS to isolate elements.
TEG (Test El
ment Group) and DLTS (Dee
pLevel Transient 5pectros
Copy) measurement was carried out, and Fe
The concentration dependence was investigated.

その結果、LOCOSパターンの周辺長とFe濃度に相
関があることがわかった(第2図参照)。
As a result, it was found that there was a correlation between the peripheral length of the LOCOS pattern and the Fe concentration (see Figure 2).

LOCOSパターンの周辺長/面積(L/S)にFe濃
度が比例することはLOGOSパターンの周辺の歪み場
にFeが引き寄せられることを示唆している。
The fact that the Fe concentration is proportional to the peripheral length/area (L/S) of the LOCOS pattern suggests that Fe is attracted to the strain field around the LOGOS pattern.

またDLTSのスペクトルをみると、FeはFe−Bベ
アの状態で存在していることがわかる。
Furthermore, looking at the DLTS spectrum, it can be seen that Fe exists in a Fe-B bare state.

このように重金属がLOGDS周辺に集積することが明
らかとなった。
In this way, it has become clear that heavy metals accumulate around LOGDS.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、上記歪み場に集積した重金属は通常のI
Gだけでは除去できない。そのためデバイス特性に対し
て悪い影響を及ぼしている。基本的にはpn接合のリー
ク電流増加やキャリアライフタイムの劣化や、バイポー
ラLSIではリークないしショートが問題となる。
However, the heavy metals accumulated in the strain field are normal I
G alone cannot remove it. Therefore, it has a bad influence on device characteristics. Basically, problems include an increase in leakage current in pn junctions and deterioration of carrier lifetime, and leakage or short circuits in bipolar LSIs.

本発明はLOCOSの周辺の歪み場に半導体デバイスプ
ロセス中の重金属汚染が集積するのを防止し、半導体ウ
ェハーの内部欠陥層に吸収することを目的とする。
The present invention aims to prevent heavy metal contamination during semiconductor device processing from accumulating in the strain field around the LOCOS and absorbing it into internal defect layers of the semiconductor wafer.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題は本発明によれば半導体基板上に選択酸化によ
り素子分離領域を形成する工程、窒素あるいは水素雰囲
気中で該半導体基板を熱処理することによって、該半導
体基板内に混入した重金属不純物が前記素子分離領域周
辺に集積するのを抑制して該半導体基板の内部欠陥層に
該重金属不純物を吸収する工程、を含むことを特徴とす
るゲッタリング方法によって解決される。
According to the present invention, heavy metal impurities mixed into the semiconductor substrate are removed from the semiconductor substrate by forming an element isolation region on the semiconductor substrate by selective oxidation, and by heat-treating the semiconductor substrate in a nitrogen or hydrogen atmosphere. The problem is solved by a gettering method characterized by including the step of absorbing the heavy metal impurities into an internal defect layer of the semiconductor substrate while suppressing their accumulation around the isolation region.

〔作 用〕[For production]

本発明では、酸化膜形成後に窒素雰囲気による熱処理(
窒素アニール)を行うとシリコンウェハー内の窒素が酸
化膜界面に集まること、あるいは水素アニールにより酸
化膜とシリコン結晶の界面準位を減らす等の公知の現象
を利用するものである。すなわちこの窒素アニール、あ
るいは水素アニールを行うことによりLOCO5周辺の
歪み場に窒素あるいは水素を集積させることによって半
導体デバイス工程中、特にイオン注入や、レジスト、ウ
ェル形成の高温(1200℃程度)熱処理工程中に上記
重金属不純物がLOGO3周辺に集積するのが防止され
る。LOCO3周辺、いわゆる、デバイス活性領域に集
積された窒素あるいは水素はデバイス特性に対して何ら
悪影響は及ぼさない。
In the present invention, heat treatment in a nitrogen atmosphere (
This method utilizes known phenomena such as nitrogen in the silicon wafer gathering at the oxide film interface when nitrogen annealing is performed, or hydrogen annealing reducing the interface states between the oxide film and the silicon crystal. In other words, by performing this nitrogen annealing or hydrogen annealing, nitrogen or hydrogen is accumulated in the strain field around the LOCO5, which can be used during the semiconductor device process, especially during the high temperature (approximately 1200°C) heat treatment process for ion implantation, resist, and well formation. Also, the heavy metal impurities are prevented from accumulating around LOGO3. Nitrogen or hydrogen accumulated around LOCO3, so-called device active region, does not have any adverse effect on device characteristics.

〔実施例〕〔Example〕

以下本発明の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.

第1図(a)〜(d)は本発明の1実施例を示す工程断
面図である。
FIGS. 1(a) to 1(d) are process sectional views showing one embodiment of the present invention.

第1図(a)に示すように、例えばシリコンウェハー1
に対し、IG(イントリンシックゲッタリング)熱処理
例えば、高温1000℃、30分と低温700℃、6時
間、高温1000℃、1時間のいわゆる3段階IG熱処
理を行ない内部欠陥層2を形成する。
As shown in FIG. 1(a), for example, a silicon wafer 1
Then, an internal defect layer 2 is formed by performing an IG (intrinsic gettering) heat treatment, for example, a three-step IG heat treatment of a high temperature of 1000° C. for 30 minutes, a low temperature of 700° C. for 6 hours, and a high temperature of 1000° C. for 1 hour.

次に第1図(b)に示すように、デバイス活性領域を形
成すべく所定位置を熱酸化しフィールド酸化膜3 (L
OCO3形成)を形成する。
Next, as shown in FIG. 1(b), a field oxide film 3 (L
OCO3 formation).

次に第1図(C)に示すように、900℃〜1200℃
の温度領域で1時間、窒素(N2)雰囲気で熱処理(N
2アニール)を行なった。このN2アニールにより5i
n2/Si界面(LOCO3周辺)に、Si中の窒素が
2 xlQ17〜3 X10”/ctl集積した図中4
が集積したN2を示す。このN2アニールによりLOC
O3周辺にN2が集積し、この後のデバイス工程中に混
入してくる重金属がLDC口S周辺に集積するのを防ぎ
第1図(d)に示す如<IG層2へ吸収させることがで
きた。
Next, as shown in Figure 1 (C),
Heat treatment (N
2 annealing) was performed. With this N2 annealing, 5i
At the n2/Si interface (around LOCO3), nitrogen in Si is accumulated at 2xlQ17~3x10''/ctl (4 in the figure).
shows the accumulated N2. With this N2 annealing, the LOC
N2 accumulates around O3, and heavy metals that are mixed in during the subsequent device process are prevented from accumulating around the LDC port S, and can be absorbed into the IG layer 2 as shown in FIG. 1(d). Ta.

上記実施例において窒素の代わりに水素ガスを用いて4
50℃、1時間、H2雰囲気として熱処理く水素アニー
ル)を行なっても同様の効果が得られた。
In the above example, hydrogen gas was used instead of nitrogen.
A similar effect was obtained even when heat treatment (hydrogen annealing) was performed at 50°C for 1 hour in an H2 atmosphere.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば半導体デバイスプロ
セスにおいてLOCO9工程で得られた酸化膜と基板と
の界面の歪み場にFe、 Ni等の重金属が集積するこ
とが防止されデバイス特性、歩留等の向上が図られる。
As explained above, according to the present invention, heavy metals such as Fe and Ni are prevented from accumulating in the strain field at the interface between the oxide film and the substrate obtained in the LOCO 9 step in the semiconductor device process, thereby improving device characteristics, yield, etc. This will lead to improvements in

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(d)は本発明の1実施例を説明するた
めの工程断面図であり、 第2図はLOCOSパターンの周辺長/面積(L/S)
にFe濃度が比例することを示すDLTS測定結″果を
示す図である。 1・・・シリコンウェハー、 2・・・内部欠陥層、   3・・・フィールド酸化膜
、4・・・集積したN2゜
FIGS. 1(a) to (d) are process cross-sectional views for explaining one embodiment of the present invention, and FIG. 2 shows the peripheral length/area (L/S) of the LOCOS pattern.
1 is a diagram showing DLTS measurement results showing that the Fe concentration is proportional to . 1... Silicon wafer, 2... Internal defect layer, 3... Field oxide film, 4... Integrated N2゜

Claims (1)

【特許請求の範囲】 1、半導体基板上に選択酸化により素子分離領域を形成
する工程、 窒素あるいは水素雰囲気中で該半導体基板を熱処理する
ことによって、該半導体基板内に混入した重金属不純物
が前記素子分離領域周辺に集積するのを抑制して該半導
体基板の内部欠陥層に該重金属不純物を吸収する工程、
を含むことを特徴とするゲッタリング方法。
[Claims] 1. A step of forming an element isolation region on a semiconductor substrate by selective oxidation, by heat-treating the semiconductor substrate in a nitrogen or hydrogen atmosphere, heavy metal impurities mixed into the semiconductor substrate are removed from the elements. absorbing the heavy metal impurities into the internal defect layer of the semiconductor substrate while suppressing their accumulation around the isolation region;
A gettering method comprising:
JP29222389A 1989-11-13 1989-11-13 Gettering Pending JPH03154346A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29222389A JPH03154346A (en) 1989-11-13 1989-11-13 Gettering

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29222389A JPH03154346A (en) 1989-11-13 1989-11-13 Gettering

Publications (1)

Publication Number Publication Date
JPH03154346A true JPH03154346A (en) 1991-07-02

Family

ID=17779097

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29222389A Pending JPH03154346A (en) 1989-11-13 1989-11-13 Gettering

Country Status (1)

Country Link
JP (1) JPH03154346A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5444001A (en) * 1992-12-25 1995-08-22 Nec Corporation Method of manufacturing a semiconductor device readily capable of removing contaminants from a silicon substrate
JP2005228931A (en) * 2004-02-13 2005-08-25 Denso Corp Semiconductor device and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5444001A (en) * 1992-12-25 1995-08-22 Nec Corporation Method of manufacturing a semiconductor device readily capable of removing contaminants from a silicon substrate
JP2005228931A (en) * 2004-02-13 2005-08-25 Denso Corp Semiconductor device and its manufacturing method

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