JPH03155136A - Method of gettering - Google Patents

Method of gettering

Info

Publication number
JPH03155136A
JPH03155136A JP29412689A JP29412689A JPH03155136A JP H03155136 A JPH03155136 A JP H03155136A JP 29412689 A JP29412689 A JP 29412689A JP 29412689 A JP29412689 A JP 29412689A JP H03155136 A JPH03155136 A JP H03155136A
Authority
JP
Japan
Prior art keywords
gettering
wafer
temperature
sec
subjected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29412689A
Other languages
Japanese (ja)
Inventor
Masaki Aoki
正樹 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP29412689A priority Critical patent/JPH03155136A/en
Publication of JPH03155136A publication Critical patent/JPH03155136A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce leakage current through p-n junctions due to heavy-metal precipitation by performing rapid thermal annealing after an IG process and a preprocess to enable gettering of the precipitated heavy metal such as silicide remaining around the wafer surface. CONSTITUTION:A silicon wafer is subjected to the conventional IG process to form a layer having internal defects. Prior to a device process, LOCOS process (for forming field oxide) is performed in which wells are formed by impurity (p-type or n-type) doping. The wafer is then subjected to rapid thermal annealing at 800-1200 deg.C. For example, the wafer is heated to about 1000 deg.C at a rate of 160 deg.C/sec, held at 1000 deg.C for one minute, and cooled rapidly at a rate higher than 100 deg.C/sec, e.g. at about 110 deg.C/sec. The wafer is then subjected to the device process.

Description

【発明の詳細な説明】 〔概 要〕 ゲッタリング方法に係り、特に半導体ウェハーの重金属
不純物のゲッタリング方法に関し、所定のゲッタリング
がなされずデバイス活性層中に形成され、残留する析出
物をゲッタリングし、ゲッタリング能力を強化、向上さ
せることを目的とし、 半導体ウェハー内にイントリンシックゲッタリングによ
る内部欠陥層を形成し、デバイスプロセスの前処理工程
を行い、その後アニール温度を800℃ないし1200
℃にした熱処理を行い、温度下降速度を100℃/秒以
上で温度を急速下降させる工程を含むことを構成とする
[Detailed Description of the Invention] [Summary] This method relates to a gettering method, particularly a method for gettering heavy metal impurities in semiconductor wafers, and is a method for gettering precipitates that are formed and remain in a device active layer due to lack of predetermined gettering. For the purpose of strengthening and improving the gettering ability, an internal defect layer is formed in the semiconductor wafer by intrinsic gettering, a pretreatment process for the device process is performed, and then the annealing temperature is set to 800℃ to 1200℃.
The method includes a step of performing heat treatment at a temperature of 100° C. and rapidly lowering the temperature at a rate of 100° C./second or more.

〔産業上の利用分野〕[Industrial application field]

本発明はゲッタリング方法に係り、特に半導体ウェハー
の重金属不純物のゲッタリング方法に関する。
The present invention relates to a gettering method, and more particularly to a gettering method for heavy metal impurities in semiconductor wafers.

本発明は従来のイントリンシックゲッタリング法と組み
合わせて用いる方法であって従来のゲッタリング能力を
向上させることができる。
The present invention is a method used in combination with the conventional intrinsic gettering method, and can improve the conventional gettering ability.

〔従来の技術〕[Conventional technology]

半導体デバイスの製造過程において、半導体ウェハー内
の1種の清浄化技術であるゲッタリング技術は外部から
操作を施すもの(Extrinsic Get−ter
ing)と内部に介在する要素を利用するイントリンシ
ックゲッタリング(Intrinsic Getter
ing:以下IGと記す)法が知られている。
In the manufacturing process of semiconductor devices, gettering technology, which is a type of cleaning technology within semiconductor wafers, is a technology that is operated externally (extrinsic gettering technology).
Intrinsic gettering that uses elements intervening inside
ing (hereinafter referred to as IG) method is known.

重金属汚染に対しては従来からIG法が有効であるが、
その方法は半導体ウェハー内に内部欠陥層を形成するこ
とによって半導体デバイスプロセス中に混入するFe、
 Cu、 Ni、 Cr等の重金属不純物を内部欠陥層
にゲッタリングするものである。これら重金属不純物が
ゲッタリングされるのはデバイスプロセス中の高温熱処
理から冷却される過程である。
The IG method has traditionally been effective against heavy metal contamination, but
The method uses Fe introduced during the semiconductor device process by forming an internal defect layer within the semiconductor wafer.
This is to getter heavy metal impurities such as Cu, Ni, and Cr into internal defect layers. These heavy metal impurities are gettered during the cooling process after high-temperature heat treatment during device processing.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、重金属によっては高温熱処理後の冷却過
程中に内部欠陥層に完全にゲッタリングされず例えばシ
リサイド等の析出物をデバイス活性層に形成され残留す
る場合がある。
However, some heavy metals may not be completely gettered to the internal defect layer during the cooling process after high-temperature heat treatment, and precipitates such as silicide may be formed and remain in the device active layer.

本発明は所定のゲッタリングがなされずデバイス活性層
中に形成され、残留する析出物をゲッタリングし、ゲッ
タリング能力を強化、向上させることを目的とする。
The present invention aims to strengthen and improve the gettering ability by gettering precipitates that are formed and remain in the active layer of a device due to a lack of predetermined gettering.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題は本発明によれば、半導体ウエノ\−内にイン
トリンシックゲッタリングによる内部欠陥層を形成し、
デバイスプロセスの前処理工程を行い、その後アニール
温度を800℃ないし1200℃にした熱処理を行い、
温度下降速度を100℃/秒以上で温度を急速下降させ
る工程を含むことを特徴とするゲッタリング方法によっ
て解決される。
According to the present invention, the above problem is solved by forming an internal defect layer in the semiconductor wafer by intrinsic gettering,
Perform a pretreatment process for the device process, then perform heat treatment at an annealing temperature of 800°C to 1200°C,
The problem is solved by a gettering method characterized by including a step of rapidly lowering the temperature at a temperature lowering rate of 100° C./sec or more.

すなわち本発明では再度の高温熱処理(RTA:Rap
id Thermal Anneal) により重金属
の析出物を溶解させ、その後、急冷することによって該
析出物の形成を防止し、重金属の内部欠陥層に吸収する
のである。
That is, in the present invention, another high temperature heat treatment (RTA: Rap
The heavy metal precipitates are dissolved by thermal annealing and then rapidly cooled to prevent the formation of the precipitates and absorb them into the internal defect layer of the heavy metals.

〔作 用〕[For production]

本発明によればIG後デバイスプロセスの前処理を行い
、高温熱処理(RTA処理)によって前処理工程で混入
し、生じた析出物を溶解させた。
According to the present invention, a pretreatment for a device process after IG is performed, and precipitates mixed in and generated in the pretreatment process are dissolved by high temperature heat treatment (RTA treatment).

この高温熱処理中に重金属は格子間位置に固溶されてお
り、その後高速度100℃/秒以上で温度を下げ固溶し
ている重金属の拡散が抑えられる。
During this high-temperature heat treatment, heavy metals are dissolved in solid solution at interstitial positions, and then the temperature is lowered at a high rate of 100° C./sec or higher to suppress the diffusion of the heavy metals dissolved in solid solution.

参考迄に第3図及び第4図にSi中の重金属の固溶度及
び拡散係数を示す(参考文献;5olidState 
Communications、  Vol、4(1,
pp、797−799(1981) K、Wu’n5t
el and P、Wagner)。
For reference, Figures 3 and 4 show the solid solubility and diffusion coefficient of heavy metals in Si (Reference: 5solidState).
Communications, Vol. 4(1,
pp, 797-799 (1981) K, Wu'n5t
el and P, Wagner).

高温熱処理からの冷却方法により、重金属の状態(Si
結晶中に占める位置、結晶学的な構造)が変化すること
は、DLTS (Deep Level Transi
entSpectroscopy)法による測定でスペ
クトルが変化することから推測される。
The state of heavy metals (Si
A change in the position occupied in a crystal (crystallographic structure) is called DLTS (Deep Level Transi...
This is inferred from the fact that the spectrum changes when measured using the entSpectroscopy method.

本発明でアニール温度を800℃ないし1200℃にし
たのは重金属析出物が溶融するために好ましい温度であ
り、温度下降速度を100℃/秒以上としたのは一旦溶
解した重金属析出物が再度析出しないように内部欠陥層
にゲッタリングするためである。なお800〜1200
℃の温度迄は150℃/秒以上で昇温させるのが好まし
い。
In the present invention, the annealing temperature of 800°C to 1200°C is a preferable temperature for melting heavy metal precipitates, and the temperature reduction rate of 100°C/sec or more is used to prevent once-dissolved heavy metal precipitates from precipitating again. This is because gettering occurs in the internal defect layer to prevent it from occurring. In addition, 800-1200
It is preferable to raise the temperature to a temperature of 150°C/second or more.

〔実施例〕〔Example〕

以下本発明の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.

第1図(a)及び(b)はそれぞれ、本発明の1実施例
の熱処理方法を示す図、及びその熱処理の時期を示す図
である。
FIGS. 1(a) and 1(b) are a diagram showing a heat treatment method according to an embodiment of the present invention, and a diagram showing the timing of the heat treatment, respectively.

まずシリコンウェハーを従来のIG処理にかける。この
IG処理では該ウェハーを1100℃の温度に約30分
間保持し、冷却速度を4℃/分にして、約650℃迄降
温し約360分間保持し再度650℃迄上昇させ30分
間保持し徐冷して行なった。次に第1図(b)に示すよ
うにデバイスプロセスの前処理としていわゆるLOCO
3(素子分離領域形成)工程、不純物(p又はn型)ド
ープによりウェル形成等を行なった。その後第1図(a
)に示す本発明のRTA(Rapid Therrna
l Anneal)処理を行なった。すなわちアニール
温度を約1000℃迄を160℃/秒の昇温速度で行な
い、その1000℃で約1分間保持した後、約り10℃
/秒の降温速度で急冷しRTA処理とした。このRTA
処理のゲッタリングの後、第1図(b)に示すようにデ
バイスプロセスの後処理を続けて行なった。
First, the silicon wafer is subjected to conventional IG processing. In this IG process, the wafer is held at a temperature of 1100°C for about 30 minutes, the cooling rate is set to 4°C/min, the temperature is lowered to about 650°C, held for about 360 minutes, then raised to 650°C again, held for 30 minutes, and then gradually I did it cold. Next, as shown in Fig. 1(b), so-called LOCO is performed as a pretreatment for the device process.
In step 3 (element isolation region formation), wells were formed by doping with impurities (p or n type). After that, Figure 1 (a
) The RTA (Rapid Therrna) of the present invention shown in
1 Anneal) treatment was performed. That is, the annealing temperature was increased to approximately 1000°C at a heating rate of 160°C/sec, and after being held at 1000°C for approximately 1 minute, the annealing temperature was increased to approximately 10°C.
RTA treatment was carried out by rapidly cooling the sample at a cooling rate of /second. This RTA
After the gettering process, post-processing of the device process was continued as shown in FIG. 1(b).

このようにRTA処理を行うと、第1表に示すようにデ
バイス活性領域中のFe濃度は本実施例(RTA処理有
)では1.0X10”以下であり従来例(PTA処理無
し)では1.0×101012at/cIIlであった
。またpn接合のリーク電流が原因となるCCD (固
体撮像素子)の暗時出力信号(DS:Dark Sig
nal)による不良率(DS不良率)は約l/10に減
少した。
When the RTA treatment is performed in this manner, as shown in Table 1, the Fe concentration in the device active region is 1.0×10” or less in the present example (with RTA treatment) and 1.0×10” in the conventional example (without PTA treatment). 0x101012at/cIIl.Also, the dark output signal (DS: Dark Sig
The defective rate (DS defective rate) was reduced to about 1/10.

第1表 〔発明の効果〕 以上説明したように本発明によればイントリンシックゲ
ッタリングでは除去できずにウェハー表面付近にシリサ
イド等の析出物として残存する重金属をゲッタリングす
ることができ、上記重金属析出物に起因するpn接合の
リーク電流を減少させることができる。
Table 1 [Effects of the Invention] As explained above, according to the present invention, heavy metals that cannot be removed by intrinsic gettering and remain as precipitates such as silicide near the wafer surface can be gettered, and the heavy metals mentioned above can be gettered. It is possible to reduce the leakage current of the pn junction caused by the precipitates.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)及び(b)はそれぞれ、本発明の1実施例
の熱処理方法を示す図、及びその熱処理の時期を示す図
であり、 第2図及び第3図はそれぞれSi中の重金属の固溶度及
び拡散係数を示す図である。
FIGS. 1(a) and (b) are diagrams showing a heat treatment method and the timing of the heat treatment, respectively, in one embodiment of the present invention, and FIGS. 2 and 3 are diagrams showing heavy metals in Si, respectively. FIG. 3 is a diagram showing the solid solubility and diffusion coefficient of .

Claims (1)

【特許請求の範囲】[Claims] 1、半導体ウェハー内にイントリンシックゲッタリング
による内部欠陥層を形成し、デバイスプロセスの前処理
工程を行い、その後アニール温度を800℃ないし12
00℃にした熱処理を行い、温度下降速度を100℃/
秒以上で温度を急速下降させる工程を含むことを特徴と
するゲッタリング方法。
1. Form an internal defect layer in the semiconductor wafer by intrinsic gettering, perform a device process pretreatment process, and then increase the annealing temperature to 800°C to 12°C.
Heat treatment is performed at 00℃, and the temperature decrease rate is 100℃/
A gettering method characterized by including a step of rapidly lowering the temperature in seconds or more.
JP29412689A 1989-11-14 1989-11-14 Method of gettering Pending JPH03155136A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29412689A JPH03155136A (en) 1989-11-14 1989-11-14 Method of gettering

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29412689A JPH03155136A (en) 1989-11-14 1989-11-14 Method of gettering

Publications (1)

Publication Number Publication Date
JPH03155136A true JPH03155136A (en) 1991-07-03

Family

ID=17803633

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29412689A Pending JPH03155136A (en) 1989-11-14 1989-11-14 Method of gettering

Country Status (1)

Country Link
JP (1) JPH03155136A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11150119A (en) * 1997-11-14 1999-06-02 Sumitomo Sitix Corp Method and device for heat-treating silicon semiconductor substance
JP2004056132A (en) * 2002-07-16 2004-02-19 Hynix Semiconductor Inc Method for fabricating semiconductor wafer
JP2008205024A (en) * 2007-02-16 2008-09-04 Sumco Corp Silicon wafer and manufacturing method therefor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11150119A (en) * 1997-11-14 1999-06-02 Sumitomo Sitix Corp Method and device for heat-treating silicon semiconductor substance
JP2004056132A (en) * 2002-07-16 2004-02-19 Hynix Semiconductor Inc Method for fabricating semiconductor wafer
JP2008205024A (en) * 2007-02-16 2008-09-04 Sumco Corp Silicon wafer and manufacturing method therefor

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