JPH03153021A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03153021A JPH03153021A JP29262989A JP29262989A JPH03153021A JP H03153021 A JPH03153021 A JP H03153021A JP 29262989 A JP29262989 A JP 29262989A JP 29262989 A JP29262989 A JP 29262989A JP H03153021 A JPH03153021 A JP H03153021A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- compound semiconductor
- substrate
- single crystal
- amorphous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 150000001875 compounds Chemical class 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000013078 crystal Substances 0.000 claims abstract description 17
- 239000010409 thin film Substances 0.000 claims abstract description 15
- 238000005468 ion implantation Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 8
- 150000002500 ions Chemical class 0.000 claims abstract description 7
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 239000007791 liquid phase Substances 0.000 claims description 2
- 239000007790 solid phase Substances 0.000 claims description 2
- 238000002425 crystallisation Methods 0.000 claims 1
- 230000008025 crystallization Effects 0.000 claims 1
- 238000010030 laminating Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 40
- 230000007547 defect Effects 0.000 abstract description 9
- 239000002131 composite material Substances 0.000 abstract description 4
- 239000002344 surface layer Substances 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 239000000470 constituent Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- -1 ALGaAs Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
【産業上の利用分野〕
本発明は半導体装置の製造方法に関する。特に５ｉ１ｉ
子回路及び化合物半導体発光デバイス、電子回路の複合
デバイスの高信頼性化において有効である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device. Especially 5i1i
It is effective in increasing the reliability of child circuits, compound semiconductor light emitting devices, and composite devices of electronic circuits.
［従来の技術］
従来、Ｓｉ基板上にＧａＡｓ、ＧａＰなどの化合物半導
体層を形成する時、ＭＢＥ法やＭＯＣＶＤ法により化合
物半導体をヘテロエピタキシャル成長していた。しかし
ながら、ヘテロエピタキシャル成長では、格子条数や熱
膨張係数のちがいから、歪が発生する。Ｓｉ表面は非常
に活性化しており、付着不純物や原子レベルの凹凸が存
在するため、鎖中や過剰な点欠陥、微小欠陥は、Ｓｉ表
面に集中し、歪が緩和する。このためＳｉ表面上に欠陥
の少ない単結晶化合物半導体薄膜が成長せず、多結晶薄
膜化したり、あるいは、Ｓｉ基板との密着が得られない
という不具合が生じた。[Prior Art] Conventionally, when forming a compound semiconductor layer such as GaAs or GaP on a Si substrate, the compound semiconductor was heteroepitaxially grown by MBE or MOCVD. However, in heteroepitaxial growth, distortion occurs due to differences in the number of lattice striations and coefficient of thermal expansion. Since the Si surface is highly activated and has attached impurities and unevenness at the atomic level, the chains, excessive point defects, and minute defects are concentrated on the Si surface, and the strain is relaxed. For this reason, a single-crystal compound semiconductor thin film with few defects is not grown on the Si surface, resulting in a polycrystalline thin film or inability to achieve close contact with the Si substrate.
［発明が解決しようとする課題］
従来技術では、Ｓｉ基板上に膜といえるほどの十分な広
さを持った化合物半導体層が形成できないため、高信頼
な化合物半導体デバイスがＳｉ基板上に形成できなかっ
た０本発明は、かかる従来の問題を回避し、Ｓｉ基板上
に無欠陥の化合物半導体層を形成し、５ｉｉＩ子回路及
び化合物半導体デバイスまたは集積回路の複合デバイス
の高信顛性化を可能にする半導体装置の製造方法の提供
を目的とする。[Problem to be solved by the invention] With conventional techniques, it is not possible to form a compound semiconductor layer with a sufficient width to be called a film on a Si substrate, so a highly reliable compound semiconductor device cannot be formed on a Si substrate. The present invention avoids such conventional problems, forms a defect-free compound semiconductor layer on a Si substrate, and enables high reliability of a 5III child circuit, a compound semiconductor device, or a composite device of an integrated circuit. The purpose of the present invention is to provide a method for manufacturing a semiconductor device.
１課題を解決するための手段１
本発明では、単結晶Ｓｉ基板上に、化合物半導体薄膜を
形成後、５ｉｌｌｌｌが蓄積され、イオン注入により、
該Ｓ１薄膜、該化合物半導体膜、及び、該Ｓｉ単結晶基
板の表面層をアモルファス化する。この後、熱処理によ
り該アモルファス層は単結晶化（固相または液相成長）
する、この時、格子条数や熱膨張係数のちがいによる歪
が発生する。この歪は、該Ｓ１単結晶基板のイオン注入
時のアモルファス／単結晶（ａ−ｃ）界面下で緩和され
るため、単結晶化した化合物半導体層またはＳ１層は無
欠陥層となる。すなわち、過剰点欠陥や微小欠陥は、該
ａ−Ｃ欠陥でゲッタリングされる。また、ＡＩ２＋−ｍ
Ｇａ＋＋ Ａｓ、Ｇａ＋−ｘ Ｉ ｎ＋＋Ａ ｓ 、
Ｇ ａ １−８Ｉ ｎｍ ＡＳ＋−ｙ Ｐｙなとの化
合物半導体における構成元素の蒸気圧の違いからくる熱
処理時のＰやＡｓの蒸発は、表面のＳ１層が保護膜とな
って問題ない、さらに、化合物半導体膜の構成元素の比
１例えば、化合物半導体成膜時に発生するストイキオメ
トリのずれについては、イオン注入時のイオンの選択と
ドーズの設定で制御できる０例＾ば、ＧａＡｓ半導体層
蓄積時にＡｓが蒸発しＧａリッチになっている場合には
、Ａｓイオン注入によりアモルファス化と同時に、スト
イキオメトリのずれを補正できる０以上説明したように
本発明によれば、Ｓｌ基板上には、ストイキオメトリ−
の制御された化合物半導体層とＳｉ薄膜の無欠陥単結晶
層が形成可能になる。該単結晶Ｓｉ薄膜または該単結晶
化合物半導体層に、素子デバイスを形成、配線接続を行
なえば、高信頼性Ｓ１または化合物半導体集積回路が出
来る。Means for Solving Problem 1 In the present invention, after forming a compound semiconductor thin film on a single crystal Si substrate, 5illll is accumulated, and by ion implantation,
The surface layers of the S1 thin film, the compound semiconductor film, and the Si single crystal substrate are made amorphous. After this, the amorphous layer becomes single crystallized (solid phase or liquid phase growth) by heat treatment.
At this time, distortion occurs due to the difference in the number of grid lines and the coefficient of thermal expansion. This strain is relaxed under the amorphous/single crystal (ac) interface during ion implantation of the S1 single crystal substrate, so the single crystal compound semiconductor layer or S1 layer becomes a defect-free layer. That is, excessive point defects and minute defects are gettered by the a-C defects. Also, AI2+-m
Ga++ As, Ga+-x I n++ As,
G a 1-8I nm AS+-y There is no problem with the evaporation of P and As during heat treatment due to the difference in vapor pressure of the constituent elements in the compound semiconductor such as Py, since the S1 layer on the surface serves as a protective film. The ratio of the constituent elements of a compound semiconductor film is 1. For example, the stoichiometry deviation that occurs during compound semiconductor film formation can be controlled by ion selection and dose setting during ion implantation. When As evaporates and becomes Ga-rich, As ion implantation makes it amorphous and at the same time corrects the deviation in stoichiometry. Ikiometry
This makes it possible to form a compound semiconductor layer with controlled properties and a defect-free single crystal layer of Si thin film. By forming element devices and wiring connections on the single crystal Si thin film or the single crystal compound semiconductor layer, a highly reliable S1 or compound semiconductor integrated circuit can be obtained.
〔実 施 例１
以下、実施例を用いて説明する。第１〜３図は１本発明
による半導体装置の製造方法の工程断面図である。第１
図において、Ｓｉ基叛ｌ上には、化合物半導体層ＩｎＰ
層２をＭＯＣＶＤ法で〜Ｏ，ｌｕｍ蓄積後、ＣＶＤまた
はスパッタによりＳｉ薄膜層３を〜０．１ｕｍ蓄積して
いる。ここでは、ＩｎＰを取り上げているが、ＧａＡｓ
、ＡＬＧａＡｓ、ＺｎＳなど、 Ｉｌ、 ＩＩＩ、Ｉ
Ｖ、Ｖ、ＶＩ属の元素からなるいずれの化合物半導体で
も良い、特に融点が１０００℃以上で、Ｓｉの融点に近
く、格子条数もＳｉに近い、ＡＬＧａＡｓ、ＧａＡｓ、
ＧａＰ、ＩｎＰ、ＺｎＳなどの化合物半導体層において
有効である。第２図において、Ｓｉ基板ｌには、イオン
４を注入し１表面層５をアモルファス化している０例え
ばリン１８０ｋｅＶ、 ５ｘ １０１１Ｉｃｍ−”、及
び、Ｓｉ、６０ｋｅＶ、５ｘ １０”ｃｍ−”注入を行
なえば、〜０．２３μｍのアモルファス層５が形成でき
る。このイオン注入条件は１表面からＳｉ基板領域まで
連続的にアモルファスが形成されるように設定する。[Example 1] Hereinafter, an explanation will be given using an example. 1 to 3 are process cross-sectional views of a method of manufacturing a semiconductor device according to the present invention. 1st
In the figure, a compound semiconductor layer InP is formed on the Si-based layer.
After layer 2 has been accumulated to a thickness of ~0.1 um by MOCVD, a Si thin film layer 3 has been accumulated to a thickness of ~0.1 um by CVD or sputtering. InP is taken up here, but GaAs
, ALGaAs, ZnS, etc., Il, III, I
Any compound semiconductor consisting of V, V, and VI group elements may be used, especially ALGaAs, GaAs, which has a melting point of 1000° C. or higher, close to the melting point of Si, and has a lattice number close to that of Si.
It is effective in compound semiconductor layers such as GaP, InP, and ZnS. In FIG. 2, ions 4 are implanted into the Si substrate 1 to make the surface layer 5 amorphous. For example, an amorphous layer 5 of ~0.23 μm can be formed.The ion implantation conditions are set so that an amorphous layer 5 is formed continuously from one surface to the Si substrate region.
また、イオン種は、化合物半導体層の成分元素（例えば
、ＧａＡｓの場合にはＧａ、Ａｓイオン）またはＳｉを
用いる。第３図において、熱処理を行なうと、アモルフ
ァス層５は再結晶化する。イオン注入時のアモルファス
／単結晶界面下には２次欠陥６が存在するが、ＩｎＰ単
結晶層２及びＳｉ薄膜層３は無欠陥単結晶が成長する。Further, as the ion species, a component element of the compound semiconductor layer (for example, Ga or As ion in the case of GaAs) or Si is used. In FIG. 3, the amorphous layer 5 is recrystallized by heat treatment. Although secondary defects 6 exist under the amorphous/single crystal interface during ion implantation, defect-free single crystals grow in the InP single crystal layer 2 and the Si thin film layer 3.
この後、例えばＩｎＰ層にはＮ型ＭＩＳＦＥＴ、Ｓｉ層
にはＰ型ＭＯＳ Ｆ ＥＴの素子デバイスを形成、配線
接続を行なうことにより、高信頼性化された、高速集積
回路からなる半導体装置が完成する。After this, element devices such as an N-type MISFET in the InP layer and a P-type MOSFET in the Si layer are formed and wiring connections are made, thereby completing a highly reliable semiconductor device consisting of a high-speed integrated circuit. do.
〔発明の効果］
以上説明したように、本発明の半導体装置の製造方法に
よれば、Ｓｉ基板上に無欠陥の化合物半導体層形成が可
能となり、半絶縁化合物半導体上のＳｉ電子回路または
化合物半導体デバイスを同−Ｓｉ基板上に形成でき、高
信頼性複合デバイスから成る半導体装置を提供する。[Effects of the Invention] As explained above, according to the method for manufacturing a semiconductor device of the present invention, it is possible to form a defect-free compound semiconductor layer on a Si substrate, and it is possible to form a defect-free compound semiconductor layer on a semi-insulating compound semiconductor or Si electronic circuit on a semi-insulating compound semiconductor. To provide a semiconductor device comprising a highly reliable composite device in which devices can be formed on the same Si substrate.
第１図〜第３図は本発明による半導体装置の製遣方法の
工程断面図。
ｌ・・・Ｓ１基板
２・・・化合物半導体層
３・・・Ｓ１層
４・・・注入イオン
５・・・アモルファス層
６・・・２次欠陥層1 to 3 are process cross-sectional views of a method for manufacturing a semiconductor device according to the present invention. l... S1 substrate 2... Compound semiconductor layer 3... S1 layer 4... Implanted ion 5... Amorphous layer 6... Secondary defect layer
Claims (1)
ｉ薄膜を積層後、Ｓｉイオンまたは化合物半導体構成原
子のイオン注入を行ない、該Ｓｉ薄膜層、該化合物半導
体層、及び該Ｓｉ基板表面領域をアモルファス化した後
、熱処理を行ないＳｉ／化合物半導体／Ｓｉ基板の単結
晶化（固相または液相成長）を行なった後、該単結晶Ｓ
ｉ薄膜または該単結晶化合物半導体層には、素子デバイ
スが形成、接続されることを特徴とする半導体装置の製
造方法。After forming a compound semiconductor thin film on a single crystal Si substrate, S
After laminating the i thin film, ion implantation of Si ions or atoms constituting the compound semiconductor is performed to make the Si thin film layer, the compound semiconductor layer, and the surface area of the Si substrate amorphous, and then heat treatment is performed to form the Si/compound semiconductor/Si After performing single crystallization (solid phase or liquid phase growth) of the substrate, the single crystal S
i. A method for manufacturing a semiconductor device, characterized in that element devices are formed and connected to the thin film or the single crystal compound semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29262989A JPH03153021A (en) | 1989-11-10 | 1989-11-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29262989A JPH03153021A (en) | 1989-11-10 | 1989-11-10 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03153021A true JPH03153021A (en) | 1991-07-01 |
Family
ID=17784274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29262989A Pending JPH03153021A (en) | 1989-11-10 | 1989-11-10 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03153021A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107910402A (en) * | 2017-06-28 | 2018-04-13 | 超晶科技（北京）有限公司 | A kind of indium-gallium-arsenide infrared detector material preparation method |
-
1989
- 1989-11-10 JP JP29262989A patent/JPH03153021A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107910402A (en) * | 2017-06-28 | 2018-04-13 | 超晶科技（北京）有限公司 | A kind of indium-gallium-arsenide infrared detector material preparation method |
| CN107910402B (en) * | 2017-06-28 | 2020-07-17 | 超晶科技（北京）有限公司 | Preparation method of indium gallium arsenic infrared detector material |
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