JPH03147423A - Tri-state setting circuit by one logic control line - Google Patents

Abstract

PURPOSE:To set the tri-state of an analog section with use of one control line by bringing the control section signal of a logic section to the tri-state as a high level H, a low level L and a clock CLK. CONSTITUTION:The LPF311 of detection circuit 31 of a state detection section 3 extracts a power voltage VDD when the input signal from a control line 2 is at an H level, the LPF311 extracts a ground level G when the input signal is at an L level, and the LPF311 extracts a DC voltage around VDD/2 when the input signal is a clock CLK respectively, and the extracted signal is outputted to a window comparator 312. The comparator 312 has threshold values alpha, beta and detects the voltage being a voltage alpha or over, a voltage beta or below or between the voltages alpha and beta, and outputs the detected voltage to a logic circuit 32. The circuit 32 decides the tri-state depending on the output from the comparator 312 and outputs a logic code in response to the states 1-3. Thus, the state detection section 3 of the analog section 20 sets the signal representing tri-state, H, L levels and the clock CLK designated by the control section 1 of the logic section 10 through one control line 2.

Description

[Detailed Description of the Invention] [Summary] Like a mobile communication terminal, the logic section and analog section are separated, and the logic section generates a setting signal to set the state of the analog section, and the analog section is connected to the master clock. There is no reset function when the power is turned on, and the state setting device consists of a state detection section that detects the setting signal sent from the logic section through a control line connected to the logic section and outputs a logic code according to each state. Regarding the circuit, if the number of control lines connecting the logic shift section and the analog section is one, and the analog section has no master clock and no power-on reset, the control section of the logic section has a high level of 11 and a low level of 11. There are three logic circuits that send signals in three states, level L and clock CLK, to the analog section via the control line, detect the levels of the three state signals in the state detection section of the analog section, and encode the detection results. The purpose is to be able to send out logical codes according to each state, and the logic section uses a single power supply V. and ground G to set the state of the analog section, a high level 11 of DC voltage close to power supply voltage VDD, a low level L of DC voltage close to ground potential G, and a DC voltage close to half of power supply voltage VDD. A 3-state signal of a square wave clock CLK centered on the center is generated and sent to the analog section through a single control line, and the state detection section of the analog section detects a voltage smaller than the power supply voltage vDD, which is half the power supply voltage.
Threshold value α larger than DD/2 and half of the power supply voltage Vno
/2 and greater than the ground potential G, the output signal of the one control line has a voltage above the threshold α, a voltage below the threshold β, and a voltage between the threshold α and the threshold β. The configuration is such that the voltages are detected as setting signals for the three states, respectively.

[Industrial application field]

The present invention is similar to a mobile communication terminal in which the logic section and analog section are separated, the logic section must set the state of the analog section, and the analog section does not have a master clock or power-on reset. When simplification of the circuit is required, the status signal set in the logic unit is transmitted to the analog unit via a control line connecting each other, and the status signal is detected by the status detection unit of the analog unit, encoded, and output. This invention relates to a state setting circuit using logic control lines.

[Conventional technology]

In the conventional state setting circuit using logic control lines, as shown in FIG.
A status signal expressed as two-level values of "H" and "L" is transmitted to the analog section 20 via the control line 2, and the analog section 20 has no master clock and no power-on reset function that resets the output when the power is turned on. In this case, analog section 2
The detection circuit 31A of the state detection unit 3A of 0 detects the level of the state signal coming through the control line 2, and the logic circuit 3□ encodes the detection result, and sends out a logic code according to each state signal. do.

When the control line 2 is a single tree 2a, the control section 1 of the logic section 10 sets two states, and the state detection section 3A of the analog section 20 sends out the logic codes of state 1 and state 2. When there are two control lines 2a and 2b, the control section 1 sets two states for a total of four states, and the state detection section 38 of the analog section 20 sends out logic codes for states 1 to 4. The configuration was as follows.

[Problem to be solved by the invention]

In the above conventional method, the state detection section 3 of the analog section 20
Since A has no master clock and no power-on reset function, if there is only one control line 2 2a, the control section l of the logic section 10 inputs serial data and clock to one control line 2a. At the time, the state detection section 3A of the analog section 20
Even if the detection circuit 31A detects the data and clock levels, the logic circuit 3□.

cannot encode the detection results and output the logical code of each state signal. Therefore, analog section 2
Under the condition that the state detection unit 3A of 0 does not have a master clock and does not have a power-on reset function, one control line 2a
So, two state settings, two control lines 2a and 2b are 4.
The problem was that only one state could be set. However, if there are three control lines 2, it is possible to configure a so-called serial interface using three signals: data, clock, and strobe, so the scope of the problem is limited to two control lines 2. . In the present invention, the number of control lines 2 connecting the logic section 10 and the analog section 20, which are separated from each other, is one, and the state detection section 3 of the analog section 20 does not have a master clock and has a power-on reset function. If there is no signal, the control unit 1 of the logic unit 10 sends signals of three states, high level H, low level L, and clock CLK, to the analog unit 20 via one control line 2, and the state detection unit of the analog unit 20 3 detection circuit.

In step 3, the logic circuit 3□ detects the levels of the three state signals and encodes the detection results.The logic circuit 3□ detects the levels of the three state signals and encodes the detection results. The challenge is to provide

[Means to solve the problem]

This problem is solved by the control section 1 of the logic section 10 as shown in FIG.
The signal sent from one control line 2 is high level H.
a buffer 3° that separates and sends out three-state analog signals of low level L and clock CLK; and a detection circuit 33 that detects a level component near DC of the three-state signal output from the buffer; Power supply voltage V for level H input. . Outputs DC voltage near ground, and outputs DC voltage near ground G for low level L input, and outputs DC voltage near ground G.
For the LK input, there is a low-pass filter LPF 3° that outputs a DC voltage around half the power supply voltage V on /2, and a three-state DC level around the output of the filter LPF.

Threshold α (vDD/2 × α〈vDD) and β (G＜β〈
V DD /2) and outputs a voltage above α, a voltage below β, and a voltage between α and β, and the window comparator 31. Judging the three output signals of state 1.2
．． This problem is solved by the present invention, in which the state detection section 3 of the analog section 20 is configured by the logic circuit 3□ that sets the value 3.

In the principle diagram of FIG. 1 showing the basic configuration of a three-state setting circuit using one logic control line of the present invention, 1 is a control section of a logic section 10, and a single power supply V. and ground G, generate three signals, high level H, low level L, and clock CLK, which set the three states of analog section #O, and send them to analog section 20 via one control line 2. Transmit.

Reference numeral 2 denotes one control line that transmits three status signals, a high level 11, a low level L, and a clock CLK, from the control unit 1 of the logic unit 10 to the analog unit 20.

3 is a state detection unit of the analog unit 20 that detects the levels of three signals, high level H, low level L, and clock CLK sent through one control line 2, and outputs a logical code; Buffer 3°, low pass filter LPF 3□ and window comparator 3□ detection circuit 3. and a logic circuit 3□.

3° is a buffer that separates and outputs analog signals in three states from the signal sent from the control unit 1 of the logic unit 10.

3I is a detection circuit that detects the component near DC of the three-state signal output from the buffer 3°, and includes a low-pass filter 3
11 and window comparators 3 and 2.

The low-pass filter 3II outputs a DC voltage near the three-state signal from the buffer 3°, that is, a DC voltage near the power supply voltage v0 for an input of high level 11.

This is a low-pass filter LPF that outputs a DC voltage near ground G in response to a low level L input, and outputs a DC voltage in the vicinity of half the power supply voltage Vofl/2 in response to a clock CLK input.

Window comparators 3 and 2 are low-pass filters 311
-threshold α(V o.

/2 < a < V on ) and β (G < β < −v D
D/2) k: Voltage above α, voltage below β, α
This is a window comparator that detects the voltage between β and β.

3□ is the detection circuit 3. This is a logic circuit that determines three states of the input signal based on the output of the window comparator 3□, and outputs the logic code of states 1, 2, and 3 designated by the control unit 1 of the logic unit 10.

[Effect]

A detection circuit 3 of the state detection section 3 of the analog section 20 connected to the logic section 10 by one control line 2. low pass filter 3
11 is a DC voltage near the power supply voltage V Ot+ when the input signal from the control line 2 is at a high level H.

For low level L, use DC voltage near ground potential G.

In the case of clock CLK, take out the DC voltage around half of the power supply voltage, VDo/2, and apply it to window comparator 3□
Output to. The window comparators 3 and 2 have threshold values α (V on /2 < α < V DD ) and β (
G<β<V on /2), and the voltage is greater than or equal to α and less than or equal to β.

The voltage between α and 30 is detected and output to the logic circuit 3□.

Logic circuit 3. is the detection circuit 3. Three states are determined based on the outputs from window comparators 3 and 2, and states 1 and 2 are
．． Outputs a logical code according to 3. As described above, the state detection section 3 of the analog section 2o can set the three-state signals of high level I+, low level, and clock CLK specified by the control section 1 of the logic section 10 by one control wire 2. The problem is solved because it is possible.

〔Example〕

FIG. 2 shows a three-dimensional diagram using one logic control line according to an embodiment of the present invention.
It is a circuit diagram of a state detection section of an analog section, showing the configuration of a state setting circuit. FIG. 3 is a three-state signal level diagram for explaining the operation. In the circuit diagram of the state detection unit shown in FIG. 2, the buffer 3° receives the high level H9 sent from the control unit 1 of the logic unit 10 via one control line 2 (not shown), and the clock CLK
Consists of amplifier B that receives and amplifies signals in three states,
The output is input to the low-pass filter 3z of the detection circuit 31.

Detection circuit 3. The low-pass filter 3Il is a filter LPF consisting of a series resistor R and a capacitor C that busses the high-frequency component to ground G, and its output is input to the positive input terminal, and the signal to the output terminal is input to the negative input terminal. It consists of a feedback differential amplifier (voltage follower). and detection circuit 3I
The window comparator 3.2 is composed of two parallel differential amplifiers OP+z-+ and OP+z-zte, and the positive input terminals of each of them both receive a signal to the output terminal of the differential amplifier of the low-pass filters 3 and 1. input, differential amplifier OP +
A power supply voltage V is applied to the negative input terminal of z-+. The resistance R + +
, R+□, and a threshold value β obtained by dividing the power supply voltage VDD by the resistor RZII Rzz is input to the negative input terminal of the differential amplifier OP+zz. The window comparator 3I2 is a gate AND that performs an AND process on the re-outputs of the differential amplifiers oPI□-,, op12-2 of the low-pass filter 311, and the inverted output of the differential amplifier OP+z-+ and the output of OP+z-z. Gate AND2 for AND processing and differential amplifier OP+z-I-
A game that performs OR processing and inverts the re-output of op+z-z) N
Consisting of OR, the output H of the window comparator 31 □ gate AND corresponds to the high level H of the output of the state l of the control line 2, and the output H of the gate AND corresponds to the high level H of the output of the control line 2.
Corresponding to the clock CLK of the output of state B2, the gate NO
The output I of R is output in response to the low level of the state 3 output of control line 2.

When the output of the buffer 3° of the state detection unit 3 of the analog unit 20 is the clock “CLK” as shown in FIG. Therefore, the signal at the output terminal A of the differential amplifier has a triangular waveform as shown in (a)-■ in Fig. 3, and the amplitude is equal to the threshold value of the window comparators 3 and 2 in the next stage. It will be between α and β. Therefore, the differential amplifier OP lz-+ of the window comparator 312
The output of becomes low level “#”, and the differential amplifier OPI□,
The output becomes high level “H” and is input to logic circuit 3□, and only the output of AND2 becomes “H” (gate of logic circuit 3□)
Therefore, the clock “CLK” in state 2 of the output of control line 2
The output corresponds to ”.

When the output of the buffer 3° is at the high level H in state 1, the signal operation to the output terminal of the filter LPFO differential amplifier is as shown in 0)) in Fig. 3, and the differential output of the window comparators 3 and 2 is Amplifier 0hz-+ and differential amplifier OP+z-
The outputs of z both become high level "II", and the logic circuit 3,
The output of only the gate AND of the logic circuit 32 becomes "H", and the output corresponds to the high level H of state 1 of the output of the control line 2.

When the output of the buffer 3° is at a low level in state 3, the signal operation at the output terminal A of the differential amplifier of the filter LPF is as shown in FIG. Amplifier OP+z-+ and differential amplifier OP+z
Both outputs of -z become low level "Yes" and logic circuit 3.
The output of the logic circuit 3□ is inputted to the logic circuit 3□, and the output of only NOH becomes ``■'', which corresponds to the low level L of state 3 of the control line 2.

As a result of the above operation, the state detection section 3 of the analog section 20 in FIG. 11 line 2
Accordingly, the high level 11. specified by the control unit 1 of the logic unit 1o. It is possible to set a three-state signal of the clock CLK and the low level L, and it can be used for gain switching, path switching, etc. (not shown) of the analog section 2o, so there is no problem.

(Effects of the Invention) As explained above, according to the present invention, the signal of the control section of the logic section is set to high level and low level, and the clock CLK
By setting the three states, it is possible to set the analog section in three states with one control line, and the values of the resistor R and capacitor C that make up the low-pass filter of the analog section increase the speed of the clock CLK. As a result, the value can be set to a small value, and when the circuit is integrated into an IC, it can be built in, and the number of connection bins required for the IC circuit can be reduced.

Figure 4 is a block diagram of a conventional state setting circuit using logic control lines.

In the figure, 1 is a control section of the logic section 10, 2 is a control line, 3 is a state detection section of the analog section 20, 3° is a buffer,
3. 3□ is a detection circuit, 3□ is a low-pass filter, 3□ is a window comparator, and 3□ is a logic circuit.

[Brief explanation of the drawing]

Fig. 1 is a principle diagram showing the basic configuration of a three-state setting circuit using one logic control line according to the present invention, and Fig. 2 shows the state of the analog part of the three-state setting circuit using one logic control line according to the embodiment of the present invention. FIG. 3 is a circuit diagram showing the configuration of the detection section.

Claims (1)

[Claims] A setting signal for setting the state of the analog section (20) is generated in a logic section (10) separate from the analog section, and the analog section is connected to the logic section without a master clock or a reset function when the power is turned on. In a circuit consisting of a state detection section (3) that detects the setting signal sent from the logic section via a control line (2) and outputs a logic code according to each state, the logic section (10) is configured simply. One power supply (V_
D_D) and ground (G) to set the state of the analog section (20). The analog section (20
), and the state detection unit (3) of the analog section detects that the state detection unit (3) is smaller than the power supply voltage (V_D_D) and is half of the power supply voltage (V_D_D
/2) larger threshold α and half of the power supply voltage (V_D
A voltage above the threshold α, a voltage below the threshold β, a threshold from the output signal of the one control line (2) due to the threshold β which is smaller than _D/2) and larger than the ground potential (G). α
3 by one logic control line, characterized in that a voltage between and a threshold value β is detected as a setting signal for the three states.
State setting circuit.