JPH07106927A - Duty factor correcting circuit - Google Patents

Abstract

PURPOSE:To reduce the scale and the cost of a duty factor correcting circuit by correcting the duty through a primary LPF consisting of a CMOS inverter, a resistance and a capacitor. CONSTITUTION:An input signal A has an error of duty ratio caused by a waveform distortion during its transmission. This signal A is supplied to a CMOS inverter 1 and binarized as an output B. The output B is supplied to an LPF 2 consisting of a resistance R1 and a capacitor C1, and the LPF 2 attenuates and eliminates the high clock frequency component of the signal B. Thus the filter output C is approximate to a sine wave. Then a CMOS inverter 3 secures connection between the input and the output via a high resistance R2 so that the input is identical with the threshold potential of the inverter 3. Under such conditions, the DC component is eliminated from the output C of the LPF 2 by a capacitor C2 and the output C is supplied to the inverter 3. Then an output signal E has 50% duty factor through pulse generation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duty correction circuit for a square wave signal having a duty ratio of around 50%.

[0002]

2. Description of the Related Art When a square wave signal having a duty ratio of 50% is transferred between a substrate and a device, a waveform collapse occurs due to impedance mismatch or the like. It is necessary to have a correction circuit that holds the percentage. Therefore, for example, a signal transmitting / receiving circuit is disclosed in
A complicated constituent circuit as described in Japanese Patent No. 131615 has been required.

[0003]

DISCLOSURE OF INVENTION Problems to be Solved by the Invention
According to the conventional circuit for correcting to a square wave of%, many components such as an amplifier, a comparator, an integrator, a differential amplifier, and a gain control circuit are required, and a complicated structure for performing feedback amplification is obtained. In addition, since an integrator is used, it is necessary to have a sufficiently large time constant for the cycle of the output signal, and a large capacitor value is required. Therefore, in the conventional technology, the circuit becomes complicated,
Due to the increase in the capacitor value, the circuit cannot be downsized and the cost cannot be reduced, and the LSI cannot be realized.

An object of the present invention is to reduce the size and cost of this duty correction circuit, and thereby to realize an LSI.

[0005]

The above object is achieved by realizing the binarization of the signals of the first stage and the latter stage with the same CMOS inverter and realizing the single power supply operation by using the resistor and the small capacity capacitor. It Furthermore, since the time constant of the filter can be made equal to the cycle of the output signal by using a low-pass filter that removes high frequencies without using an integrator, this is achieved by reducing the capacitor capacitance value and downsizing.

[0006]

The input signal is binarized by the CMOS inverter in the first stage. Then, this output signal is input to a low-pass filter including the following resistor and capacitor, the high frequency component of the input signal is attenuated, and the output of the filter has a waveform close to a sine wave. Further, since the center point of the AC component of the sine wave output is set to the threshold potential of the CMOS inverter of the next stage, it is necessary to add only the AC component of the filter output to the input of the CMOS inverter of the next stage and stabilize the threshold potential. The output signal is fed back and added.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to an embodiment of the drawings. In FIG. 1, 1 is a CMOS inverter that amplifies an input signal and binarizes it, 2 is a low-pass filter that removes high frequency components from a signal composed of a resistor R ₁ and a capacitor C ₁ , and 3 is an output signal of the low-pass filter 2 again This is a binary CMOS inverter.

FIG. 3 shows each of A, B, C, in the circuit of FIG.
The circuit operation will be described with reference to the signal waveform diagrams at points D and E. The input signal A is a signal whose duty ratio is shifted due to waveform distortion during transmission, and this is input to the CMOS inverter 1 and binarized to become an output B. The output B is input to the low pass filter 2 including the resistor R ₁ and the capacitor C ₂ . The circuit constant of this low-pass filter is set so that the original clock cycle of the input signal is used as a time constant. By attenuating and removing the high frequency component of the clock frequency of the signal B, the filter output C becomes close to a sine wave. . Next, the CMOS inverter 3 inputs and outputs high resistance R ₂
The input of the CMOS inverter 3 becomes the threshold potential of the CMOS inverter 3 by the connection. Here, the output C of the filter 2 has its DC component removed by the capacitor C _{2 and} becomes an output D, and this signal D is input to the CMOS inverter 3. When the signal D with the DC component cut is input to the CMOS inverter 3 whose input is held at the threshold potential, the signal is pulse-shaped and the output signal E becomes a signal with a duty of 50%.

CMOS inverters 1 and 3 used here
Operates with a single power supply as shown in FIG. 2, and in the transfer area, P
Both the type MOS 21 and the N type MOS 22 are in a saturated state, and at the center of the transfer, that is, at the threshold V _DD / 2, almost coincides with the V level of Vout = Vin, so that bias is applied with high resistance feedback from the output to the input. As a result, the input can be stabilized at the threshold.
Further, since the threshold potentials of the P-type MOS 21 and the N-type MOS 22 have mutually opposite temperature coefficients, the temperature coefficient of the threshold is extremely small in the entire CMOS, and therefore the threshold potential E of the CMOS inverter 3 is reduced. Stable duty 50% with little influence on duty
The square signal of can be reproduced.

Further, since the low-pass filter of the capacitor C ₁ uses the clock cycle of the input signal as a time constant, the capacitors C ₁ and C ₂ may have a small capacitance as the high frequency with a large collapse of the duty ratio. Since high precision is not required in terms of circuit usage conditions, it is easy to form an LSI together with a CMOS.

[0011]

As described above, according to the present invention, a simple C
Since the duty can be corrected by the MOS inverter and the primary low-pass filter including the resistor and the capacitor, the circuit configuration can be downsized and the cost can be reduced.

Moreover, since it can be constituted by a CMOS digital IC and a low-pass filter of a small-capacity capacitor, it is an LSI.
It has the effect of enabling conversion.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a detailed view of the CMOS inverter of FIG.

3 is an explanatory diagram of a signal waveform at each point in FIG.

[Explanation of symbols]

1 ... CMOS inverter, 2 ... Low-pass filter, 3 ...
CMOS inverter, 21 ... P-type MOS, 22 ... N-type M
OS.

Claims (1)

[Claims] 1. A CMOS inverter for amplifying an input signal and binarizing the same, a low pass filter for removing a high frequency component from a binarized signal output from the CMOS inverter, and an output signal of the low pass filter again. Two
CMOS with added high-value feedback to input with high resistance
A duty correction circuit comprising an inverter.